[deliverable/linux.git] / arch / arm / mach-ixp2000 / core.c

/*
 * arch/arm/mach-ixp2000/core.c
 *
 * Common routines used by all IXP2400/2800 based platforms.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2004 (C) MontaVista Software, Inc. 
 *
 * Based on work Copyright (C) 2002-2003 Intel Corporation
 * 
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any 
 * warranty of any kind, whether express or implied.
 */
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/bitops.h>
#include <linux/serial_8250.h>
#include <linux/mm.h>
#include <linux/export.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/tlbflush.h>
#include <asm/pgtable.h>

#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>

#include <mach/gpio-ixp2000.h>

static DEFINE_SPINLOCK(ixp2000_slowport_lock);
static unsigned long ixp2000_slowport_irq_flags;

/*************************************************************************
 * Slowport access routines
 *************************************************************************/
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
{
	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);

	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;

	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
}

void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
{
	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);

	spin_unlock_irqrestore(&ixp2000_slowport_lock, 
					ixp2000_slowport_irq_flags);
}

/*************************************************************************
 * Chip specific mappings shared by all IXP2000 systems
 *************************************************************************/
static struct map_desc ixp2000_io_desc[] __initdata = {
	{
		.virtual	= IXP2000_CAP_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
		.length		= IXP2000_CAP_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_INTCTL_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
		.length		= IXP2000_INTCTL_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CREG_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
		.length		= IXP2000_PCI_CREG_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CSR_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
		.length		= IXP2000_PCI_CSR_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_MSF_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
		.length		= IXP2000_MSF_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_SCRATCH_RING_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
		.length		= IXP2000_SCRATCH_RING_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_SRAM0_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
		.length		= IXP2000_SRAM0_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
		.length		= IXP2000_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG0_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
		.length		= IXP2000_PCI_CFG0_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG1_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
		.length		= IXP2000_PCI_CFG1_SIZE,
		.type		= MT_DEVICE,
	}
};

void __init ixp2000_map_io(void)
{
	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));

	/* Set slowport to 8-bit mode.  */
	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
}


/*************************************************************************
 * Serial port support for IXP2000
 *************************************************************************/
static struct plat_serial8250_port ixp2000_serial_port[] = {
	{
		.mapbase	= IXP2000_UART_PHYS_BASE,
		.membase	= (char *)(IXP2000_UART_VIRT_BASE + 3),
		.irq		= IRQ_IXP2000_UART,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 50000000,
	},
	{ },
};

static struct resource ixp2000_uart_resource = {
	.start		= IXP2000_UART_PHYS_BASE,
	.end		= IXP2000_UART_PHYS_BASE + 0x1f,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixp2000_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= ixp2000_serial_port,
	},
	.num_resources	= 1,
	.resource	= &ixp2000_uart_resource,
};

void __init ixp2000_uart_init(void)
{
	platform_device_register(&ixp2000_serial_device);
}


/*************************************************************************
 * Timer-tick functions for IXP2000
 *************************************************************************/
static unsigned ticks_per_jiffy;
static unsigned ticks_per_usec;
static unsigned next_jiffy_time;
static volatile unsigned long *missing_jiffy_timer_csr;

unsigned long ixp2000_gettimeoffset (void)
{
 	unsigned long offset;

	offset = next_jiffy_time - *missing_jiffy_timer_csr;

	return offset / ticks_per_usec;
}

static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
{
	/* clear timer 1 */
	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);

	while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
							>= ticks_per_jiffy) {
		timer_tick();
		next_jiffy_time -= ticks_per_jiffy;
	}

	return IRQ_HANDLED;
}

static struct irqaction ixp2000_timer_irq = {
	.name		= "IXP2000 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= ixp2000_timer_interrupt,
};

void __init ixp2000_init_time(unsigned long tick_rate)
{
	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	ticks_per_usec = tick_rate / 1000000;

	/*
	 * We use timer 1 as our timer interrupt.
	 */
	ixp2000_reg_write(IXP2000_T1_CLR, 0);
	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));

	/*
	 * We use a second timer as a monotonic counter for tracking
	 * missed jiffies.  The IXP2000 has four timers, but if we're
	 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
	 * chips we use timer 4.  Timer 4 is the only timer that can
	 * be used for the watchdog, so we use timer 2 if we're on a
	 * non-buggy chip.
	 */
	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
		printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");

		ixp2000_reg_write(IXP2000_T4_CLR, 0);
		ixp2000_reg_write(IXP2000_T4_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T4_CSR;
	} else {
		ixp2000_reg_write(IXP2000_T2_CLR, 0);
		ixp2000_reg_write(IXP2000_T2_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T2_CSR;
	}
 	next_jiffy_time = 0xffffffff;

	/* register for interrupt */
	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
}

/*************************************************************************
 * GPIO helpers
 *************************************************************************/
static unsigned long GPIO_IRQ_falling_edge;
static unsigned long GPIO_IRQ_rising_edge;
static unsigned long GPIO_IRQ_level_low;
static unsigned long GPIO_IRQ_level_high;

static void update_gpio_int_csrs(void)
{
	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
}

void gpio_line_config(int line, int direction)
{
	unsigned long flags;

	local_irq_save(flags);
	if (direction == GPIO_OUT) {
		/* if it's an output, it ain't an interrupt anymore */
		GPIO_IRQ_falling_edge &= ~(1 << line);
		GPIO_IRQ_rising_edge &= ~(1 << line);
		GPIO_IRQ_level_low &= ~(1 << line);
		GPIO_IRQ_level_high &= ~(1 << line);
		update_gpio_int_csrs();

		ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
	} else if (direction == GPIO_IN) {
		ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
	}
	local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_line_config);


/*************************************************************************
 * IRQ handling IXP2000
 *************************************************************************/
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
{                               
	int i;
	unsigned long status = *IXP2000_GPIO_INST;
		   
	for (i = 0; i <= 7; i++) {
		if (status & (1<<i)) {
			generic_handle_irq(i + IRQ_IXP2000_GPIO0);
		}
	}
}

static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
{
	int line = d->irq - IRQ_IXP2000_GPIO0;

	/*
	 * First, configure this GPIO line as an input.
	 */
	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);

	/*
	 * Then, set the proper trigger type.
	 */
	if (type & IRQ_TYPE_EDGE_FALLING)
		GPIO_IRQ_falling_edge |= 1 << line;
	else
		GPIO_IRQ_falling_edge &= ~(1 << line);
	if (type & IRQ_TYPE_EDGE_RISING)
		GPIO_IRQ_rising_edge |= 1 << line;
	else
		GPIO_IRQ_rising_edge &= ~(1 << line);
	if (type & IRQ_TYPE_LEVEL_LOW)
		GPIO_IRQ_level_low |= 1 << line;
	else
		GPIO_IRQ_level_low &= ~(1 << line);
	if (type & IRQ_TYPE_LEVEL_HIGH)
		GPIO_IRQ_level_high |= 1 << line;
	else
		GPIO_IRQ_level_high &= ~(1 << line);
	update_gpio_int_csrs();

	return 0;
}

static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));

	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_mask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static struct irq_chip ixp2000_GPIO_irq_chip = {
	.irq_ack	= ixp2000_GPIO_irq_mask_ack,
	.irq_mask	= ixp2000_GPIO_irq_mask,
	.irq_unmask	= ixp2000_GPIO_irq_unmask,
	.irq_set_type	= ixp2000_GPIO_irq_type,
};

static void ixp2000_pci_irq_mask(struct irq_data *d)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (d->irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
	else if (d->irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}

static void ixp2000_pci_irq_unmask(struct irq_data *d)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (d->irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
	else if (d->irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}

/*
 * Error interrupts. These are used extensively by the microengine drivers
 */
static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	int i;
	unsigned long status = *IXP2000_IRQ_ERR_STATUS;

	for(i = 31; i >= 0; i--) {
		if(status & (1 << i)) {
			generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
		}
	}
}

static void ixp2000_err_irq_mask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
			(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static void ixp2000_err_irq_unmask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
			(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static struct irq_chip ixp2000_err_irq_chip = {
	.irq_ack	= ixp2000_err_irq_mask,
	.irq_mask	= ixp2000_err_irq_mask,
	.irq_unmask	= ixp2000_err_irq_unmask
};

static struct irq_chip ixp2000_pci_irq_chip = {
	.irq_ack	= ixp2000_pci_irq_mask,
	.irq_mask	= ixp2000_pci_irq_mask,
	.irq_unmask	= ixp2000_pci_irq_unmask
};

static void ixp2000_irq_mask(struct irq_data *d)
{
	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
}

static void ixp2000_irq_unmask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
}

static struct irq_chip ixp2000_irq_chip = {
	.irq_ack	= ixp2000_irq_mask,
	.irq_mask	= ixp2000_irq_mask,
	.irq_unmask	= ixp2000_irq_unmask
};

void __init ixp2000_init_irq(void)
{
	int irq;

	/*
	 * Mask all sources
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);

	/* clear all GPIO edge/level detects */
	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);

	/* clear PCI interrupt sources */
	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);

	/*
	 * Certain bits in the IRQ status register of the 
	 * IXP2000 are reserved. Instead of trying to map
	 * things non 1:1 from bit position to IRQ number,
	 * we mark the reserved IRQs as invalid. This makes
	 * our mask/unmask code much simpler.
	 */
	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
		if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
			irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
						 handle_level_irq);
			set_irq_flags(irq, IRQF_VALID);
		} else set_irq_flags(irq, 0);
	}

	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
		if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
				IXP2000_VALID_ERR_IRQ_MASK) {
			irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
						 handle_level_irq);
			set_irq_flags(irq, IRQF_VALID);
		}
		else
			set_irq_flags(irq, 0);
	}
	irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);

	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
		irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);

	/*
	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in
	 * entry-macro.S, so we don't need a chained handler for the
	 * PCI interrupt source.
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
		irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
}

void ixp2000_restart(char mode, const char *cmd)
{
	ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
}
Commit	Line	Data
1da177e4	1	/*
fa87cedd	2	* arch/arm/mach-ixp2000/core.c
1da177e4 LT	3	*
	4	* Common routines used by all IXP2400/2800 based platforms.
	5	*
	6	* Author: Deepak Saxena <dsaxena@plexity.net>
	7	*
	8	* Copyright 2004 (C) MontaVista Software, Inc.
	9	*
	10	* Based on work Copyright (C) 2002-2003 Intel Corporation
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
2f8163ba	16	#include <linux/gpio.h>
1da177e4 LT	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/sched.h>
	21	#include <linux/interrupt.h>
64ffae8a	22	#include <linux/irq.h>
1da177e4 LT	23	#include <linux/serial.h>
	24	#include <linux/tty.h>
	25	#include <linux/bitops.h>
28187f2c	26	#include <linux/serial_8250.h>
1da177e4	27	#include <linux/mm.h>
dc28094b	28	#include <linux/export.h>
1da177e4 LT	29
	30	#include <asm/types.h>
	31	#include <asm/setup.h>
	32	#include <asm/memory.h>
a09e64fb	33	#include <mach/hardware.h>
1da177e4	34	#include <asm/irq.h>
1da177e4 LT	35	#include <asm/tlbflush.h>
	36	#include <asm/pgtable.h>
	37
	38	#include <asm/mach/map.h>
	39	#include <asm/mach/time.h>
	40	#include <asm/mach/irq.h>
	41
87f911a3 LW	42	#include <mach/gpio-ixp2000.h>
87f911a3 LW	43
1da177e4 LT	44	static DEFINE_SPINLOCK(ixp2000_slowport_lock);
	45	static unsigned long ixp2000_slowport_irq_flags;
	46
	47	/*************************************************************************
	48	* Slowport access routines
	49	*************************************************************************/
	50	void ixp2000_acquire_slowport(struct slowport_cfg new_cfg, struct slowport_cfg old_cfg)
	51	{
1da177e4 LT	52	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
	53
	54	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	55	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	56	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	57	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	58	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
	59
	60	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	61	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	62	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	63	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
e9b72e43	64	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
1da177e4 LT	65	}
	66
	67	void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
	68	{
	69	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	70	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	71	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	72	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
e9b72e43	73	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
1da177e4 LT	74
	75	spin_unlock_irqrestore(&ixp2000_slowport_lock,
	76	ixp2000_slowport_irq_flags);
	77	}
	78
	79	/*************************************************************************
	80	* Chip specific mappings shared by all IXP2000 systems
	81	*************************************************************************/
	82	static struct map_desc ixp2000_io_desc[] __initdata = {
	83	{
	84	.virtual = IXP2000_CAP_VIRT_BASE,
db0d087e	85	.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
1da177e4	86	.length = IXP2000_CAP_SIZE,
db5b7169	87	.type = MT_DEVICE,
1da177e4 LT	88	}, {
1da177e4 LT	89	.virtual = IXP2000_INTCTL_VIRT_BASE,
db0d087e	90	.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
1da177e4	91	.length = IXP2000_INTCTL_SIZE,
db5b7169	92	.type = MT_DEVICE,
1da177e4 LT	93	}, {
1da177e4 LT	94	.virtual = IXP2000_PCI_CREG_VIRT_BASE,
db0d087e	95	.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
1da177e4	96	.length = IXP2000_PCI_CREG_SIZE,
db5b7169	97	.type = MT_DEVICE,
1da177e4 LT	98	}, {
1da177e4 LT	99	.virtual = IXP2000_PCI_CSR_VIRT_BASE,
db0d087e	100	.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
1da177e4	101	.length = IXP2000_PCI_CSR_SIZE,
db5b7169	102	.type = MT_DEVICE,
baaf7ed1 LB	103	}, {
baaf7ed1 LB	104	.virtual = IXP2000_MSF_VIRT_BASE,
db0d087e	105	.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
baaf7ed1	106	.length = IXP2000_MSF_SIZE,
db5b7169	107	.type = MT_DEVICE,
dd29c727 LB	108	}, {
	109	.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
	110	.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
	111	.length = IXP2000_SCRATCH_RING_SIZE,
db5b7169	112	.type = MT_DEVICE,
dd29c727 LB	113	}, {
	114	.virtual = IXP2000_SRAM0_VIRT_BASE,
	115	.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
	116	.length = IXP2000_SRAM0_SIZE,
db5b7169	117	.type = MT_DEVICE,
1da177e4 LT	118	}, {
1da177e4 LT	119	.virtual = IXP2000_PCI_IO_VIRT_BASE,
db0d087e	120	.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
1da177e4	121	.length = IXP2000_PCI_IO_SIZE,
db5b7169	122	.type = MT_DEVICE,
1da177e4 LT	123	}, {
1da177e4 LT	124	.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
db0d087e	125	.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
1da177e4	126	.length = IXP2000_PCI_CFG0_SIZE,
db5b7169	127	.type = MT_DEVICE,
1da177e4 LT	128	}, {
1da177e4 LT	129	.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
db0d087e	130	.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
1da177e4	131	.length = IXP2000_PCI_CFG1_SIZE,
db5b7169	132	.type = MT_DEVICE,
1da177e4 LT	133	}
	134	};
	135
1da177e4 LT	136	void __init ixp2000_map_io(void)
1da177e4 LT	137	{
1da177e4	138	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
1da177e4 LT	139
1da177e4 LT	140	/* Set slowport to 8-bit mode. */
e9b72e43	141	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
1da177e4 LT	142	}
1da177e4 LT	143
28187f2c LB	144
	145	/*************************************************************************
	146	* Serial port support for IXP2000
	147	*************************************************************************/
	148	static struct plat_serial8250_port ixp2000_serial_port[] = {
	149	{
	150	.mapbase = IXP2000_UART_PHYS_BASE,
	151	.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
	152	.irq = IRQ_IXP2000_UART,
	153	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	154	.iotype = UPIO_MEM,
	155	.regshift = 2,
	156	.uartclk = 50000000,
	157	},
	158	{ },
	159	};
	160
	161	static struct resource ixp2000_uart_resource = {
	162	.start = IXP2000_UART_PHYS_BASE,
702c96d5	163	.end = IXP2000_UART_PHYS_BASE + 0x1f,
28187f2c LB	164	.flags = IORESOURCE_MEM,
	165	};
	166
	167	static struct platform_device ixp2000_serial_device = {
	168	.name = "serial8250",
6df29deb	169	.id = PLAT8250_DEV_PLATFORM,
28187f2c LB	170	.dev = {
	171	.platform_data = ixp2000_serial_port,
	172	},
	173	.num_resources = 1,
	174	.resource = &ixp2000_uart_resource,
	175	};
	176
	177	void __init ixp2000_uart_init(void)
	178	{
	179	platform_device_register(&ixp2000_serial_device);
	180	}
	181
	182
1da177e4 LT	183	/*************************************************************************
	184	* Timer-tick functions for IXP2000
	185	*************************************************************************/
	186	static unsigned ticks_per_jiffy;
	187	static unsigned ticks_per_usec;
	188	static unsigned next_jiffy_time;
e4fe1981	189	static volatile unsigned long *missing_jiffy_timer_csr;
1da177e4 LT	190
	191	unsigned long ixp2000_gettimeoffset (void)
	192	{
	193	unsigned long offset;
	194
e4fe1981	195	offset = next_jiffy_time - *missing_jiffy_timer_csr;
1da177e4 LT	196
	197	return offset / ticks_per_usec;
	198	}
	199
d463f363	200	static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
1da177e4	201	{
1da177e4	202	/* clear timer 1 */
e9b72e43	203	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
c4982887	204
f869afab LB	205	while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
f869afab LB	206	>= ticks_per_jiffy) {
0cd61b68	207	timer_tick();
1da177e4 LT	208	next_jiffy_time -= ticks_per_jiffy;
	209	}
	210
1da177e4 LT	211	return IRQ_HANDLED;
	212	}
	213
	214	static struct irqaction ixp2000_timer_irq = {
	215	.name = "IXP2000 Timer Tick",
b30fabad	216	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
09b8b5f8	217	.handler = ixp2000_timer_interrupt,
1da177e4 LT	218	};
	219
	220	void __init ixp2000_init_time(unsigned long tick_rate)
	221	{
1da177e4 LT	222	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	223	ticks_per_usec = tick_rate / 1000000;
	224
e4fe1981 LB	225	/*
	226	* We use timer 1 as our timer interrupt.
	227	*/
	228	ixp2000_reg_write(IXP2000_T1_CLR, 0);
1da177e4 LT	229	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	230	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
	231
	232	/*
e4fe1981 LB	233	* We use a second timer as a monotonic counter for tracking
	234	* missed jiffies. The IXP2000 has four timers, but if we're
	235	* on an A-step IXP2800, timer 2 and 3 don't work, so on those
	236	* chips we use timer 4. Timer 4 is the only timer that can
	237	* be used for the watchdog, so we use timer 2 if we're on a
	238	* non-buggy chip.
1da177e4	239	*/
e4fe1981 LB	240	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
	241	printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
	242
	243	ixp2000_reg_write(IXP2000_T4_CLR, 0);
	244	ixp2000_reg_write(IXP2000_T4_CLD, -1);
e9b72e43	245	ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
e4fe1981 LB	246	missing_jiffy_timer_csr = IXP2000_T4_CSR;
	247	} else {
	248	ixp2000_reg_write(IXP2000_T2_CLR, 0);
	249	ixp2000_reg_write(IXP2000_T2_CLD, -1);
e9b72e43	250	ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
e4fe1981 LB	251	missing_jiffy_timer_csr = IXP2000_T2_CSR;
e4fe1981 LB	252	}
1da177e4 LT	253	next_jiffy_time = 0xffffffff;
	254
	255	/* register for interrupt */
	256	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
	257	}
	258
	259	/*************************************************************************
	260	* GPIO helpers
	261	*************************************************************************/
1da177e4	262	static unsigned long GPIO_IRQ_falling_edge;
c4982887	263	static unsigned long GPIO_IRQ_rising_edge;
1da177e4 LT	264	static unsigned long GPIO_IRQ_level_low;
	265	static unsigned long GPIO_IRQ_level_high;
	266
c4982887 LB	267	static void update_gpio_int_csrs(void)
	268	{
	269	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	270	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	271	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
e9b72e43	272	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
c4982887 LB	273	}
	274
	275	void gpio_line_config(int line, int direction)
1da177e4 LT	276	{
	277	unsigned long flags;
	278
	279	local_irq_save(flags);
c4982887	280	if (direction == GPIO_OUT) {
1da177e4	281	/* if it's an output, it ain't an interrupt anymore */
1da177e4 LT	282	GPIO_IRQ_falling_edge &= ~(1 << line);
	283	GPIO_IRQ_rising_edge &= ~(1 << line);
	284	GPIO_IRQ_level_low &= ~(1 << line);
	285	GPIO_IRQ_level_high &= ~(1 << line);
c4982887 LB	286	update_gpio_int_csrs();
c4982887 LB	287
e9b72e43	288	ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
c4982887	289	} else if (direction == GPIO_IN) {
e9b72e43	290	ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
1da177e4	291	}
1da177e4	292	local_irq_restore(flags);
c4982887	293	}
fc8ea7a1	294	EXPORT_SYMBOL(gpio_line_config);
1da177e4 LT	295
	296
	297	/*************************************************************************
	298	* IRQ handling IXP2000
	299	*************************************************************************/
10dd5ce2	300	static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	301	{
	302	int i;
	303	unsigned long status = *IXP2000_GPIO_INST;
	304
	305	for (i = 0; i <= 7; i++) {
	306	if (status & (1<<i)) {
d8aa0251	307	generic_handle_irq(i + IRQ_IXP2000_GPIO0);
1da177e4 LT	308	}
	309	}
	310	}
	311
6e8f54fa	312	static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
c4982887	313	{
6e8f54fa	314	int line = d->irq - IRQ_IXP2000_GPIO0;
c4982887 LB	315
	316	/*
	317	* First, configure this GPIO line as an input.
	318	*/
	319	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
	320
	321	/*
	322	* Then, set the proper trigger type.
	323	*/
6cab4860	324	if (type & IRQ_TYPE_EDGE_FALLING)
c4982887 LB	325	GPIO_IRQ_falling_edge \|= 1 << line;
	326	else
	327	GPIO_IRQ_falling_edge &= ~(1 << line);
6cab4860	328	if (type & IRQ_TYPE_EDGE_RISING)
c4982887 LB	329	GPIO_IRQ_rising_edge \|= 1 << line;
	330	else
	331	GPIO_IRQ_rising_edge &= ~(1 << line);
6cab4860	332	if (type & IRQ_TYPE_LEVEL_LOW)
c4982887 LB	333	GPIO_IRQ_level_low \|= 1 << line;
	334	else
	335	GPIO_IRQ_level_low &= ~(1 << line);
6cab4860	336	if (type & IRQ_TYPE_LEVEL_HIGH)
c4982887 LB	337	GPIO_IRQ_level_high \|= 1 << line;
	338	else
	339	GPIO_IRQ_level_high &= ~(1 << line);
	340	update_gpio_int_csrs();
	341
c4982887 LB	342	return 0;
	343	}
	344
6e8f54fa	345	static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
1da177e4	346	{
6e8f54fa LB	347	unsigned int irq = d->irq;
6e8f54fa LB	348
1da177e4	349	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
c4982887 LB	350
	351	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	352	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
e9b72e43	353	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	354	}
1da177e4 LT	355
6e8f54fa	356	static void ixp2000_GPIO_irq_mask(struct irq_data *d)
1da177e4	357	{
6e8f54fa LB	358	unsigned int irq = d->irq;
6e8f54fa LB	359
e9b72e43	360	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	361	}
1da177e4 LT	362
6e8f54fa	363	static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
1da177e4	364	{
6e8f54fa LB	365	unsigned int irq = d->irq;
6e8f54fa LB	366
1da177e4 LT	367	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	368	}
	369
10dd5ce2	370	static struct irq_chip ixp2000_GPIO_irq_chip = {
6e8f54fa LB	371	.irq_ack = ixp2000_GPIO_irq_mask_ack,
	372	.irq_mask = ixp2000_GPIO_irq_mask,
	373	.irq_unmask = ixp2000_GPIO_irq_unmask,
	374	.irq_set_type = ixp2000_GPIO_irq_type,
1da177e4 LT	375	};
1da177e4 LT	376
6e8f54fa	377	static void ixp2000_pci_irq_mask(struct irq_data *d)
1da177e4 LT	378	{
1da177e4 LT	379	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
6e8f54fa	380	if (d->irq == IRQ_IXP2000_PCIA)
e9b72e43	381	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
6e8f54fa	382	else if (d->irq == IRQ_IXP2000_PCIB)
e9b72e43	383	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
1da177e4 LT	384	}
1da177e4 LT	385
6e8f54fa	386	static void ixp2000_pci_irq_unmask(struct irq_data *d)
1da177e4 LT	387	{
1da177e4 LT	388	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
6e8f54fa	389	if (d->irq == IRQ_IXP2000_PCIA)
1da177e4	390	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 26)));
6e8f54fa	391	else if (d->irq == IRQ_IXP2000_PCIB)
1da177e4 LT	392	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 27)));
	393	}
	394
7866f649 DJ	395	/*
	396	* Error interrupts. These are used extensively by the microengine drivers
	397	*/
10dd5ce2	398	static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
7866f649 DJ	399	{
	400	int i;
	401	unsigned long status = *IXP2000_IRQ_ERR_STATUS;
	402
	403	for(i = 31; i >= 0; i--) {
	404	if(status & (1 << i)) {
d8aa0251	405	generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
7866f649 DJ	406	}
	407	}
	408	}
	409
6e8f54fa	410	static void ixp2000_err_irq_mask(struct irq_data *d)
7866f649 DJ	411	{
7866f649 DJ	412	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
6e8f54fa	413	(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
7866f649 DJ	414	}
7866f649 DJ	415
6e8f54fa	416	static void ixp2000_err_irq_unmask(struct irq_data *d)
7866f649 DJ	417	{
7866f649 DJ	418	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
6e8f54fa	419	(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
7866f649 DJ	420	}
7866f649 DJ	421
10dd5ce2	422	static struct irq_chip ixp2000_err_irq_chip = {
6e8f54fa LB	423	.irq_ack = ixp2000_err_irq_mask,
	424	.irq_mask = ixp2000_err_irq_mask,
	425	.irq_unmask = ixp2000_err_irq_unmask
7866f649 DJ	426	};
7866f649 DJ	427
10dd5ce2	428	static struct irq_chip ixp2000_pci_irq_chip = {
6e8f54fa LB	429	.irq_ack = ixp2000_pci_irq_mask,
	430	.irq_mask = ixp2000_pci_irq_mask,
	431	.irq_unmask = ixp2000_pci_irq_unmask
1da177e4 LT	432	};
1da177e4 LT	433
6e8f54fa	434	static void ixp2000_irq_mask(struct irq_data *d)
1da177e4	435	{
6e8f54fa	436	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
1da177e4 LT	437	}
1da177e4 LT	438
6e8f54fa	439	static void ixp2000_irq_unmask(struct irq_data *d)
1da177e4	440	{
6e8f54fa	441	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
1da177e4 LT	442	}
1da177e4 LT	443
10dd5ce2	444	static struct irq_chip ixp2000_irq_chip = {
6e8f54fa LB	445	.irq_ack = ixp2000_irq_mask,
	446	.irq_mask = ixp2000_irq_mask,
	447	.irq_unmask = ixp2000_irq_unmask
1da177e4 LT	448	};
	449
	450	void __init ixp2000_init_irq(void)
	451	{
	452	int irq;
	453
	454	/*
	455	* Mask all sources
	456	*/
	457	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	458	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
	459
	460	/* clear all GPIO edge/level detects */
	461	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	462	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	463	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	464	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	465	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
	466
	467	/* clear PCI interrupt sources */
e9b72e43	468	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
1da177e4 LT	469
	470	/*
	471	* Certain bits in the IRQ status register of the
	472	* IXP2000 are reserved. Instead of trying to map
	473	* things non 1:1 from bit position to IRQ number,
	474	* we mark the reserved IRQs as invalid. This makes
	475	* our mask/unmask code much simpler.
	476	*/
	477	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
c4982887	478	if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
f38c02f3 TG	479	irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
f38c02f3 TG	480	handle_level_irq);
1da177e4 LT	481	set_irq_flags(irq, IRQF_VALID);
	482	} else set_irq_flags(irq, 0);
	483	}
c4982887	484
7866f649 DJ	485	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
	486	if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
	487	IXP2000_VALID_ERR_IRQ_MASK) {
f38c02f3 TG	488	irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
f38c02f3 TG	489	handle_level_irq);
7866f649 DJ	490	set_irq_flags(irq, IRQF_VALID);
	491	}
	492	else
	493	set_irq_flags(irq, 0);
	494	}
6845664a	495	irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
7866f649	496
1da177e4	497	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
f38c02f3 TG	498	irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
f38c02f3 TG	499	handle_level_irq);
bd115ea0	500	set_irq_flags(irq, IRQF_VALID);
1da177e4	501	}
6845664a	502	irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
1da177e4 LT	503
	504	/*
	505	* Enable PCI irqs. The actual PCI[AB] decoding is done in
	506	* entry-macro.S, so we don't need a chained handler for the
	507	* PCI interrupt source.
	508	*/
	509	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	510	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
f38c02f3 TG	511	irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
f38c02f3 TG	512	handle_level_irq);
1da177e4 LT	513	set_irq_flags(irq, IRQF_VALID);
	514	}
	515	}
	516
1139b926 RK	517	void ixp2000_restart(char mode, const char *cmd)
	518	{
	519	ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
	520	}