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c4713074 LB |
1 | /* |
2 | * arch/arm/mach-ixp23xx/pci.c | |
3 | * | |
4 | * PCI routines for IXP23XX based systems | |
5 | * | |
6 | * Copyright (c) 2005 MontaVista Software, Inc. | |
7 | * | |
8 | * based on original code: | |
9 | * | |
10 | * Author: Naeem Afzal <naeem.m.afzal@intel.com> | |
11 | * Copyright 2002-2005 Intel Corp. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
c4713074 LB |
19 | #include <linux/sched.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ioport.h> | |
c4713074 | 26 | #include <linux/delay.h> |
fced80c7 | 27 | #include <linux/io.h> |
c4713074 | 28 | |
c4713074 LB |
29 | #include <asm/irq.h> |
30 | #include <asm/sizes.h> | |
c4713074 | 31 | #include <asm/mach/pci.h> |
a09e64fb | 32 | #include <mach/hardware.h> |
c4713074 LB |
33 | |
34 | extern int (*external_fault) (unsigned long, struct pt_regs *); | |
35 | ||
46156e04 | 36 | static volatile int pci_master_aborts = 0; |
c4713074 LB |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x...) printk(x) | |
40 | #else | |
41 | #define DBG(x...) | |
42 | #endif | |
43 | ||
44 | int clear_master_aborts(void); | |
45 | ||
46 | static u32 | |
47 | *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) | |
48 | { | |
49 | u32 *paddress; | |
50 | ||
51 | /* | |
52 | * Must be dword aligned | |
53 | */ | |
54 | where &= ~3; | |
55 | ||
56 | /* | |
57 | * For top bus, generate type 0, else type 1 | |
58 | */ | |
59 | if (!bus_nr) { | |
60 | if (PCI_SLOT(devfn) >= 8) | |
61 | return 0; | |
62 | ||
63 | paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT | |
64 | | (1 << (PCI_SLOT(devfn) + 16)) | |
65 | | (PCI_FUNC(devfn) << 8) | where); | |
66 | } else { | |
67 | paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT | |
68 | | (bus_nr << 16) | |
69 | | (PCI_SLOT(devfn) << 11) | |
70 | | (PCI_FUNC(devfn) << 8) | where); | |
71 | } | |
72 | ||
73 | return paddress; | |
74 | } | |
75 | ||
76 | /* | |
77 | * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. | |
78 | * 0 and 3 are not valid indexes... | |
79 | */ | |
80 | static u32 bytemask[] = { | |
81 | /*0*/ 0, | |
82 | /*1*/ 0xff, | |
83 | /*2*/ 0xffff, | |
84 | /*3*/ 0, | |
85 | /*4*/ 0xffffffff, | |
86 | }; | |
87 | ||
88 | static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
89 | int where, int size, u32 *value) | |
90 | { | |
91 | u32 n; | |
92 | u32 *addr; | |
93 | ||
94 | n = where % 4; | |
95 | ||
96 | DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where, | |
97 | bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
98 | ||
99 | addr = ixp23xx_pci_config_addr(bus->number, devfn, where); | |
100 | if (!addr) | |
101 | return PCIBIOS_DEVICE_NOT_FOUND; | |
102 | ||
103 | pci_master_aborts = 0; | |
104 | *value = (*addr >> (8*n)) & bytemask[size]; | |
105 | if (pci_master_aborts) { | |
106 | pci_master_aborts = 0; | |
107 | *value = 0xffffffff; | |
108 | return PCIBIOS_DEVICE_NOT_FOUND; | |
109 | } | |
110 | ||
111 | return PCIBIOS_SUCCESSFUL; | |
112 | } | |
113 | ||
114 | /* | |
115 | * We don't do error checking on the address for writes. | |
116 | * It's assumed that the user checked for the device existing first | |
117 | * by doing a read first. | |
118 | */ | |
119 | static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
120 | int where, int size, u32 value) | |
121 | { | |
122 | u32 mask; | |
123 | u32 *addr; | |
124 | u32 temp; | |
125 | ||
126 | mask = ~(bytemask[size] << ((where % 0x4) * 8)); | |
127 | addr = ixp23xx_pci_config_addr(bus->number, devfn, where); | |
128 | if (!addr) | |
129 | return PCIBIOS_DEVICE_NOT_FOUND; | |
130 | temp = (u32) (value) << ((where % 0x4) * 8); | |
131 | *addr = (*addr & mask) | temp; | |
132 | ||
133 | clear_master_aborts(); | |
134 | ||
135 | return PCIBIOS_SUCCESSFUL; | |
136 | } | |
137 | ||
138 | struct pci_ops ixp23xx_pci_ops = { | |
139 | .read = ixp23xx_pci_read_config, | |
140 | .write = ixp23xx_pci_write_config, | |
141 | }; | |
142 | ||
143 | struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) | |
144 | { | |
37d15909 BH |
145 | return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, |
146 | sysdata, &sysdata->resources); | |
c4713074 LB |
147 | } |
148 | ||
149 | int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | |
150 | { | |
151 | volatile unsigned long temp; | |
152 | unsigned long flags; | |
153 | ||
154 | pci_master_aborts = 1; | |
155 | ||
156 | local_irq_save(flags); | |
157 | temp = *IXP23XX_PCI_CONTROL; | |
158 | ||
159 | /* | |
160 | * master abort and cmd tgt err | |
161 | */ | |
162 | if (temp & ((1 << 8) | (1 << 5))) | |
163 | *IXP23XX_PCI_CONTROL = temp; | |
164 | ||
165 | temp = *IXP23XX_PCI_CMDSTAT; | |
166 | ||
167 | if (temp & (1 << 29)) | |
168 | *IXP23XX_PCI_CMDSTAT = temp; | |
169 | local_irq_restore(flags); | |
170 | ||
171 | /* | |
172 | * If it was an imprecise abort, then we need to correct the | |
173 | * return address to be _after_ the instruction. | |
174 | */ | |
175 | if (fsr & (1 << 10)) | |
176 | regs->ARM_pc += 4; | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | int clear_master_aborts(void) | |
182 | { | |
183 | volatile u32 temp; | |
184 | ||
185 | temp = *IXP23XX_PCI_CONTROL; | |
186 | ||
187 | /* | |
188 | * master abort and cmd tgt err | |
189 | */ | |
190 | if (temp & ((1 << 8) | (1 << 5))) | |
191 | *IXP23XX_PCI_CONTROL = temp; | |
192 | ||
193 | temp = *IXP23XX_PCI_CMDSTAT; | |
194 | ||
195 | if (temp & (1 << 29)) | |
196 | *IXP23XX_PCI_CMDSTAT = temp; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
532bda5d | 201 | static void __init ixp23xx_pci_common_init(void) |
c4713074 LB |
202 | { |
203 | #ifdef __ARMEB__ | |
204 | *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */ | |
205 | #endif | |
206 | /* | |
207 | * ADDR_31 needs to be clear for PCI memory access to CPP memory | |
208 | */ | |
209 | *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31; | |
210 | *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF; | |
211 | ||
212 | /* | |
213 | * Select correct memory for PCI inbound transactions | |
214 | */ | |
215 | if (ixp23xx_cpp_boot()) { | |
216 | *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1); | |
217 | } else { | |
218 | *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); | |
23759dc6 LB |
219 | |
220 | /* | |
221 | * Enable coherency on A2 silicon. | |
222 | */ | |
223 | if (arch_is_coherent()) | |
224 | *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF; | |
c4713074 | 225 | } |
532bda5d LB |
226 | } |
227 | ||
228 | void __init ixp23xx_pci_preinit(void) | |
229 | { | |
c9d95fbe RH |
230 | pcibios_min_io = 0; |
231 | pcibios_min_mem = 0xe0000000; | |
232 | ||
dc8d966b RH |
233 | pci_set_flags(0); |
234 | ||
532bda5d | 235 | ixp23xx_pci_common_init(); |
c4713074 | 236 | |
6338a6aa | 237 | hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0, |
c4713074 LB |
238 | "PCI config cycle to non-existent device"); |
239 | ||
240 | *IXP23XX_PCI_ADDR_EXT = 0x0000e000; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Prevent PCI layer from seeing the inbound host-bridge resources | |
245 | */ | |
246 | static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev) | |
247 | { | |
248 | int i; | |
249 | ||
250 | dev->class &= 0xff; | |
251 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | |
252 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
253 | dev->resource[i].start = 0; | |
254 | dev->resource[i].end = 0; | |
255 | dev->resource[i].flags = 0; | |
256 | } | |
257 | } | |
258 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx); | |
259 | ||
260 | /* | |
261 | * IXP2300 systems often have large resource requirements, so we just | |
262 | * use our own resource space. | |
263 | */ | |
264 | static struct resource ixp23xx_pci_mem_space = { | |
265 | .start = IXP23XX_PCI_MEM_START, | |
266 | .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1, | |
267 | .flags = IORESOURCE_MEM, | |
268 | .name = "PCI Mem Space" | |
269 | }; | |
270 | ||
271 | static struct resource ixp23xx_pci_io_space = { | |
272 | .start = 0x00000100, | |
273 | .end = 0x01ffffff, | |
274 | .flags = IORESOURCE_IO, | |
275 | .name = "PCI I/O Space" | |
276 | }; | |
277 | ||
278 | int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) | |
279 | { | |
280 | if (nr >= 1) | |
281 | return 0; | |
282 | ||
37d15909 BH |
283 | pci_add_resource(&sys->resources, &ixp23xx_pci_io_space); |
284 | pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space); | |
c4713074 LB |
285 | |
286 | return 1; | |
287 | } | |
532bda5d | 288 | |
cdea4606 | 289 | void __init ixp23xx_pci_slave_init(void) |
532bda5d LB |
290 | { |
291 | ixp23xx_pci_common_init(); | |
292 | } |