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1da177e4 LT |
1 | if ARCH_IXP4XX |
2 | ||
3 | config ARCH_SUPPORTS_BIG_ENDIAN | |
4 | bool | |
5 | default y | |
6 | ||
7 | menu "Intel IXP4xx Implementation Options" | |
8 | ||
9 | comment "IXP4xx Platforms" | |
10 | ||
11 | config ARCH_AVILA | |
12 | bool "Avila" | |
13 | help | |
14 | Say 'Y' here if you want your kernel to support the Gateworks | |
15 | Avila Network Platform. For more information on this platform, | |
16 | see <file:Documentation/arm/IXP4xx>. | |
17 | ||
18 | config ARCH_ADI_COYOTE | |
19 | bool "Coyote" | |
20 | help | |
21 | Say 'Y' here if you want your kernel to support the ADI | |
22 | Engineering Coyote Gateway Reference Platform. For more | |
23 | information on this platform, see <file:Documentation/arm/IXP4xx>. | |
24 | ||
25 | config ARCH_IXDP425 | |
26 | bool "IXDP425" | |
27 | help | |
28 | Say 'Y' here if you want your kernel to support Intel's | |
29 | IXDP425 Development Platform (Also known as Richfield). | |
30 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. | |
31 | ||
32 | config MACH_IXDPG425 | |
33 | bool "IXDPG425" | |
34 | help | |
35 | Say 'Y' here if you want your kernel to support Intel's | |
36 | IXDPG425 Development Platform (Also known as Montajade). | |
37 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. | |
38 | ||
39 | config MACH_IXDP465 | |
40 | bool "IXDP465" | |
41 | help | |
42 | Say 'Y' here if you want your kernel to support Intel's | |
43 | IXDP465 Development Platform (Also known as BMP). | |
7aa52f51 | 44 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. |
1da177e4 LT |
45 | |
46 | ||
47 | # | |
48 | # IXCDP1100 is the exact same HW as IXDP425, but with a different machine | |
49 | # number from the bootloader due to marketing monkeys, so we just enable it | |
50 | # by default if IXDP425 is enabled. | |
51 | # | |
52 | config ARCH_IXCDP1100 | |
53 | bool | |
54 | depends on ARCH_IXDP425 | |
55 | default y | |
56 | ||
57 | config ARCH_PRPMC1100 | |
58 | bool "PrPMC1100" | |
59 | help | |
60 | Say 'Y' here if you want your kernel to support the Motorola | |
61 | PrPCM1100 Processor Mezanine Module. For more information on | |
62 | this platform, see <file:Documentation/arm/IXP4xx>. | |
63 | ||
64 | # | |
65 | # Avila and IXDP share the same source for now. Will change in future | |
66 | # | |
67 | config ARCH_IXDP4XX | |
68 | bool | |
69 | depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465 | |
70 | default y | |
71 | ||
72 | # | |
73 | # Certain registers and IRQs are only enabled if supporting IXP465 CPUs | |
74 | # | |
75 | config CPU_IXP46X | |
76 | bool | |
77 | depends on MACH_IXDP465 | |
78 | default y | |
79 | ||
80 | config MACH_GTWX5715 | |
81 | bool "Gemtek WX5715 (Linksys WRV54G)" | |
82 | depends on ARCH_IXP4XX | |
83 | help | |
84 | This board is currently inside the Linksys WRV54G Gateways. | |
85 | ||
86 | IXP425 - 266mhz | |
87 | 32mb SDRAM | |
88 | 8mb Flash | |
89 | miniPCI slot 0 does not have a card connector soldered to the board | |
90 | miniPCI slot 1 has an ISL3880 802.11g card (Prism54) | |
91 | npe0 is connected to a Kendin KS8995M Switch (4 ports) | |
92 | npe1 is the "wan" port | |
93 | "Console" UART is available on J11 as console | |
94 | "High Speed" UART is n/c (as far as I can tell) | |
95 | 20 Pin ARM/Xscale JTAG interface on J2 | |
96 | ||
97 | ||
98 | comment "IXP4xx Options" | |
99 | ||
100 | config IXP4XX_INDIRECT_PCI | |
101 | bool "Use indirect PCI memory access" | |
102 | help | |
103 | IXP4xx provides two methods of accessing PCI memory space: | |
104 | ||
105 | 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
106 | To access PCI via this space, we simply ioremap() the BAR | |
107 | into the kernel and we can use the standard read[bwl]/write[bwl] | |
108 | macros. This is the preferred method due to speed but it | |
109 | limits the system to just 64MB of PCI memory. This can be | |
110 | problamatic if using video cards and other memory-heavy devices. | |
111 | ||
112 | 2) If > 64MB of memory space is required, the IXP4xx can be | |
113 | configured to use indirect registers to access PCI This allows | |
114 | for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. | |
115 | The disadvantadge of this is that every PCI access requires | |
116 | three local register accesses plus a spinlock, but in some | |
117 | cases the performance hit is acceptable. In addition, you cannot | |
118 | mmap() PCI devices in this case due to the indirect nature | |
119 | of the PCI window. | |
120 | ||
121 | By default, the direct method is used. Choose this option if you | |
122 | need to use the indirect method instead. If you don't know | |
123 | what you need, leave this option unselected. | |
124 | ||
125 | endmenu | |
126 | ||
127 | endif |