[deliverable/linux.git] / arch / arm / mach-ixp4xx / ixdp425-setup.c

/*
 * arch/arm/mach-ixp4xx/ixdp425-setup.c
 *
 * IXDP425/IXCDP1100 board-setup
 *
 * Copyright (C) 2003-2005 MontaVista Software, Inc.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>

#define IXDP425_SDA_PIN		7
#define IXDP425_SCL_PIN		6

/* NAND Flash pins */
#define IXDP425_NAND_NCE_PIN	12

#define IXDP425_NAND_CMD_BYTE	0x01
#define IXDP425_NAND_ADDR_BYTE	0x02

static struct flash_platform_data ixdp425_flash_data = {
	.map_name	= "cfi_probe",
	.width		= 2,
};

static struct resource ixdp425_flash_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp425_flash = {
	.name		= "IXP4XX-Flash",
	.id		= 0,
	.dev		= {
		.platform_data = &ixdp425_flash_data,
	},
	.num_resources	= 1,
	.resource	= &ixdp425_flash_resource,
};

#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)

#ifdef CONFIG_MTD_PARTITIONS
const char *part_probes[] = { "cmdlinepart", NULL };

static struct mtd_partition ixdp425_partitions[] = {
	{
		.name	= "ixp400 NAND FS 0",
		.offset	= 0,
		.size 	= SZ_8M
	}, {
		.name	= "ixp400 NAND FS 1",
		.offset	= MTDPART_OFS_APPEND,
		.size	= MTDPART_SIZ_FULL
	},
};
#endif

static void
ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *this = mtd->priv;
	int offset = (int)this->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_NCE) {
			gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
			udelay(5);
		} else
			gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);

		offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
		offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
		this->priv = (void *)offset;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, this->IO_ADDR_W + offset);
}

static struct platform_nand_data ixdp425_flash_nand_data = {
	.chip = {
		.nr_chips		= 1,
		.chip_delay		= 30,
		.options		= NAND_NO_AUTOINCR,
#ifdef CONFIG_MTD_PARTITIONS
		.part_probe_types 	= part_probes,
		.partitions	 	= ixdp425_partitions,
		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
#endif
	},
	.ctrl = {
		.cmd_ctrl 		= ixdp425_flash_nand_cmd_ctrl
	}
};

static struct resource ixdp425_flash_nand_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp425_flash_nand = {
	.name		= "gen_nand",
	.id		= -1,
	.dev		= {
		.platform_data = &ixdp425_flash_nand_data,
	},
	.num_resources	= 1,
	.resource	= &ixdp425_flash_nand_resource,
};
#endif	/* CONFIG_MTD_NAND_PLATFORM */

static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
	.sda_pin	= IXDP425_SDA_PIN,
	.scl_pin	= IXDP425_SCL_PIN,
};

static struct platform_device ixdp425_i2c_gpio = {
	.name		= "i2c-gpio",
	.id		= 0,
	.dev	 = {
		.platform_data	= &ixdp425_i2c_gpio_data,
	},
};

static struct resource ixdp425_uart_resources[] = {
	{
		.start		= IXP4XX_UART1_BASE_PHYS,
		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM
	},
	{
		.start		= IXP4XX_UART2_BASE_PHYS,
		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM
	}
};

static struct plat_serial8250_port ixdp425_uart_data[] = {
	{
		.mapbase	= IXP4XX_UART1_BASE_PHYS,
		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{
		.mapbase	= IXP4XX_UART2_BASE_PHYS,
		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{ },
};

static struct platform_device ixdp425_uart = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev.platform_data	= ixdp425_uart_data,
	.num_resources		= 2,
	.resource		= ixdp425_uart_resources
};

/* Built-in 10/100 Ethernet MAC interfaces */
static struct eth_plat_info ixdp425_plat_eth[] = {
	{
		.phy		= 0,
		.rxq		= 3,
		.txreadyq	= 20,
	}, {
		.phy		= 1,
		.rxq		= 4,
		.txreadyq	= 21,
	}
};

static struct platform_device ixdp425_eth[] = {
	{
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEB,
		.dev.platform_data	= ixdp425_plat_eth,
	}, {
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEC,
		.dev.platform_data	= ixdp425_plat_eth + 1,
	}
};

static struct platform_device *ixdp425_devices[] __initdata = {
	&ixdp425_i2c_gpio,
	&ixdp425_flash,
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	&ixdp425_flash_nand,
#endif
	&ixdp425_uart,
	&ixdp425_eth[0],
	&ixdp425_eth[1],
};

static void __init ixdp425_init(void)
{
	ixp4xx_sys_init();

	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	ixdp425_flash_resource.end =
		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;

#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
	ixdp425_flash_nand_resource.end   = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;

	gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);

	/* Configure expansion bus for NAND Flash */
	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
			  IXP4XX_EXP_BUS_STROBE_T(1) |	/* extend by 1 clock */
			  IXP4XX_EXP_BUS_CYCLES(0) |	/* Intel cycles */
			  IXP4XX_EXP_BUS_SIZE(0) |	/* 512bytes addr space*/
			  IXP4XX_EXP_BUS_WR_EN |
			  IXP4XX_EXP_BUS_BYTE_EN;	/* 8 bit data bus */
#endif

	if (cpu_is_ixp43x()) {
		ixdp425_uart.num_resources = 1;
		ixdp425_uart_data[1].flags = 0;
	}

	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}

#ifdef CONFIG_ARCH_IXDP425
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_MACH_IXDP465
MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_ARCH_PRPMC1100
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_MACH_KIXRP435
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp4xx/ixdp425-setup.c
	3	*
9bf4d676	4	* IXDP425/IXCDP1100 board-setup
1da177e4 LT	5	*
	6	* Copyright (C) 2003-2005 MontaVista Software, Inc.
	7	*
	8	* Author: Deepak Saxena <dsaxena@plexity.net>
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/device.h>
	14	#include <linux/serial.h>
	15	#include <linux/tty.h>
	16	#include <linux/serial_8250.h>
5a4a2387	17	#include <linux/i2c-gpio.h>
4ad48b4b VB	18	#include <linux/io.h>
	19	#include <linux/mtd/mtd.h>
	20	#include <linux/mtd/nand.h>
	21	#include <linux/mtd/partitions.h>
8029db12	22	#include <linux/delay.h>
1da177e4 LT	23	#include <asm/types.h>
	24	#include <asm/setup.h>
	25	#include <asm/memory.h>
a09e64fb	26	#include <mach/hardware.h>
1da177e4 LT	27	#include <asm/mach-types.h>
	28	#include <asm/irq.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/flash.h>
	31
9bf4d676 KH	32	#define IXDP425_SDA_PIN 7
	33	#define IXDP425_SCL_PIN 6
	34
	35	/* NAND Flash pins */
	36	#define IXDP425_NAND_NCE_PIN 12
	37
	38	#define IXDP425_NAND_CMD_BYTE 0x01
	39	#define IXDP425_NAND_ADDR_BYTE 0x02
	40
1da177e4 LT	41	static struct flash_platform_data ixdp425_flash_data = {
	42	.map_name = "cfi_probe",
	43	.width = 2,
	44	};
	45
	46	static struct resource ixdp425_flash_resource = {
1da177e4 LT	47	.flags = IORESOURCE_MEM,
	48	};
	49
	50	static struct platform_device ixdp425_flash = {
	51	.name = "IXP4XX-Flash",
	52	.id = 0,
	53	.dev = {
	54	.platform_data = &ixdp425_flash_data,
	55	},
	56	.num_resources = 1,
	57	.resource = &ixdp425_flash_resource,
	58	};
	59
4ad48b4b VB	60	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	61	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	62
	63	#ifdef CONFIG_MTD_PARTITIONS
	64	const char *part_probes[] = { "cmdlinepart", NULL };
	65
	66	static struct mtd_partition ixdp425_partitions[] = {
	67	{
	68	.name = "ixp400 NAND FS 0",
	69	.offset = 0,
	70	.size = SZ_8M
	71	}, {
	72	.name = "ixp400 NAND FS 1",
	73	.offset = MTDPART_OFS_APPEND,
	74	.size = MTDPART_SIZ_FULL
	75	},
	76	};
	77	#endif
	78
	79	static void
	80	ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	81	{
	82	struct nand_chip *this = mtd->priv;
	83	int offset = (int)this->priv;
	84
	85	if (ctrl & NAND_CTRL_CHANGE) {
	86	if (ctrl & NAND_NCE) {
	87	gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
	88	udelay(5);
	89	} else
	90	gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
	91
	92	offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
	93	offset \|= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
	94	this->priv = (void *)offset;
	95	}
	96
	97	if (cmd != NAND_CMD_NONE)
	98	writeb(cmd, this->IO_ADDR_W + offset);
	99	}
	100
	101	static struct platform_nand_data ixdp425_flash_nand_data = {
	102	.chip = {
ef077179	103	.nr_chips = 1,
4ad48b4b VB	104	.chip_delay = 30,
	105	.options = NAND_NO_AUTOINCR,
	106	#ifdef CONFIG_MTD_PARTITIONS
	107	.part_probe_types = part_probes,
	108	.partitions = ixdp425_partitions,
	109	.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
	110	#endif
	111	},
	112	.ctrl = {
	113	.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
	114	}
	115	};
	116
	117	static struct resource ixdp425_flash_nand_resource = {
	118	.flags = IORESOURCE_MEM,
	119	};
	120
	121	static struct platform_device ixdp425_flash_nand = {
	122	.name = "gen_nand",
	123	.id = -1,
	124	.dev = {
	125	.platform_data = &ixdp425_flash_nand_data,
	126	},
	127	.num_resources = 1,
	128	.resource = &ixdp425_flash_nand_resource,
	129	};
	130	#endif /* CONFIG_MTD_NAND_PLATFORM */
	131
5a4a2387	132	static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
1da177e4 LT	133	.sda_pin = IXDP425_SDA_PIN,
	134	.scl_pin = IXDP425_SCL_PIN,
	135	};
	136
5a4a2387 MLJ	137	static struct platform_device ixdp425_i2c_gpio = {
5a4a2387 MLJ	138	.name = "i2c-gpio",
1da177e4	139	.id = 0,
5a4a2387 MLJ	140	.dev = {
5a4a2387 MLJ	141	.platform_data = &ixdp425_i2c_gpio_data,
1da177e4	142	},
1da177e4 LT	143	};
	144
	145	static struct resource ixdp425_uart_resources[] = {
	146	{
	147	.start = IXP4XX_UART1_BASE_PHYS,
	148	.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
	149	.flags = IORESOURCE_MEM
	150	},
	151	{
	152	.start = IXP4XX_UART2_BASE_PHYS,
	153	.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
	154	.flags = IORESOURCE_MEM
	155	}
	156	};
	157
	158	static struct plat_serial8250_port ixdp425_uart_data[] = {
	159	{
	160	.mapbase = IXP4XX_UART1_BASE_PHYS,
	161	.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
	162	.irq = IRQ_IXP4XX_UART1,
8c741ed7	163	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	164	.iotype = UPIO_MEM,
	165	.regshift = 2,
	166	.uartclk = IXP4XX_UART_XTAL,
	167	},
	168	{
	169	.mapbase = IXP4XX_UART2_BASE_PHYS,
	170	.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
a35d6c91	171	.irq = IRQ_IXP4XX_UART2,
8c741ed7	172	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	173	.iotype = UPIO_MEM,
	174	.regshift = 2,
	175	.uartclk = IXP4XX_UART_XTAL,
bcaafbe4 SS	176	},
bcaafbe4 SS	177	{ },
1da177e4 LT	178	};
	179
	180	static struct platform_device ixdp425_uart = {
	181	.name = "serial8250",
6df29deb	182	.id = PLAT8250_DEV_PLATFORM,
1da177e4 LT	183	.dev.platform_data = ixdp425_uart_data,
	184	.num_resources = 2,
	185	.resource = ixdp425_uart_resources
	186	};
	187
78225913 RW	188	/* Built-in 10/100 Ethernet MAC interfaces */
	189	static struct eth_plat_info ixdp425_plat_eth[] = {
	190	{
	191	.phy = 0,
	192	.rxq = 3,
	193	.txreadyq = 20,
	194	}, {
	195	.phy = 1,
	196	.rxq = 4,
	197	.txreadyq = 21,
	198	}
	199	};
	200
	201	static struct platform_device ixdp425_eth[] = {
	202	{
	203	.name = "ixp4xx_eth",
	204	.id = IXP4XX_ETH_NPEB,
	205	.dev.platform_data = ixdp425_plat_eth,
	206	}, {
	207	.name = "ixp4xx_eth",
	208	.id = IXP4XX_ETH_NPEC,
	209	.dev.platform_data = ixdp425_plat_eth + 1,
	210	}
	211	};
	212
1da177e4	213	static struct platform_device *ixdp425_devices[] __initdata = {
5a4a2387	214	&ixdp425_i2c_gpio,
1da177e4	215	&ixdp425_flash,
4ad48b4b VB	216	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	217	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	218	&ixdp425_flash_nand,
	219	#endif
78225913 RW	220	&ixdp425_uart,
	221	&ixdp425_eth[0],
	222	&ixdp425_eth[1],
1da177e4 LT	223	};
1da177e4 LT	224
1da177e4 LT	225	static void __init ixdp425_init(void)
	226	{
	227	ixp4xx_sys_init();
	228
54e269ea DS	229	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	230	ixdp425_flash_resource.end =
	231	IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
1da177e4	232
4ad48b4b VB	233	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	234	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	235	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
	236	ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
	237
	238	gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
	239
	240	/* Configure expansion bus for NAND Flash */
	241	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN \|
	242	IXP4XX_EXP_BUS_STROBE_T(1) \| /* extend by 1 clock */
	243	IXP4XX_EXP_BUS_CYCLES(0) \| /* Intel cycles */
	244	IXP4XX_EXP_BUS_SIZE(0) \| /* 512bytes addr space*/
	245	IXP4XX_EXP_BUS_WR_EN \|
	246	IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
	247	#endif
	248
45fba084 RS	249	if (cpu_is_ixp43x()) {
	250	ixdp425_uart.num_resources = 1;
	251	ixdp425_uart_data[1].flags = 0;
	252	}
	253
1da177e4 LT	254	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
	255	}
	256
b38708fc	257	#ifdef CONFIG_ARCH_IXDP425
1da177e4	258	MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
e9dea0c6	259	/* Maintainer: MontaVista Software, Inc. */
e605ecd7	260	.map_io = ixp4xx_map_io,
e9dea0c6	261	.init_irq = ixp4xx_init_irq,
1da177e4	262	.timer = &ixp4xx_timer,
e9dea0c6 RK	263	.boot_params = 0x0100,
e9dea0c6 RK	264	.init_machine = ixdp425_init,
1da177e4	265	MACHINE_END
e0a20089	266	#endif
1da177e4	267
e0a20089	268	#ifdef CONFIG_MACH_IXDP465
1da177e4	269	MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
e9dea0c6	270	/* Maintainer: MontaVista Software, Inc. */
e605ecd7	271	.map_io = ixp4xx_map_io,
e9dea0c6	272	.init_irq = ixp4xx_init_irq,
1da177e4	273	.timer = &ixp4xx_timer,
e9dea0c6 RK	274	.boot_params = 0x0100,
e9dea0c6 RK	275	.init_machine = ixdp425_init,
1da177e4	276	MACHINE_END
e0a20089	277	#endif
1da177e4	278
e0a20089	279	#ifdef CONFIG_ARCH_PRPMC1100
1da177e4	280	MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
e9dea0c6	281	/* Maintainer: MontaVista Software, Inc. */
e605ecd7	282	.map_io = ixp4xx_map_io,
e9dea0c6	283	.init_irq = ixp4xx_init_irq,
1da177e4	284	.timer = &ixp4xx_timer,
e9dea0c6 RK	285	.boot_params = 0x0100,
e9dea0c6 RK	286	.init_machine = ixdp425_init,
1da177e4	287	MACHINE_END
e0a20089	288	#endif
45fba084 RS	289
	290	#ifdef CONFIG_MACH_KIXRP435
	291	MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
	292	/* Maintainer: MontaVista Software, Inc. */
45fba084 RS	293	.map_io = ixp4xx_map_io,
	294	.init_irq = ixp4xx_init_irq,
	295	.timer = &ixp4xx_timer,
	296	.boot_params = 0x0100,
	297	.init_machine = ixdp425_init,
	298	MACHINE_END
	299	#endif