[deliverable/linux.git] / arch / arm / mach-lpc32xx / serial.c

/*
 * arch/arm/mach-lpc32xx/serial.c
 *
 * Author: Kevin Wells <kevin.wells@nxp.com>
 *
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"

#define LPC32XX_SUART_FIFO_SIZE	64

struct uartinit {
	char *uart_ck_name;
	u32 ck_mode_mask;
	void __iomem *pdiv_clk_reg;
	resource_size_t mapbase;
};

static struct uartinit uartinit_data[] __initdata = {
	{
		.uart_ck_name = "uart5_ck",
		.ck_mode_mask =
			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
		.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
		.mapbase = LPC32XX_UART5_BASE,
	},
	{
		.uart_ck_name = "uart3_ck",
		.ck_mode_mask =
			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
		.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
		.mapbase = LPC32XX_UART3_BASE,
	},
	{
		.uart_ck_name = "uart4_ck",
		.ck_mode_mask =
			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
		.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
		.mapbase = LPC32XX_UART4_BASE,
	},
	{
		.uart_ck_name = "uart6_ck",
		.ck_mode_mask =
			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
		.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
		.mapbase = LPC32XX_UART6_BASE,
	},
};

void __init lpc32xx_serial_init(void)
{
	u32 tmp, clkmodes = 0;
	struct clk *clk;
	unsigned int puart;
	int i, j;

	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
		clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
		if (!IS_ERR(clk)) {
			clk_enable(clk);
		}

		/* Setup UART clock modes for all UARTs, disable autoclock */
		clkmodes |= uartinit_data[i].ck_mode_mask;

		/* pre-UART clock divider set to 1 */
		__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);

		/*
		 * Force a flush of the RX FIFOs to work around a
		 * HW bug
		 */
		puart = uartinit_data[i].mapbase;
		__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
		__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
		j = LPC32XX_SUART_FIFO_SIZE;
		while (j--)
			tmp = __raw_readl(
				LPC32XX_UART_DLL_FIFO(puart));
		__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
	}

	/* This needs to be done after all UART clocks are setup */
	__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
		/* Force a flush of the RX FIFOs to work around a HW bug */
		puart = uartinit_data[i].mapbase;
		__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
		__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
		j = LPC32XX_SUART_FIFO_SIZE;
		while (j--)
			tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
		__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
	}

	/* Disable IrDA pulsing support on UART6 */
	tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
	tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
	__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);

	/* Disable UART5->USB transparent mode or USB won't work */
	tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
	tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
	__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
}
Commit	Line	Data
e6e912c4 KW	1	/*
	2	* arch/arm/mach-lpc32xx/serial.c
	3	*
	4	* Author: Kevin Wells <kevin.wells@nxp.com>
	5	*
	6	* Copyright (C) 2010 NXP Semiconductors
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/types.h>
	21	#include <linux/serial.h>
	22	#include <linux/serial_core.h>
	23	#include <linux/serial_reg.h>
	24	#include <linux/serial_8250.h>
	25	#include <linux/clk.h>
	26	#include <linux/io.h>
	27
	28	#include <mach/hardware.h>
	29	#include <mach/platform.h>
	30	#include "common.h"
	31
	32	#define LPC32XX_SUART_FIFO_SIZE 64
	33
e6e912c4 KW	34	struct uartinit {
	35	char *uart_ck_name;
	36	u32 ck_mode_mask;
	37	void __iomem *pdiv_clk_reg;
2707208e	38	resource_size_t mapbase;
e6e912c4 KW	39	};
	40
	41	static struct uartinit uartinit_data[] __initdata = {
e6e912c4 KW	42	{
	43	.uart_ck_name = "uart5_ck",
	44	.ck_mode_mask =
	45	LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
	46	.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
2707208e	47	.mapbase = LPC32XX_UART5_BASE,
e6e912c4	48	},
e6e912c4 KW	49	{
	50	.uart_ck_name = "uart3_ck",
	51	.ck_mode_mask =
	52	LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
	53	.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
2707208e	54	.mapbase = LPC32XX_UART3_BASE,
e6e912c4	55	},
e6e912c4 KW	56	{
	57	.uart_ck_name = "uart4_ck",
	58	.ck_mode_mask =
	59	LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
	60	.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
2707208e	61	.mapbase = LPC32XX_UART4_BASE,
e6e912c4	62	},
e6e912c4 KW	63	{
	64	.uart_ck_name = "uart6_ck",
	65	.ck_mode_mask =
	66	LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
	67	.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
2707208e	68	.mapbase = LPC32XX_UART6_BASE,
e6e912c4	69	},
e6e912c4 KW	70	};
	71
	72	void __init lpc32xx_serial_init(void)
	73	{
	74	u32 tmp, clkmodes = 0;
	75	struct clk *clk;
	76	unsigned int puart;
	77	int i, j;
	78
e6e912c4 KW	79	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
	80	clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
	81	if (!IS_ERR(clk)) {
	82	clk_enable(clk);
e6e912c4 KW	83	}
e6e912c4 KW	84
e6e912c4 KW	85	/* Setup UART clock modes for all UARTs, disable autoclock */
	86	clkmodes \|= uartinit_data[i].ck_mode_mask;
	87
	88	/* pre-UART clock divider set to 1 */
	89	__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
2707208e RS	90
	91	/*
	92	* Force a flush of the RX FIFOs to work around a
	93	* HW bug
	94	*/
	95	puart = uartinit_data[i].mapbase;
	96	__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
	97	__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
	98	j = LPC32XX_SUART_FIFO_SIZE;
	99	while (j--)
	100	tmp = __raw_readl(
	101	LPC32XX_UART_DLL_FIFO(puart));
	102	__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
e6e912c4 KW	103	}
	104
	105	/* This needs to be done after all UART clocks are setup */
	106	__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
ff424aa4	107	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
e6e912c4	108	/* Force a flush of the RX FIFOs to work around a HW bug */
c70426f1	109	puart = uartinit_data[i].mapbase;
e6e912c4 KW	110	__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
	111	__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
	112	j = LPC32XX_SUART_FIFO_SIZE;
	113	while (j--)
	114	tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
	115	__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
	116	}
	117
5fe8f11c APS	118	/* Disable IrDA pulsing support on UART6 */
	119	tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
	120	tmp \|= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
	121	__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
	122
e6e912c4 KW	123	/* Disable UART5->USB transparent mode or USB won't work */
	124	tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
	125	tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
	126	__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
e6e912c4	127	}