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13dee960 HZ |
1 | /* |
2 | * linux/arch/arm/mach-mmp/brownstone.c | |
3 | * | |
4 | * Support for the Marvell Brownstone Development Platform. | |
5 | * | |
6 | * Copyright (C) 2009-2010 Marvell International Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * publishhed by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/io.h> | |
b8f649f1 | 17 | #include <linux/gpio-pxa.h> |
13dee960 HZ |
18 | #include <linux/regulator/machine.h> |
19 | #include <linux/regulator/max8649.h> | |
e97d0fac | 20 | #include <linux/regulator/fixed.h> |
13dee960 HZ |
21 | #include <linux/mfd/max8925.h> |
22 | ||
23 | #include <asm/mach-types.h> | |
24 | #include <asm/mach/arch.h> | |
25 | #include <mach/addr-map.h> | |
26 | #include <mach/mfp-mmp2.h> | |
27 | #include <mach/mmp2.h> | |
28 | #include <mach/irqs.h> | |
29 | ||
30 | #include "common.h" | |
31 | ||
8661fb92 | 32 | #define BROWNSTONE_NR_IRQS (MMP_NR_IRQS + 40) |
13dee960 | 33 | |
e97d0fac MB |
34 | #define GPIO_5V_ENABLE (89) |
35 | ||
13dee960 HZ |
36 | static unsigned long brownstone_pin_config[] __initdata = { |
37 | /* UART1 */ | |
38 | GPIO29_UART1_RXD, | |
39 | GPIO30_UART1_TXD, | |
40 | ||
41 | /* UART3 */ | |
42 | GPIO51_UART3_RXD, | |
43 | GPIO52_UART3_TXD, | |
44 | ||
45 | /* DFI */ | |
46 | GPIO168_DFI_D0, | |
47 | GPIO167_DFI_D1, | |
48 | GPIO166_DFI_D2, | |
49 | GPIO165_DFI_D3, | |
50 | GPIO107_DFI_D4, | |
51 | GPIO106_DFI_D5, | |
52 | GPIO105_DFI_D6, | |
53 | GPIO104_DFI_D7, | |
54 | GPIO111_DFI_D8, | |
55 | GPIO164_DFI_D9, | |
56 | GPIO163_DFI_D10, | |
57 | GPIO162_DFI_D11, | |
58 | GPIO161_DFI_D12, | |
59 | GPIO110_DFI_D13, | |
60 | GPIO109_DFI_D14, | |
61 | GPIO108_DFI_D15, | |
62 | GPIO143_ND_nCS0, | |
63 | GPIO144_ND_nCS1, | |
64 | GPIO147_ND_nWE, | |
65 | GPIO148_ND_nRE, | |
66 | GPIO150_ND_ALE, | |
67 | GPIO149_ND_CLE, | |
68 | GPIO112_ND_RDY0, | |
69 | GPIO160_ND_RDY1, | |
70 | ||
71 | /* PMIC */ | |
72 | PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, | |
73 | ||
74 | /* MMC0 */ | |
75 | GPIO131_MMC1_DAT3 | MFP_PULL_HIGH, | |
76 | GPIO132_MMC1_DAT2 | MFP_PULL_HIGH, | |
77 | GPIO133_MMC1_DAT1 | MFP_PULL_HIGH, | |
78 | GPIO134_MMC1_DAT0 | MFP_PULL_HIGH, | |
79 | GPIO136_MMC1_CMD | MFP_PULL_HIGH, | |
80 | GPIO139_MMC1_CLK, | |
81 | GPIO140_MMC1_CD | MFP_PULL_LOW, | |
82 | GPIO141_MMC1_WP | MFP_PULL_LOW, | |
83 | ||
84 | /* MMC1 */ | |
85 | GPIO37_MMC2_DAT3 | MFP_PULL_HIGH, | |
86 | GPIO38_MMC2_DAT2 | MFP_PULL_HIGH, | |
87 | GPIO39_MMC2_DAT1 | MFP_PULL_HIGH, | |
88 | GPIO40_MMC2_DAT0 | MFP_PULL_HIGH, | |
89 | GPIO41_MMC2_CMD | MFP_PULL_HIGH, | |
90 | GPIO42_MMC2_CLK, | |
91 | ||
92 | /* MMC2 */ | |
93 | GPIO165_MMC3_DAT7 | MFP_PULL_HIGH, | |
94 | GPIO162_MMC3_DAT6 | MFP_PULL_HIGH, | |
95 | GPIO166_MMC3_DAT5 | MFP_PULL_HIGH, | |
96 | GPIO163_MMC3_DAT4 | MFP_PULL_HIGH, | |
97 | GPIO167_MMC3_DAT3 | MFP_PULL_HIGH, | |
98 | GPIO164_MMC3_DAT2 | MFP_PULL_HIGH, | |
99 | GPIO168_MMC3_DAT1 | MFP_PULL_HIGH, | |
100 | GPIO111_MMC3_DAT0 | MFP_PULL_HIGH, | |
101 | GPIO112_MMC3_CMD | MFP_PULL_HIGH, | |
102 | GPIO151_MMC3_CLK, | |
e97d0fac MB |
103 | |
104 | /* 5V regulator */ | |
105 | GPIO89_GPIO, | |
13dee960 HZ |
106 | }; |
107 | ||
b8f649f1 HZ |
108 | static struct pxa_gpio_platform_data mmp2_gpio_pdata = { |
109 | .irq_base = MMP_GPIO_TO_IRQ(0), | |
110 | }; | |
111 | ||
13dee960 HZ |
112 | static struct regulator_consumer_supply max8649_supply[] = { |
113 | REGULATOR_SUPPLY("vcc_core", NULL), | |
114 | }; | |
115 | ||
116 | static struct regulator_init_data max8649_init_data = { | |
117 | .constraints = { | |
118 | .name = "vcc_core range", | |
119 | .min_uV = 1150000, | |
120 | .max_uV = 1280000, | |
121 | .always_on = 1, | |
122 | .boot_on = 1, | |
123 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
124 | }, | |
125 | .num_consumer_supplies = 1, | |
126 | .consumer_supplies = &max8649_supply[0], | |
127 | }; | |
128 | ||
129 | static struct max8649_platform_data brownstone_max8649_info = { | |
130 | .mode = 2, /* VID1 = 1, VID0 = 0 */ | |
131 | .extclk = 0, | |
132 | .ramp_timing = MAX8649_RAMP_32MV, | |
133 | .regulator = &max8649_init_data, | |
134 | }; | |
135 | ||
e97d0fac MB |
136 | static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = { |
137 | REGULATOR_SUPPLY("v_5vp", NULL), | |
138 | }; | |
139 | ||
140 | static struct regulator_init_data brownstone_v_5vp_data = { | |
141 | .constraints = { | |
142 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
143 | }, | |
144 | .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies), | |
145 | .consumer_supplies = brownstone_v_5vp_supplies, | |
146 | }; | |
147 | ||
148 | static struct fixed_voltage_config brownstone_v_5vp = { | |
149 | .supply_name = "v_5vp", | |
150 | .microvolts = 5000000, | |
151 | .gpio = GPIO_5V_ENABLE, | |
152 | .enable_high = 1, | |
153 | .enabled_at_boot = 1, | |
154 | .init_data = &brownstone_v_5vp_data, | |
155 | }; | |
156 | ||
157 | static struct platform_device brownstone_v_5vp_device = { | |
158 | .name = "reg-fixed-voltage", | |
159 | .id = 1, | |
160 | .dev = { | |
161 | .platform_data = &brownstone_v_5vp, | |
162 | }, | |
163 | }; | |
164 | ||
13dee960 | 165 | static struct max8925_platform_data brownstone_max8925_info = { |
8661fb92 | 166 | .irq_base = MMP_NR_IRQS, |
13dee960 HZ |
167 | }; |
168 | ||
169 | static struct i2c_board_info brownstone_twsi1_info[] = { | |
170 | [0] = { | |
171 | .type = "max8649", | |
172 | .addr = 0x60, | |
173 | .platform_data = &brownstone_max8649_info, | |
174 | }, | |
175 | [1] = { | |
176 | .type = "max8925", | |
177 | .addr = 0x3c, | |
178 | .irq = IRQ_MMP2_PMIC, | |
179 | .platform_data = &brownstone_max8925_info, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { | |
6f984f3b | 184 | .clk_delay_cycles = 0x1f, |
13dee960 HZ |
185 | }; |
186 | ||
6f984f3b ZG |
187 | static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = { |
188 | .clk_delay_cycles = 0x1f, | |
189 | .flags = PXA_FLAG_CARD_PERMANENT | |
190 | | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT, | |
191 | }; | |
192 | ||
101bf4c1 LY |
193 | static struct sram_platdata mmp2_asram_platdata = { |
194 | .pool_name = "asram", | |
195 | .granularity = SRAM_GRANULARITY, | |
196 | }; | |
6f984f3b | 197 | |
bca7ab31 LY |
198 | static struct sram_platdata mmp2_isram_platdata = { |
199 | .pool_name = "isram", | |
200 | .granularity = SRAM_GRANULARITY, | |
201 | }; | |
6f984f3b | 202 | |
13dee960 HZ |
203 | static void __init brownstone_init(void) |
204 | { | |
205 | mfp_config(ARRAY_AND_SIZE(brownstone_pin_config)); | |
206 | ||
207 | /* on-chip devices */ | |
208 | mmp2_add_uart(1); | |
209 | mmp2_add_uart(3); | |
b8f649f1 HZ |
210 | platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata, |
211 | sizeof(struct pxa_gpio_platform_data)); | |
157d2644 | 212 | platform_device_register(&mmp2_device_gpio); |
13dee960 HZ |
213 | mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info)); |
214 | mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ | |
6f984f3b | 215 | mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */ |
101bf4c1 | 216 | mmp2_add_asram(&mmp2_asram_platdata); |
bca7ab31 | 217 | mmp2_add_isram(&mmp2_isram_platdata); |
e97d0fac MB |
218 | |
219 | /* enable 5v regulator */ | |
220 | platform_device_register(&brownstone_v_5vp_device); | |
13dee960 HZ |
221 | } |
222 | ||
223 | MACHINE_START(BROWNSTONE, "Brownstone Development Platform") | |
224 | /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */ | |
225 | .map_io = mmp_map_io, | |
226 | .nr_irqs = BROWNSTONE_NR_IRQS, | |
227 | .init_irq = mmp2_init_irq, | |
6bb27d73 | 228 | .init_time = mmp2_timer_init, |
13dee960 | 229 | .init_machine = brownstone_init, |
9854a38e | 230 | .restart = mmp_restart, |
13dee960 | 231 | MACHINE_END |