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c24b3114 HZ |
1 | /* |
2 | * linux/arch/arm/mach-mmp/irq.c | |
3 | * | |
4 | * Generic IRQ handling, GPIO IRQ demultiplexing, etc. | |
5 | * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd. | |
6 | * | |
7 | * Author: Bin Yang <bin.yang@marvell.com> | |
8 | * Haojian Zhuang <haojian.zhuang@gmail.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/irqdomain.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | ||
24 | #include <mach/irqs.h> | |
25 | ||
87046f4f CX |
26 | #ifdef CONFIG_CPU_MMP2 |
27 | #include <mach/pm-mmp2.h> | |
28 | #endif | |
902ca229 CX |
29 | #ifdef CONFIG_CPU_PXA910 |
30 | #include <mach/pm-pxa910.h> | |
31 | #endif | |
87046f4f | 32 | |
c24b3114 HZ |
33 | #include "common.h" |
34 | ||
35 | #define MAX_ICU_NR 16 | |
36 | ||
37 | struct icu_chip_data { | |
38 | int nr_irqs; | |
39 | unsigned int virq_base; | |
40 | unsigned int cascade_irq; | |
41 | void __iomem *reg_status; | |
42 | void __iomem *reg_mask; | |
43 | unsigned int conf_enable; | |
44 | unsigned int conf_disable; | |
45 | unsigned int conf_mask; | |
46 | unsigned int clr_mfp_irq_base; | |
47 | unsigned int clr_mfp_hwirq; | |
48 | struct irq_domain *domain; | |
49 | }; | |
50 | ||
51 | struct mmp_intc_conf { | |
52 | unsigned int conf_enable; | |
53 | unsigned int conf_disable; | |
54 | unsigned int conf_mask; | |
55 | }; | |
56 | ||
57 | void __iomem *mmp_icu_base; | |
58 | static struct icu_chip_data icu_data[MAX_ICU_NR]; | |
59 | static int max_icu_nr; | |
60 | ||
61 | extern void mmp2_clear_pmic_int(void); | |
62 | ||
63 | static void icu_mask_ack_irq(struct irq_data *d) | |
64 | { | |
65 | struct irq_domain *domain = d->domain; | |
66 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; | |
67 | int hwirq; | |
68 | u32 r; | |
69 | ||
70 | hwirq = d->irq - data->virq_base; | |
71 | if (data == &icu_data[0]) { | |
72 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); | |
73 | r &= ~data->conf_mask; | |
74 | r |= data->conf_disable; | |
75 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); | |
76 | } else { | |
77 | #ifdef CONFIG_CPU_MMP2 | |
78 | if ((data->virq_base == data->clr_mfp_irq_base) | |
79 | && (hwirq == data->clr_mfp_hwirq)) | |
80 | mmp2_clear_pmic_int(); | |
81 | #endif | |
82 | r = readl_relaxed(data->reg_mask) | (1 << hwirq); | |
83 | writel_relaxed(r, data->reg_mask); | |
84 | } | |
85 | } | |
86 | ||
87 | static void icu_mask_irq(struct irq_data *d) | |
88 | { | |
89 | struct irq_domain *domain = d->domain; | |
90 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; | |
91 | int hwirq; | |
92 | u32 r; | |
93 | ||
94 | hwirq = d->irq - data->virq_base; | |
95 | if (data == &icu_data[0]) { | |
96 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); | |
97 | r &= ~data->conf_mask; | |
98 | r |= data->conf_disable; | |
99 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); | |
100 | } else { | |
101 | r = readl_relaxed(data->reg_mask) | (1 << hwirq); | |
102 | writel_relaxed(r, data->reg_mask); | |
103 | } | |
104 | } | |
105 | ||
106 | static void icu_unmask_irq(struct irq_data *d) | |
107 | { | |
108 | struct irq_domain *domain = d->domain; | |
109 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; | |
110 | int hwirq; | |
111 | u32 r; | |
112 | ||
113 | hwirq = d->irq - data->virq_base; | |
114 | if (data == &icu_data[0]) { | |
115 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); | |
116 | r &= ~data->conf_mask; | |
117 | r |= data->conf_enable; | |
118 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); | |
119 | } else { | |
120 | r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); | |
121 | writel_relaxed(r, data->reg_mask); | |
122 | } | |
123 | } | |
124 | ||
125 | static struct irq_chip icu_irq_chip = { | |
126 | .name = "icu_irq", | |
127 | .irq_mask = icu_mask_irq, | |
128 | .irq_mask_ack = icu_mask_ack_irq, | |
129 | .irq_unmask = icu_unmask_irq, | |
130 | }; | |
131 | ||
132 | static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) | |
133 | { | |
134 | struct irq_domain *domain; | |
135 | struct icu_chip_data *data; | |
136 | int i; | |
137 | unsigned long mask, status, n; | |
138 | ||
139 | for (i = 1; i < max_icu_nr; i++) { | |
140 | if (irq == icu_data[i].cascade_irq) { | |
141 | domain = icu_data[i].domain; | |
142 | data = (struct icu_chip_data *)domain->host_data; | |
143 | break; | |
144 | } | |
145 | } | |
146 | if (i >= max_icu_nr) { | |
147 | pr_err("Spurious irq %d in MMP INTC\n", irq); | |
148 | return; | |
149 | } | |
150 | ||
151 | mask = readl_relaxed(data->reg_mask); | |
152 | while (1) { | |
153 | status = readl_relaxed(data->reg_status) & ~mask; | |
154 | if (status == 0) | |
155 | break; | |
156 | n = find_first_bit(&status, BITS_PER_LONG); | |
157 | while (n < BITS_PER_LONG) { | |
158 | generic_handle_irq(icu_data[i].virq_base + n); | |
159 | n = find_next_bit(&status, BITS_PER_LONG, n + 1); | |
160 | } | |
161 | } | |
162 | } | |
163 | ||
164 | static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
165 | irq_hw_number_t hw) | |
166 | { | |
167 | irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); | |
168 | set_irq_flags(irq, IRQF_VALID); | |
169 | return 0; | |
170 | } | |
171 | ||
172 | static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node, | |
173 | const u32 *intspec, unsigned int intsize, | |
174 | unsigned long *out_hwirq, | |
175 | unsigned int *out_type) | |
176 | { | |
177 | *out_hwirq = intspec[0]; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | const struct irq_domain_ops mmp_irq_domain_ops = { | |
182 | .map = mmp_irq_domain_map, | |
183 | .xlate = mmp_irq_domain_xlate, | |
184 | }; | |
185 | ||
186 | static struct mmp_intc_conf mmp_conf = { | |
187 | .conf_enable = 0x51, | |
188 | .conf_disable = 0x0, | |
189 | .conf_mask = 0x7f, | |
190 | }; | |
191 | ||
192 | static struct mmp_intc_conf mmp2_conf = { | |
193 | .conf_enable = 0x20, | |
194 | .conf_disable = 0x0, | |
195 | .conf_mask = 0x7f, | |
196 | }; | |
197 | ||
198 | /* MMP (ARMv5) */ | |
199 | void __init icu_init_irq(void) | |
200 | { | |
201 | int irq; | |
202 | ||
203 | max_icu_nr = 1; | |
204 | mmp_icu_base = ioremap(0xd4282000, 0x1000); | |
205 | icu_data[0].conf_enable = mmp_conf.conf_enable; | |
206 | icu_data[0].conf_disable = mmp_conf.conf_disable; | |
207 | icu_data[0].conf_mask = mmp_conf.conf_mask; | |
208 | icu_data[0].nr_irqs = 64; | |
209 | icu_data[0].virq_base = 0; | |
210 | icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, | |
211 | &irq_domain_simple_ops, | |
212 | &icu_data[0]); | |
213 | for (irq = 0; irq < 64; irq++) { | |
214 | icu_mask_irq(irq_get_irq_data(irq)); | |
215 | irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); | |
216 | set_irq_flags(irq, IRQF_VALID); | |
217 | } | |
218 | irq_set_default_host(icu_data[0].domain); | |
902ca229 CX |
219 | #ifdef CONFIG_CPU_PXA910 |
220 | icu_irq_chip.irq_set_wake = pxa910_set_wake; | |
221 | #endif | |
c24b3114 HZ |
222 | } |
223 | ||
224 | /* MMP2 (ARMv7) */ | |
225 | void __init mmp2_init_icu(void) | |
226 | { | |
227 | int irq; | |
228 | ||
229 | max_icu_nr = 8; | |
230 | mmp_icu_base = ioremap(0xd4282000, 0x1000); | |
231 | icu_data[0].conf_enable = mmp2_conf.conf_enable; | |
232 | icu_data[0].conf_disable = mmp2_conf.conf_disable; | |
233 | icu_data[0].conf_mask = mmp2_conf.conf_mask; | |
234 | icu_data[0].nr_irqs = 64; | |
235 | icu_data[0].virq_base = 0; | |
236 | icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, | |
237 | &irq_domain_simple_ops, | |
238 | &icu_data[0]); | |
239 | icu_data[1].reg_status = mmp_icu_base + 0x150; | |
240 | icu_data[1].reg_mask = mmp_icu_base + 0x168; | |
241 | icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; | |
242 | icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; | |
243 | icu_data[1].nr_irqs = 2; | |
244 | icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; | |
245 | icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, | |
246 | icu_data[1].virq_base, 0, | |
247 | &irq_domain_simple_ops, | |
248 | &icu_data[1]); | |
249 | icu_data[2].reg_status = mmp_icu_base + 0x154; | |
250 | icu_data[2].reg_mask = mmp_icu_base + 0x16c; | |
251 | icu_data[2].nr_irqs = 2; | |
252 | icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; | |
253 | icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, | |
254 | icu_data[2].virq_base, 0, | |
255 | &irq_domain_simple_ops, | |
256 | &icu_data[2]); | |
257 | icu_data[3].reg_status = mmp_icu_base + 0x180; | |
258 | icu_data[3].reg_mask = mmp_icu_base + 0x17c; | |
259 | icu_data[3].nr_irqs = 3; | |
260 | icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; | |
261 | icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, | |
262 | icu_data[3].virq_base, 0, | |
263 | &irq_domain_simple_ops, | |
264 | &icu_data[3]); | |
265 | icu_data[4].reg_status = mmp_icu_base + 0x158; | |
266 | icu_data[4].reg_mask = mmp_icu_base + 0x170; | |
267 | icu_data[4].nr_irqs = 5; | |
268 | icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; | |
269 | icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, | |
270 | icu_data[4].virq_base, 0, | |
271 | &irq_domain_simple_ops, | |
272 | &icu_data[4]); | |
273 | icu_data[5].reg_status = mmp_icu_base + 0x15c; | |
274 | icu_data[5].reg_mask = mmp_icu_base + 0x174; | |
275 | icu_data[5].nr_irqs = 15; | |
276 | icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; | |
277 | icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, | |
278 | icu_data[5].virq_base, 0, | |
279 | &irq_domain_simple_ops, | |
280 | &icu_data[5]); | |
281 | icu_data[6].reg_status = mmp_icu_base + 0x160; | |
282 | icu_data[6].reg_mask = mmp_icu_base + 0x178; | |
283 | icu_data[6].nr_irqs = 2; | |
284 | icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; | |
285 | icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, | |
286 | icu_data[6].virq_base, 0, | |
287 | &irq_domain_simple_ops, | |
288 | &icu_data[6]); | |
289 | icu_data[7].reg_status = mmp_icu_base + 0x188; | |
290 | icu_data[7].reg_mask = mmp_icu_base + 0x184; | |
291 | icu_data[7].nr_irqs = 2; | |
292 | icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; | |
293 | icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, | |
294 | icu_data[7].virq_base, 0, | |
295 | &irq_domain_simple_ops, | |
296 | &icu_data[7]); | |
297 | for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { | |
298 | icu_mask_irq(irq_get_irq_data(irq)); | |
299 | switch (irq) { | |
300 | case IRQ_MMP2_PMIC_MUX: | |
301 | case IRQ_MMP2_RTC_MUX: | |
302 | case IRQ_MMP2_KEYPAD_MUX: | |
303 | case IRQ_MMP2_TWSI_MUX: | |
304 | case IRQ_MMP2_MISC_MUX: | |
305 | case IRQ_MMP2_MIPI_HSI1_MUX: | |
306 | case IRQ_MMP2_MIPI_HSI0_MUX: | |
307 | irq_set_chip(irq, &icu_irq_chip); | |
308 | irq_set_chained_handler(irq, icu_mux_irq_demux); | |
309 | break; | |
310 | default: | |
311 | irq_set_chip_and_handler(irq, &icu_irq_chip, | |
312 | handle_level_irq); | |
313 | break; | |
314 | } | |
315 | set_irq_flags(irq, IRQF_VALID); | |
316 | } | |
317 | irq_set_default_host(icu_data[0].domain); | |
87046f4f CX |
318 | #ifdef CONFIG_CPU_MMP2 |
319 | icu_irq_chip.irq_set_wake = mmp2_set_wake; | |
320 | #endif | |
c24b3114 HZ |
321 | } |
322 | ||
323 | #ifdef CONFIG_OF | |
324 | static const struct of_device_id intc_ids[] __initconst = { | |
325 | { .compatible = "mrvl,mmp-intc", .data = &mmp_conf }, | |
326 | { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf }, | |
327 | {} | |
328 | }; | |
329 | ||
330 | static const struct of_device_id mmp_mux_irq_match[] __initconst = { | |
331 | { .compatible = "mrvl,mmp2-mux-intc" }, | |
332 | {} | |
333 | }; | |
334 | ||
335 | int __init mmp2_mux_init(struct device_node *parent) | |
336 | { | |
337 | struct device_node *node; | |
338 | const struct of_device_id *of_id; | |
339 | struct resource res; | |
340 | int i, irq_base, ret, irq; | |
341 | u32 nr_irqs, mfp_irq; | |
342 | ||
343 | node = parent; | |
344 | max_icu_nr = 1; | |
345 | for (i = 1; i < MAX_ICU_NR; i++) { | |
346 | node = of_find_matching_node(node, mmp_mux_irq_match); | |
347 | if (!node) | |
348 | break; | |
349 | of_id = of_match_node(&mmp_mux_irq_match[0], node); | |
350 | ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", | |
351 | &nr_irqs); | |
352 | if (ret) { | |
353 | pr_err("Not found mrvl,intc-nr-irqs property\n"); | |
354 | ret = -EINVAL; | |
355 | goto err; | |
356 | } | |
357 | ret = of_address_to_resource(node, 0, &res); | |
358 | if (ret < 0) { | |
359 | pr_err("Not found reg property\n"); | |
360 | ret = -EINVAL; | |
361 | goto err; | |
362 | } | |
363 | icu_data[i].reg_status = mmp_icu_base + res.start; | |
364 | ret = of_address_to_resource(node, 1, &res); | |
365 | if (ret < 0) { | |
366 | pr_err("Not found reg property\n"); | |
367 | ret = -EINVAL; | |
368 | goto err; | |
369 | } | |
370 | icu_data[i].reg_mask = mmp_icu_base + res.start; | |
371 | icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); | |
372 | if (!icu_data[i].cascade_irq) { | |
373 | ret = -EINVAL; | |
374 | goto err; | |
375 | } | |
376 | ||
377 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); | |
378 | if (irq_base < 0) { | |
379 | pr_err("Failed to allocate IRQ numbers for mux intc\n"); | |
380 | ret = irq_base; | |
381 | goto err; | |
382 | } | |
383 | if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", | |
384 | &mfp_irq)) { | |
385 | icu_data[i].clr_mfp_irq_base = irq_base; | |
386 | icu_data[i].clr_mfp_hwirq = mfp_irq; | |
387 | } | |
388 | irq_set_chained_handler(icu_data[i].cascade_irq, | |
389 | icu_mux_irq_demux); | |
390 | icu_data[i].nr_irqs = nr_irqs; | |
391 | icu_data[i].virq_base = irq_base; | |
392 | icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs, | |
393 | irq_base, 0, | |
394 | &mmp_irq_domain_ops, | |
395 | &icu_data[i]); | |
396 | for (irq = irq_base; irq < irq_base + nr_irqs; irq++) | |
397 | icu_mask_irq(irq_get_irq_data(irq)); | |
398 | } | |
399 | max_icu_nr = i; | |
400 | return 0; | |
401 | err: | |
402 | of_node_put(node); | |
403 | max_icu_nr = i; | |
404 | return ret; | |
405 | } | |
406 | ||
407 | void __init mmp_dt_irq_init(void) | |
408 | { | |
409 | struct device_node *node; | |
410 | const struct of_device_id *of_id; | |
411 | struct mmp_intc_conf *conf; | |
412 | int nr_irqs, irq_base, ret, irq; | |
413 | ||
414 | node = of_find_matching_node(NULL, intc_ids); | |
415 | if (!node) { | |
416 | pr_err("Failed to find interrupt controller in arch-mmp\n"); | |
417 | return; | |
418 | } | |
419 | of_id = of_match_node(intc_ids, node); | |
420 | conf = of_id->data; | |
421 | ||
422 | ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); | |
423 | if (ret) { | |
424 | pr_err("Not found mrvl,intc-nr-irqs property\n"); | |
425 | return; | |
426 | } | |
427 | ||
428 | mmp_icu_base = of_iomap(node, 0); | |
429 | if (!mmp_icu_base) { | |
430 | pr_err("Failed to get interrupt controller register\n"); | |
431 | return; | |
432 | } | |
433 | ||
434 | irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0); | |
435 | if (irq_base < 0) { | |
436 | pr_err("Failed to allocate IRQ numbers\n"); | |
437 | goto err; | |
438 | } else if (irq_base != NR_IRQS_LEGACY) { | |
439 | pr_err("ICU's irqbase should be started from 0\n"); | |
440 | goto err; | |
441 | } | |
442 | icu_data[0].conf_enable = conf->conf_enable; | |
443 | icu_data[0].conf_disable = conf->conf_disable; | |
444 | icu_data[0].conf_mask = conf->conf_mask; | |
445 | icu_data[0].nr_irqs = nr_irqs; | |
446 | icu_data[0].virq_base = 0; | |
447 | icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0, | |
448 | &mmp_irq_domain_ops, | |
449 | &icu_data[0]); | |
450 | irq_set_default_host(icu_data[0].domain); | |
451 | for (irq = 0; irq < nr_irqs; irq++) | |
452 | icu_mask_irq(irq_get_irq_data(irq)); | |
453 | mmp2_mux_init(node); | |
454 | return; | |
455 | err: | |
456 | iounmap(mmp_icu_base); | |
457 | } | |
458 | #endif |