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2f7e8fae HZ |
1 | /* |
2 | * linux/arch/arm/mach-mmp/mmp2.c | |
3 | * | |
4 | * code name MMP2 | |
5 | * | |
6 | * Copyright (C) 2009 Marvell International Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
2f7e8fae HZ |
12 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/io.h> | |
16 | ||
66b19647 HZ |
17 | #include <asm/hardware/cache-tauros2.h> |
18 | ||
4d4a339d | 19 | #include <asm/mach/time.h> |
2f7e8fae HZ |
20 | #include <mach/addr-map.h> |
21 | #include <mach/regs-apbc.h> | |
22 | #include <mach/regs-apmu.h> | |
23 | #include <mach/cputype.h> | |
24 | #include <mach/irqs.h> | |
f4557870 | 25 | #include <mach/dma.h> |
2f7e8fae | 26 | #include <mach/mfp.h> |
f55be1bf | 27 | #include <mach/gpio-pxa.h> |
2f7e8fae | 28 | #include <mach/devices.h> |
2728701d | 29 | #include <mach/mmp2.h> |
2f7e8fae HZ |
30 | |
31 | #include "common.h" | |
32 | #include "clock.h" | |
33 | ||
34 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | |
35 | ||
16144bfb HZ |
36 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) |
37 | ||
247b4592 | 38 | static struct mfp_addr_map mmp2_addr_map[] __initdata = { |
7f39403c HZ |
39 | |
40 | MFP_ADDR_X(GPIO0, GPIO58, 0x54), | |
41 | MFP_ADDR_X(GPIO59, GPIO73, 0x280), | |
42 | MFP_ADDR_X(GPIO74, GPIO101, 0x170), | |
43 | ||
44 | MFP_ADDR(GPIO102, 0x0), | |
45 | MFP_ADDR(GPIO103, 0x4), | |
46 | MFP_ADDR(GPIO104, 0x1fc), | |
47 | MFP_ADDR(GPIO105, 0x1f8), | |
48 | MFP_ADDR(GPIO106, 0x1f4), | |
49 | MFP_ADDR(GPIO107, 0x1f0), | |
50 | MFP_ADDR(GPIO108, 0x21c), | |
51 | MFP_ADDR(GPIO109, 0x218), | |
52 | MFP_ADDR(GPIO110, 0x214), | |
53 | MFP_ADDR(GPIO111, 0x200), | |
54 | MFP_ADDR(GPIO112, 0x244), | |
55 | MFP_ADDR(GPIO113, 0x25c), | |
56 | MFP_ADDR(GPIO114, 0x164), | |
57 | MFP_ADDR_X(GPIO115, GPIO122, 0x260), | |
58 | ||
59 | MFP_ADDR(GPIO123, 0x148), | |
60 | MFP_ADDR_X(GPIO124, GPIO141, 0xc), | |
61 | ||
62 | MFP_ADDR(GPIO142, 0x8), | |
63 | MFP_ADDR_X(GPIO143, GPIO151, 0x220), | |
64 | MFP_ADDR_X(GPIO152, GPIO153, 0x248), | |
65 | MFP_ADDR_X(GPIO154, GPIO155, 0x254), | |
66 | MFP_ADDR_X(GPIO156, GPIO159, 0x14c), | |
67 | ||
68 | MFP_ADDR(GPIO160, 0x250), | |
69 | MFP_ADDR(GPIO161, 0x210), | |
70 | MFP_ADDR(GPIO162, 0x20c), | |
71 | MFP_ADDR(GPIO163, 0x208), | |
72 | MFP_ADDR(GPIO164, 0x204), | |
73 | MFP_ADDR(GPIO165, 0x1ec), | |
74 | MFP_ADDR(GPIO166, 0x1e8), | |
75 | MFP_ADDR(GPIO167, 0x1e4), | |
76 | MFP_ADDR(GPIO168, 0x1e0), | |
77 | ||
78 | MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), | |
79 | MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), | |
80 | ||
247b4592 | 81 | MFP_ADDR(PMIC_INT, 0x2c4), |
7f39403c | 82 | MFP_ADDR(CLK_REQ, 0x160), |
247b4592 HZ |
83 | |
84 | MFP_ADDR_END, | |
85 | }; | |
86 | ||
df0c3824 HZ |
87 | void mmp2_clear_pmic_int(void) |
88 | { | |
97b09da4 AB |
89 | void __iomem *mfpr_pmic; |
90 | unsigned long data; | |
df0c3824 HZ |
91 | |
92 | mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; | |
93 | data = __raw_readl(mfpr_pmic); | |
94 | __raw_writel(data | (1 << 6), mfpr_pmic); | |
95 | __raw_writel(data, mfpr_pmic); | |
96 | } | |
97 | ||
16144bfb HZ |
98 | static void __init mmp2_init_gpio(void) |
99 | { | |
100 | int i; | |
101 | ||
102 | /* enable GPIO clock */ | |
103 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); | |
104 | ||
105 | /* unmask GPIO edge detection for all 6 banks -- APMASKx */ | |
106 | for (i = 0; i < 6; i++) | |
107 | __raw_writel(0xffffffff, APMASK(i)); | |
108 | ||
109 | pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); | |
110 | } | |
111 | ||
112 | void __init mmp2_init_irq(void) | |
113 | { | |
114 | mmp2_init_icu(); | |
115 | mmp2_init_gpio(); | |
116 | } | |
117 | ||
5382f419 ZG |
118 | static void sdhc_clk_enable(struct clk *clk) |
119 | { | |
120 | uint32_t clk_rst; | |
121 | ||
122 | clk_rst = __raw_readl(clk->clk_rst); | |
123 | clk_rst |= clk->enable_val; | |
124 | __raw_writel(clk_rst, clk->clk_rst); | |
125 | } | |
126 | ||
127 | static void sdhc_clk_disable(struct clk *clk) | |
128 | { | |
129 | uint32_t clk_rst; | |
130 | ||
131 | clk_rst = __raw_readl(clk->clk_rst); | |
132 | clk_rst &= ~clk->enable_val; | |
133 | __raw_writel(clk_rst, clk->clk_rst); | |
134 | } | |
135 | ||
136 | struct clkops sdhc_clk_ops = { | |
137 | .enable = sdhc_clk_enable, | |
138 | .disable = sdhc_clk_disable, | |
139 | }; | |
140 | ||
2f7e8fae HZ |
141 | /* APB peripheral clocks */ |
142 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); | |
143 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); | |
144 | static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); | |
145 | static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); | |
146 | static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); | |
147 | static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); | |
148 | static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); | |
149 | static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); | |
150 | static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); | |
151 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); | |
2f7e8fae HZ |
152 | |
153 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | |
5382f419 ZG |
154 | static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); |
155 | static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); | |
156 | static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); | |
157 | static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); | |
2f7e8fae HZ |
158 | |
159 | static struct clk_lookup mmp2_clkregs[] = { | |
160 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
161 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
162 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | |
163 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), | |
164 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), | |
165 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), | |
166 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), | |
167 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), | |
168 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | |
169 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | |
170 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | |
6f984f3b ZG |
171 | INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), |
172 | INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), | |
173 | INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), | |
174 | INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), | |
2f7e8fae HZ |
175 | }; |
176 | ||
177 | static int __init mmp2_init(void) | |
178 | { | |
179 | if (cpu_is_mmp2()) { | |
66b19647 HZ |
180 | #ifdef CONFIG_CACHE_TAUROS2 |
181 | tauros2_init(); | |
182 | #endif | |
2f7e8fae | 183 | mfp_init_base(MFPR_VIRT_BASE); |
247b4592 | 184 | mfp_init_addr(mmp2_addr_map); |
f4557870 | 185 | pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); |
e5988636 | 186 | clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); |
2f7e8fae HZ |
187 | } |
188 | ||
189 | return 0; | |
190 | } | |
191 | postcore_initcall(mmp2_init); | |
192 | ||
4d4a339d EM |
193 | static void __init mmp2_timer_init(void) |
194 | { | |
195 | unsigned long clk_rst; | |
196 | ||
197 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); | |
198 | ||
199 | /* | |
200 | * enable bus/functional clock, enable 6.5MHz (divider 4), | |
201 | * release reset | |
202 | */ | |
203 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); | |
204 | __raw_writel(clk_rst, APBC_MMP2_TIMERS); | |
205 | ||
206 | timer_init(IRQ_MMP2_TIMER1); | |
207 | } | |
208 | ||
209 | struct sys_timer mmp2_timer = { | |
210 | .init = mmp2_timer_init, | |
211 | }; | |
212 | ||
2f7e8fae HZ |
213 | /* on-chip devices */ |
214 | MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); | |
215 | MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); | |
216 | MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); | |
217 | MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); | |
218 | MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); | |
219 | MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); | |
220 | MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); | |
221 | MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); | |
222 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); | |
223 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); | |
224 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); | |
6f984f3b ZG |
225 | MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120); |
226 | MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120); | |
227 | MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120); | |
228 | MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120); | |
101bf4c1 | 229 | MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000); |
bca7ab31 LY |
230 | /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */ |
231 | MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000); | |
2f7e8fae | 232 |