[deliverable/linux.git] / arch / arm / mach-msm / board-qsd8x50.c

/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/err.h>
#include <linux/clkdev.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/io.h>
#include <asm/setup.h>

#include <mach/board.h>
#include <mach/irqs.h>
#include <mach/sirc.h>
#include <mach/vreg.h>
#include <mach/mmc.h>

#include "devices.h"
#include "common.h"

static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;

/* Leave smc91x resources empty here, as we'll fill them in
 * at run-time: they vary from board to board, and the true
 * configuration won't be known until boot.
 */
static struct resource smc91x_resources[] = {
	[0] = {
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name           = "smc91x",
	.id             = 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init msm_init_smc91x(void)
{
	if (machine_is_qsd8x50_surf()) {
		smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
		smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
		smc91x_resources[1].start =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		smc91x_resources[1].end   =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		platform_device_register(&smc91x_device);
	}

	return 0;
}
module_init(msm_init_smc91x);

static int hsusb_phy_init_seq[] = {
	0x08, 0x31,	/* Increase HS Driver Amplitude */
	0x20, 0x32,	/* Enable and set Pre-Emphasis Depth to 10% */
	-1
};

static struct msm_otg_platform_data msm_otg_pdata = {
	.phy_init_seq		= hsusb_phy_init_seq,
	.mode                   = USB_PERIPHERAL,
	.otg_control		= OTG_PHY_CONTROL,
};

static struct platform_device *devices[] __initdata = {
	&msm_device_uart3,
	&msm_device_smd,
	&msm_device_otg,
	&msm_device_hsusb,
	&msm_device_hsusb_host,
};

static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	{51, "sdc1_dat_3"},
	{52, "sdc1_dat_2"},
	{53, "sdc1_dat_1"},
	{54, "sdc1_dat_0"},
	{55, "sdc1_cmd"},
	{56, "sdc1_clk"}
};

static struct vreg *vreg_mmc;
static unsigned long vreg_sts;

static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
{
	int rc = 0;
	struct platform_device *pdev;

	pdev = container_of(dv, struct platform_device, dev);

	if (vdd == 0) {
		if (!vreg_sts)
			return 0;

		clear_bit(pdev->id, &vreg_sts);

		if (!vreg_sts) {
			rc = vreg_disable(vreg_mmc);
			if (rc)
				pr_err("vreg_mmc disable failed for slot "
						"%d: %d\n", pdev->id, rc);
		}
		return 0;
	}

	if (!vreg_sts) {
		rc = vreg_set_level(vreg_mmc, 2900);
		if (rc)
			pr_err("vreg_mmc set level failed for slot %d: %d\n",
					pdev->id, rc);
		rc = vreg_enable(vreg_mmc);
		if (rc)
			pr_err("vreg_mmc enable failed for slot %d: %d\n",
					pdev->id, rc);
	}
	set_bit(pdev->id, &vreg_sts);
	return 0;
}

static struct msm_mmc_gpio_data sdc1_gpio = {
	.gpio = sdc1_gpio_cfg,
	.size = ARRAY_SIZE(sdc1_gpio_cfg),
};

static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	.ocr_mask	= MMC_VDD_27_28 | MMC_VDD_28_29,
	.translate_vdd	= msm_sdcc_setup_power,
	.gpio_data = &sdc1_gpio,
};

static void __init qsd8x50_init_mmc(void)
{
	vreg_mmc = vreg_get(NULL, "gp5");

	if (IS_ERR(vreg_mmc)) {
		pr_err("vreg get for vreg_mmc failed (%ld)\n",
				PTR_ERR(vreg_mmc));
		return;
	}

	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
}

static void __init qsd8x50_map_io(void)
{
	msm_map_qsd8x50_io();
	msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
}

static void __init qsd8x50_init_irq(void)
{
	msm_init_irq();
	msm_init_sirc();
}

static void __init qsd8x50_init(void)
{
	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
	platform_add_devices(devices, ARRAY_SIZE(devices));
	qsd8x50_init_mmc();
}

static void __init qsd8x50_init_late(void)
{
	smd_debugfs_init();
}

MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
	.atag_offset = 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.init_late = qsd8x50_init_late,
	.timer = &qsd8x50_timer,
MACHINE_END

MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
	.atag_offset = 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.init_late = qsd8x50_init_late,
	.timer = &qsd8x50_timer,
MACHINE_END
Commit	Line	Data
8b4d95fc	1	/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
a32d2feb DW	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*/
2f8163ba	17	#include <linux/gpio.h>
a32d2feb DW	18	#include <linux/kernel.h>
a32d2feb DW	19	#include <linux/irq.h>
a32d2feb	20	#include <linux/platform_device.h>
a32d2feb	21	#include <linux/delay.h>
7032d512	22	#include <linux/usb/msm_hsusb.h>
8b4d95fc	23	#include <linux/err.h>
bd32344a	24	#include <linux/clkdev.h>
a32d2feb DW	25
	26	#include <asm/mach-types.h>
	27	#include <asm/mach/arch.h>
	28	#include <asm/io.h>
	29	#include <asm/setup.h>
	30
a32d2feb	31	#include <mach/board.h>
d1c0d43d DW	32	#include <mach/irqs.h>
d1c0d43d DW	33	#include <mach/sirc.h>
8b4d95fc ST	34	#include <mach/vreg.h>
8b4d95fc ST	35	#include <mach/mmc.h>
a32d2feb DW	36
a32d2feb DW	37	#include "devices.h"
4312a7ef	38	#include "common.h"
a32d2feb	39
5d73c53b GB	40	static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
	41	static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
	42
	43	/* Leave smc91x resources empty here, as we'll fill them in
	44	* at run-time: they vary from board to board, and the true
	45	* configuration won't be known until boot.
	46	*/
7c63dedc	47	static struct resource smc91x_resources[] = {
5d73c53b GB	48	[0] = {
	49	.flags = IORESOURCE_MEM,
	50	},
	51	[1] = {
	52	.flags = IORESOURCE_IRQ,
	53	},
	54	};
	55
7c63dedc	56	static struct platform_device smc91x_device = {
5d73c53b GB	57	.name = "smc91x",
	58	.id = 0,
	59	.num_resources = ARRAY_SIZE(smc91x_resources),
	60	.resource = smc91x_resources,
	61	};
	62
	63	static int __init msm_init_smc91x(void)
	64	{
	65	if (machine_is_qsd8x50_surf()) {
	66	smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
	67	smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
	68	smc91x_resources[1].start =
	69	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	70	smc91x_resources[1].end =
	71	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	72	platform_device_register(&smc91x_device);
	73	}
	74
	75	return 0;
	76	}
	77	module_init(msm_init_smc91x);
	78
7032d512 PK	79	static int hsusb_phy_init_seq[] = {
	80	0x08, 0x31, /* Increase HS Driver Amplitude */
	81	0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
	82	-1
	83	};
	84
	85	static struct msm_otg_platform_data msm_otg_pdata = {
	86	.phy_init_seq = hsusb_phy_init_seq,
	87	.mode = USB_PERIPHERAL,
	88	.otg_control = OTG_PHY_CONTROL,
	89	};
	90
a32d2feb	91	static struct platform_device *devices[] __initdata = {
d1c0d43d	92	&msm_device_uart3,
88b52277	93	&msm_device_smd,
7032d512 PK	94	&msm_device_otg,
	95	&msm_device_hsusb,
	96	&msm_device_hsusb_host,
a32d2feb DW	97	};
a32d2feb DW	98
8b4d95fc ST	99	static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	100	{51, "sdc1_dat_3"},
	101	{52, "sdc1_dat_2"},
	102	{53, "sdc1_dat_1"},
	103	{54, "sdc1_dat_0"},
	104	{55, "sdc1_cmd"},
	105	{56, "sdc1_clk"}
	106	};
	107
	108	static struct vreg *vreg_mmc;
	109	static unsigned long vreg_sts;
	110
	111	static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
	112	{
	113	int rc = 0;
	114	struct platform_device *pdev;
	115
	116	pdev = container_of(dv, struct platform_device, dev);
	117
	118	if (vdd == 0) {
	119	if (!vreg_sts)
	120	return 0;
	121
	122	clear_bit(pdev->id, &vreg_sts);
	123
	124	if (!vreg_sts) {
	125	rc = vreg_disable(vreg_mmc);
	126	if (rc)
	127	pr_err("vreg_mmc disable failed for slot "
	128	"%d: %d\n", pdev->id, rc);
	129	}
	130	return 0;
	131	}
	132
	133	if (!vreg_sts) {
	134	rc = vreg_set_level(vreg_mmc, 2900);
	135	if (rc)
	136	pr_err("vreg_mmc set level failed for slot %d: %d\n",
	137	pdev->id, rc);
	138	rc = vreg_enable(vreg_mmc);
	139	if (rc)
	140	pr_err("vreg_mmc enable failed for slot %d: %d\n",
	141	pdev->id, rc);
	142	}
	143	set_bit(pdev->id, &vreg_sts);
	144	return 0;
	145	}
	146
	147	static struct msm_mmc_gpio_data sdc1_gpio = {
	148	.gpio = sdc1_gpio_cfg,
	149	.size = ARRAY_SIZE(sdc1_gpio_cfg),
	150	};
	151
	152	static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	153	.ocr_mask = MMC_VDD_27_28 \| MMC_VDD_28_29,
	154	.translate_vdd = msm_sdcc_setup_power,
	155	.gpio_data = &sdc1_gpio,
	156	};
	157
	158	static void __init qsd8x50_init_mmc(void)
	159	{
62f0988e	160	vreg_mmc = vreg_get(NULL, "gp5");
8b4d95fc ST	161
	162	if (IS_ERR(vreg_mmc)) {
	163	pr_err("vreg get for vreg_mmc failed (%ld)\n",
	164	PTR_ERR(vreg_mmc));
	165	return;
	166	}
	167
	168	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
	169	}
	170
d1c0d43d	171	static void __init qsd8x50_map_io(void)
a32d2feb	172	{
d1c0d43d DW	173	msm_map_qsd8x50_io();
d1c0d43d DW	174	msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
a32d2feb DW	175	}
a32d2feb DW	176
d1c0d43d	177	static void __init qsd8x50_init_irq(void)
a32d2feb	178	{
d1c0d43d DW	179	msm_init_irq();
d1c0d43d DW	180	msm_init_sirc();
a32d2feb DW	181	}
	182
	183	static void __init qsd8x50_init(void)
	184	{
7032d512 PK	185	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	186	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	187	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
a32d2feb	188	platform_add_devices(devices, ARRAY_SIZE(devices));
8b4d95fc	189	qsd8x50_init_mmc();
a32d2feb DW	190	}
a32d2feb DW	191
c633c531 SG	192	static void __init qsd8x50_init_late(void)
	193	{
	194	smd_debugfs_init();
	195	}
	196
a32d2feb	197	MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
f631dd41	198	.atag_offset = 0x100,
a32d2feb DW	199	.map_io = qsd8x50_map_io,
	200	.init_irq = qsd8x50_init_irq,
	201	.init_machine = qsd8x50_init,
c633c531	202	.init_late = qsd8x50_init_late,
4312a7ef	203	.timer = &qsd8x50_timer,
a32d2feb DW	204	MACHINE_END
a32d2feb DW	205
d1c0d43d	206	MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
f631dd41	207	.atag_offset = 0x100,
a32d2feb DW	208	.map_io = qsd8x50_map_io,
	209	.init_irq = qsd8x50_init_irq,
	210	.init_machine = qsd8x50_init,
c633c531	211	.init_late = qsd8x50_init_late,
4312a7ef	212	.timer = &qsd8x50_timer,
a32d2feb	213	MACHINE_END