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50bc0ef4 DW |
1 | /* linux/arch/arm/mach-msm/board-trout-mddi.c |
2 | ** Author: Brian Swetland <swetland@google.com> | |
3 | */ | |
2f8163ba | 4 | #include <linux/gpio.h> |
50bc0ef4 DW |
5 | #include <linux/kernel.h> |
6 | #include <linux/init.h> | |
7 | #include <linux/platform_device.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/leds.h> | |
50bc0ef4 DW |
10 | #include <linux/err.h> |
11 | ||
12 | #include <asm/io.h> | |
50bc0ef4 | 13 | #include <asm/mach-types.h> |
204241c2 | 14 | #include <asm/system_info.h> |
50bc0ef4 | 15 | |
1ef21f63 | 16 | #include <linux/platform_data/video-msm_fb.h> |
50bc0ef4 DW |
17 | #include <mach/vreg.h> |
18 | ||
19 | #include "board-trout.h" | |
20 | #include "proc_comm.h" | |
2dfd9c1f | 21 | #include "clock-pcom.h" |
50bc0ef4 DW |
22 | #include "devices.h" |
23 | ||
24 | #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 | |
25 | ||
26 | #define MDDI_CLIENT_CORE_BASE 0x108000 | |
27 | #define LCD_CONTROL_BLOCK_BASE 0x110000 | |
28 | #define SPI_BLOCK_BASE 0x120000 | |
29 | #define I2C_BLOCK_BASE 0x130000 | |
30 | #define PWM_BLOCK_BASE 0x140000 | |
31 | #define GPIO_BLOCK_BASE 0x150000 | |
32 | #define SYSTEM_BLOCK1_BASE 0x160000 | |
33 | #define SYSTEM_BLOCK2_BASE 0x170000 | |
34 | ||
35 | ||
36 | #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) | |
37 | #define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C) | |
38 | #define PWM0OFF (PWM_BLOCK_BASE|0x1C) | |
39 | ||
40 | #define V_VDDE2E_VDD2_GPIO 0 | |
41 | #define MDDI_RST_N 82 | |
42 | ||
43 | #define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) | |
44 | #define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) | |
45 | #define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) | |
46 | #define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) | |
47 | #define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) | |
48 | #define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) | |
49 | #define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) | |
50 | #define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) | |
51 | #define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) | |
52 | #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) | |
53 | #define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) | |
54 | #define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) | |
55 | #define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) | |
56 | #define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) | |
57 | #define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) | |
58 | #define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) | |
59 | #define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) | |
60 | #define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) | |
61 | #define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) | |
62 | #define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) | |
63 | #define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) | |
64 | #define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) | |
65 | ||
66 | #define SRST (LCD_CONTROL_BLOCK_BASE|0x00) | |
67 | #define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) | |
68 | #define START (LCD_CONTROL_BLOCK_BASE|0x08) | |
69 | #define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) | |
70 | #define CMN (LCD_CONTROL_BLOCK_BASE|0x10) | |
71 | #define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) | |
72 | #define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) | |
73 | #define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) | |
74 | #define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) | |
75 | #define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) | |
76 | #define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) | |
77 | #define PXL (LCD_CONTROL_BLOCK_BASE|0x30) | |
78 | #define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) | |
79 | #define HSW (LCD_CONTROL_BLOCK_BASE|0x38) | |
80 | #define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) | |
81 | #define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) | |
82 | #define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) | |
83 | #define VSW (LCD_CONTROL_BLOCK_BASE|0x48) | |
84 | #define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) | |
85 | #define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) | |
86 | #define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) | |
87 | #define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) | |
88 | #define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) | |
89 | #define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) | |
90 | #define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) | |
91 | #define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) | |
92 | #define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) | |
93 | #define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) | |
94 | #define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) | |
95 | #define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) | |
96 | #define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) | |
97 | #define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) | |
98 | #define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) | |
99 | #define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) | |
100 | #define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) | |
101 | ||
102 | #define SSICTL (SPI_BLOCK_BASE|0x00) | |
103 | #define SSITIME (SPI_BLOCK_BASE|0x04) | |
104 | #define SSITX (SPI_BLOCK_BASE|0x08) | |
105 | #define SSIRX (SPI_BLOCK_BASE|0x0C) | |
106 | #define SSIINTC (SPI_BLOCK_BASE|0x10) | |
107 | #define SSIINTS (SPI_BLOCK_BASE|0x14) | |
108 | #define SSIDBG1 (SPI_BLOCK_BASE|0x18) | |
109 | #define SSIDBG2 (SPI_BLOCK_BASE|0x1C) | |
110 | #define SSIID (SPI_BLOCK_BASE|0x20) | |
111 | ||
112 | #define WKREQ (SYSTEM_BLOCK1_BASE|0x00) | |
113 | #define CLKENB (SYSTEM_BLOCK1_BASE|0x04) | |
114 | #define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) | |
115 | #define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) | |
116 | #define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) | |
117 | ||
118 | #define GPIODATA (GPIO_BLOCK_BASE|0x00) | |
119 | #define GPIODIR (GPIO_BLOCK_BASE|0x04) | |
120 | #define GPIOIS (GPIO_BLOCK_BASE|0x08) | |
121 | #define GPIOIBE (GPIO_BLOCK_BASE|0x0C) | |
122 | #define GPIOIEV (GPIO_BLOCK_BASE|0x10) | |
123 | #define GPIOIE (GPIO_BLOCK_BASE|0x14) | |
124 | #define GPIORIS (GPIO_BLOCK_BASE|0x18) | |
125 | #define GPIOMIS (GPIO_BLOCK_BASE|0x1C) | |
126 | #define GPIOIC (GPIO_BLOCK_BASE|0x20) | |
127 | #define GPIOOMS (GPIO_BLOCK_BASE|0x24) | |
128 | #define GPIOPC (GPIO_BLOCK_BASE|0x28) | |
129 | #define GPIOID (GPIO_BLOCK_BASE|0x30) | |
130 | ||
131 | #define SPI_WRITE(reg, val) \ | |
132 | { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \ | |
133 | { 0, 5 }, | |
134 | ||
135 | #define SPI_WRITE1(reg) \ | |
136 | { SSITX, (reg) & 0xff }, \ | |
137 | { 0, 5 }, | |
138 | ||
139 | struct mddi_table { | |
140 | uint32_t reg; | |
141 | uint32_t value; | |
142 | }; | |
143 | static struct mddi_table mddi_toshiba_init_table[] = { | |
144 | { DPSET0, 0x09e90046 }, | |
145 | { DPSET1, 0x00000118 }, | |
146 | { DPSUS, 0x00000000 }, | |
147 | { DPRUN, 0x00000001 }, | |
148 | { 1, 14 }, /* msleep 14 */ | |
149 | { SYSCKENA, 0x00000001 }, | |
150 | { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */ | |
151 | ||
152 | { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */ | |
153 | { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */ | |
154 | { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */ | |
155 | { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */ | |
156 | { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */ | |
157 | ||
158 | { GPIOIBE, 0x000003FF }, | |
159 | { GPIOIS, 0x00000000 }, | |
160 | { GPIOIC, 0x000003FF }, | |
161 | { GPIOIE, 0x00000000 }, | |
162 | ||
163 | { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ | |
164 | { 1, 1 }, /* msleep 1 */ | |
165 | { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ | |
166 | { DRAMPWR, 0x00000001 }, /* eDRAM power */ | |
167 | }; | |
168 | ||
169 | #define GPIOSEL_VWAKEINT (1U << 0) | |
170 | #define INTMASK_VWAKEOUT (1U << 0) | |
171 | ||
172 | ||
50bc0ef4 DW |
173 | static int trout_new_backlight = 1; |
174 | static struct vreg *vreg_mddi_1v5; | |
175 | static struct vreg *vreg_lcm_2v85; | |
176 | ||
177 | static void trout_process_mddi_table(struct msm_mddi_client_data *client_data, | |
178 | struct mddi_table *table, size_t count) | |
179 | { | |
180 | int i; | |
181 | for (i = 0; i < count; i++) { | |
182 | uint32_t reg = table[i].reg; | |
183 | uint32_t value = table[i].value; | |
184 | ||
185 | if (reg == 0) | |
186 | udelay(value); | |
187 | else if (reg == 1) | |
188 | msleep(value); | |
189 | else | |
190 | client_data->remote_write(client_data, value, reg); | |
191 | } | |
192 | } | |
193 | ||
194 | static int trout_mddi_toshiba_client_init( | |
195 | struct msm_mddi_bridge_platform_data *bridge_data, | |
196 | struct msm_mddi_client_data *client_data) | |
197 | { | |
198 | int panel_id; | |
199 | ||
200 | client_data->auto_hibernate(client_data, 0); | |
201 | trout_process_mddi_table(client_data, mddi_toshiba_init_table, | |
202 | ARRAY_SIZE(mddi_toshiba_init_table)); | |
203 | client_data->auto_hibernate(client_data, 1); | |
204 | panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3; | |
205 | if (panel_id > 1) { | |
206 | printk(KERN_WARNING "unknown panel id at mddi_enable\n"); | |
207 | return -1; | |
208 | } | |
209 | return 0; | |
210 | } | |
211 | ||
212 | static int trout_mddi_toshiba_client_uninit( | |
213 | struct msm_mddi_bridge_platform_data *bridge_data, | |
214 | struct msm_mddi_client_data *client_data) | |
215 | { | |
216 | return 0; | |
217 | } | |
218 | ||
219 | static struct resource resources_msm_fb[] = { | |
220 | { | |
221 | .start = MSM_FB_BASE, | |
222 | .end = MSM_FB_BASE + MSM_FB_SIZE, | |
223 | .flags = IORESOURCE_MEM, | |
224 | }, | |
225 | }; | |
226 | ||
227 | struct msm_mddi_bridge_platform_data toshiba_client_data = { | |
228 | .init = trout_mddi_toshiba_client_init, | |
229 | .uninit = trout_mddi_toshiba_client_uninit, | |
230 | .fb_data = { | |
231 | .xres = 320, | |
232 | .yres = 480, | |
233 | .width = 45, | |
234 | .height = 67, | |
235 | .output_format = 0, | |
236 | }, | |
237 | }; | |
238 | ||
239 | static struct msm_mddi_platform_data mddi_pdata = { | |
240 | .clk_rate = 122880000, | |
241 | .fb_resource = resources_msm_fb, | |
242 | .num_clients = 1, | |
243 | .client_platform_data = { | |
244 | { | |
245 | .product_id = (0xd263 << 16 | 0), | |
246 | .name = "mddi_c_d263_0000", | |
247 | .id = 0, | |
248 | .client_data = &toshiba_client_data, | |
249 | .clk_rate = 0, | |
250 | }, | |
251 | }, | |
252 | }; | |
253 | ||
254 | int __init trout_init_panel(void) | |
255 | { | |
256 | int rc; | |
257 | ||
258 | if (!machine_is_trout()) | |
259 | return 0; | |
260 | vreg_mddi_1v5 = vreg_get(0, "gp2"); | |
261 | if (IS_ERR(vreg_mddi_1v5)) | |
262 | return PTR_ERR(vreg_mddi_1v5); | |
263 | vreg_lcm_2v85 = vreg_get(0, "gp4"); | |
264 | if (IS_ERR(vreg_lcm_2v85)) | |
265 | return PTR_ERR(vreg_lcm_2v85); | |
266 | ||
267 | trout_new_backlight = system_rev >= 5; | |
268 | if (trout_new_backlight) { | |
269 | uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, | |
270 | GPIO_NO_PULL, GPIO_8MA); | |
271 | msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); | |
272 | } else { | |
273 | uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, | |
274 | GPIO_NO_PULL, GPIO_8MA); | |
2dfd9c1f SB |
275 | uint32_t id = P_GP_CLK; |
276 | uint32_t rate = 19200000; | |
277 | ||
50bc0ef4 DW |
278 | msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); |
279 | ||
2dfd9c1f SB |
280 | msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate); |
281 | if (id < 0) | |
282 | pr_err("trout_init_panel: set clock rate failed\n"); | |
50bc0ef4 DW |
283 | } |
284 | ||
285 | rc = platform_device_register(&msm_device_mdp); | |
286 | if (rc) | |
287 | return rc; | |
288 | msm_device_mddi0.dev.platform_data = &mddi_pdata; | |
289 | return platform_device_register(&msm_device_mddi0); | |
290 | } | |
291 | ||
292 | device_initcall(trout_init_panel); |