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3042102a BS |
1 | /* arch/arm/mach-msm/io.c |
2 | * | |
cf62ffae | 3 | * MSM7K, QSD io support |
3042102a BS |
4 | * |
5 | * Copyright (C) 2007 Google, Inc. | |
8c27e6f3 | 6 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
3042102a BS |
7 | * Author: Brian Swetland <swetland@google.com> |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
dc28094b | 23 | #include <linux/export.h> |
3042102a | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
3042102a | 26 | #include <asm/page.h> |
a09e64fb | 27 | #include <mach/msm_iomap.h> |
3042102a BS |
28 | #include <asm/mach/map.h> |
29 | ||
a09e64fb | 30 | #include <mach/board.h> |
3042102a | 31 | |
8c27e6f3 | 32 | #define MSM_CHIP_DEVICE(name, chip) { \ |
bcc0f6af | 33 | .virtual = (unsigned long) MSM_##name##_BASE, \ |
8c27e6f3 DB |
34 | .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ |
35 | .length = chip##_##name##_SIZE, \ | |
3042102a BS |
36 | .type = MT_DEVICE_NONSHARED, \ |
37 | } | |
38 | ||
8c27e6f3 DB |
39 | #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) |
40 | ||
cf62ffae DW |
41 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ |
42 | || defined(CONFIG_ARCH_MSM7X25) | |
3042102a BS |
43 | static struct map_desc msm_io_desc[] __initdata = { |
44 | MSM_DEVICE(VIC), | |
8c27e6f3 | 45 | MSM_CHIP_DEVICE(CSR, MSM7X00), |
3042102a | 46 | MSM_DEVICE(DMOV), |
03db0729 DB |
47 | MSM_CHIP_DEVICE(GPIO1, MSM7X00), |
48 | MSM_CHIP_DEVICE(GPIO2, MSM7X00), | |
3042102a | 49 | MSM_DEVICE(CLK_CTL), |
650e3f0d SB |
50 | #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ |
51 | defined(CONFIG_DEBUG_MSM_UART3) | |
6339f669 | 52 | MSM_DEVICE(DEBUG_UART), |
b42dc44a DZ |
53 | #endif |
54 | #ifdef CONFIG_ARCH_MSM7X30 | |
55 | MSM_DEVICE(GCC), | |
6339f669 | 56 | #endif |
3042102a | 57 | { |
bcc0f6af | 58 | .virtual = (unsigned long) MSM_SHARED_RAM_BASE, |
cf62ffae | 59 | .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), |
3042102a BS |
60 | .length = MSM_SHARED_RAM_SIZE, |
61 | .type = MT_DEVICE, | |
62 | }, | |
63 | }; | |
64 | ||
65 | void __init msm_map_common_io(void) | |
66 | { | |
67 | /* Make sure the peripheral register window is closed, since | |
68 | * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which | |
69 | * pages are peripheral interface or not. | |
70 | */ | |
71 | asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); | |
3042102a BS |
72 | iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); |
73 | } | |
cf62ffae DW |
74 | #endif |
75 | ||
76 | #ifdef CONFIG_ARCH_QSD8X50 | |
77 | static struct map_desc qsd8x50_io_desc[] __initdata = { | |
78 | MSM_DEVICE(VIC), | |
8c27e6f3 | 79 | MSM_CHIP_DEVICE(CSR, QSD8X50), |
cf62ffae | 80 | MSM_DEVICE(DMOV), |
03db0729 DB |
81 | MSM_CHIP_DEVICE(GPIO1, QSD8X50), |
82 | MSM_CHIP_DEVICE(GPIO2, QSD8X50), | |
cf62ffae DW |
83 | MSM_DEVICE(CLK_CTL), |
84 | MSM_DEVICE(SIRC), | |
85 | MSM_DEVICE(SCPLL), | |
86 | MSM_DEVICE(AD5), | |
87 | MSM_DEVICE(MDC), | |
650e3f0d SB |
88 | #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ |
89 | defined(CONFIG_DEBUG_MSM_UART3) | |
cf62ffae DW |
90 | MSM_DEVICE(DEBUG_UART), |
91 | #endif | |
92 | { | |
93 | .virtual = (unsigned long) MSM_SHARED_RAM_BASE, | |
94 | .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), | |
95 | .length = MSM_SHARED_RAM_SIZE, | |
96 | .type = MT_DEVICE, | |
97 | }, | |
98 | }; | |
99 | ||
100 | void __init msm_map_qsd8x50_io(void) | |
101 | { | |
102 | iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); | |
103 | } | |
104 | #endif /* CONFIG_ARCH_QSD8X50 */ | |
3042102a | 105 | |
6cf6dfef SM |
106 | #ifdef CONFIG_ARCH_MSM8X60 |
107 | static struct map_desc msm8x60_io_desc[] __initdata = { | |
8bb06444 DB |
108 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), |
109 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), | |
8c27e6f3 DB |
110 | MSM_CHIP_DEVICE(TMR, MSM8X60), |
111 | MSM_CHIP_DEVICE(TMR0, MSM8X60), | |
6cf6dfef SM |
112 | MSM_DEVICE(ACC), |
113 | MSM_DEVICE(GCC), | |
a3d3ef9d SB |
114 | #ifdef CONFIG_DEBUG_MSM8660_UART |
115 | MSM_DEVICE(DEBUG_UART), | |
116 | #endif | |
6cf6dfef SM |
117 | }; |
118 | ||
119 | void __init msm_map_msm8x60_io(void) | |
120 | { | |
121 | iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc)); | |
122 | } | |
123 | #endif /* CONFIG_ARCH_MSM8X60 */ | |
124 | ||
5d0afd74 SM |
125 | #ifdef CONFIG_ARCH_MSM8960 |
126 | static struct map_desc msm8960_io_desc[] __initdata = { | |
127 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), | |
128 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), | |
129 | MSM_CHIP_DEVICE(TMR, MSM8960), | |
130 | MSM_CHIP_DEVICE(TMR0, MSM8960), | |
a3d3ef9d SB |
131 | #ifdef CONFIG_DEBUG_MSM8960_UART |
132 | MSM_DEVICE(DEBUG_UART), | |
133 | #endif | |
5d0afd74 SM |
134 | }; |
135 | ||
136 | void __init msm_map_msm8960_io(void) | |
137 | { | |
138 | iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); | |
139 | } | |
140 | #endif /* CONFIG_ARCH_MSM8960 */ | |
141 | ||
c83b2bf6 DW |
142 | #ifdef CONFIG_ARCH_MSM7X30 |
143 | static struct map_desc msm7x30_io_desc[] __initdata = { | |
144 | MSM_DEVICE(VIC), | |
8c27e6f3 | 145 | MSM_CHIP_DEVICE(CSR, MSM7X30), |
c83b2bf6 | 146 | MSM_DEVICE(DMOV), |
03db0729 DB |
147 | MSM_CHIP_DEVICE(GPIO1, MSM7X30), |
148 | MSM_CHIP_DEVICE(GPIO2, MSM7X30), | |
c83b2bf6 DW |
149 | MSM_DEVICE(CLK_CTL), |
150 | MSM_DEVICE(CLK_CTL_SH2), | |
151 | MSM_DEVICE(AD5), | |
152 | MSM_DEVICE(MDC), | |
153 | MSM_DEVICE(ACC), | |
154 | MSM_DEVICE(SAW), | |
155 | MSM_DEVICE(GCC), | |
156 | MSM_DEVICE(TCSR), | |
650e3f0d SB |
157 | #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ |
158 | defined(CONFIG_DEBUG_MSM_UART3) | |
c83b2bf6 DW |
159 | MSM_DEVICE(DEBUG_UART), |
160 | #endif | |
161 | { | |
162 | .virtual = (unsigned long) MSM_SHARED_RAM_BASE, | |
163 | .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), | |
164 | .length = MSM_SHARED_RAM_SIZE, | |
165 | .type = MT_DEVICE, | |
166 | }, | |
167 | }; | |
168 | ||
169 | void __init msm_map_msm7x30_io(void) | |
170 | { | |
171 | iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); | |
172 | } | |
173 | #endif /* CONFIG_ARCH_MSM7X30 */ | |
174 | ||
3042102a BS |
175 | void __iomem * |
176 | __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | |
177 | { | |
178 | if (mtype == MT_DEVICE) { | |
179 | /* The peripherals in the 88000000 - D0000000 range | |
b595076a | 180 | * are only accessible by type MT_DEVICE_NONSHARED. |
3042102a BS |
181 | * Adjust mtype as necessary to make this "just work." |
182 | */ | |
183 | if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000)) | |
184 | mtype = MT_DEVICE_NONSHARED; | |
185 | } | |
186 | ||
31aa8fd6 RK |
187 | return __arm_ioremap_caller(phys_addr, size, mtype, |
188 | __builtin_return_address(0)); | |
3042102a | 189 | } |
4916a108 | 190 | EXPORT_SYMBOL(__msm_ioremap); |