[deliverable/linux.git] / arch / arm / mach-mvebu / coherency.c

/*
 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370 and Armada XP SOCs have a coherency fabric which is
 * responsible for ensuring hardware coherency between all CPUs and between
 * CPUs and I/O masters. This file initializes the coherency fabric and
 * supplies basic routines for configuring and controlling hardware coherency
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/smp_plat.h>
#include "armada-370-xp.h"

static void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

/* Coherency fabric registers */
#define COHERENCY_FABRIC_CFG_OFFSET		   0x4

#define IO_SYNC_BARRIER_CTL_OFFSET		   0x0

static struct of_device_id of_coherency_table[] = {
	{.compatible = "marvell,coherency-fabric"},
	{ /* end of list */ },
};

/* Function defined in coherency_ll.S */
int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);

int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
{
	if (!coherency_base) {
		pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
		pr_warn("Coherency fabric is not initialized\n");
		return 1;
	}

	return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
}

static inline void mvebu_hwcc_sync_io_barrier(void)
{
	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
}

static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
				  unsigned long offset, size_t size,
				  enum dma_data_direction dir,
				  struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
}


static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
			      size_t size, enum dma_data_direction dir,
			      struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
			size_t size, enum dma_data_direction dir)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static struct dma_map_ops mvebu_hwcc_dma_ops = {
	.alloc			= arm_dma_alloc,
	.free			= arm_dma_free,
	.mmap			= arm_dma_mmap,
	.map_page		= mvebu_hwcc_dma_map_page,
	.unmap_page		= mvebu_hwcc_dma_unmap_page,
	.get_sgtable		= arm_dma_get_sgtable,
	.map_sg			= arm_dma_map_sg,
	.unmap_sg		= arm_dma_unmap_sg,
	.sync_single_for_cpu	= mvebu_hwcc_dma_sync,
	.sync_single_for_device	= mvebu_hwcc_dma_sync,
	.sync_sg_for_cpu	= arm_dma_sync_sg_for_cpu,
	.sync_sg_for_device	= arm_dma_sync_sg_for_device,
	.set_dma_mask		= arm_dma_set_mask,
};

static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
				       unsigned long event, void *__dev)
{
	struct device *dev = __dev;

	if (event != BUS_NOTIFY_ADD_DEVICE)
		return NOTIFY_DONE;
	set_dma_ops(dev, &mvebu_hwcc_dma_ops);

	return NOTIFY_OK;
}

static struct notifier_block mvebu_hwcc_platform_nb = {
	.notifier_call = mvebu_hwcc_platform_notifier,
};

int __init coherency_init(void)
{
	struct device_node *np;

	np = of_find_matching_node(NULL, of_coherency_table);
	if (np) {
		pr_info("Initializing Coherency fabric\n");
		coherency_base = of_iomap(np, 0);
		coherency_cpu_base = of_iomap(np, 1);
		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
	}

	return 0;
}

static int __init coherency_late_init(void)
{
	bus_register_notifier(&platform_bus_type,
			      &mvebu_hwcc_platform_nb);
	return 0;
}

postcore_initcall(coherency_late_init);
Commit	Line	Data
009f1315 GC	1	/*
	2	* Coherency fabric (Aurora) support for Armada 370 and XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Yehuda Yitschak <yehuday@marvell.com>
	7	* Gregory Clement <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* The Armada 370 and Armada XP SOCs have a coherency fabric which is
	15	* responsible for ensuring hardware coherency between all CPUs and between
	16	* CPUs and I/O masters. This file initializes the coherency fabric and
	17	* supplies basic routines for configuring and controlling hardware coherency
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/of_address.h>
	23	#include <linux/io.h>
	24	#include <linux/smp.h>
e60304f8 GC	25	#include <linux/dma-mapping.h>
e60304f8 GC	26	#include <linux/platform_device.h>
009f1315 GC	27	#include <asm/smp_plat.h>
	28	#include "armada-370-xp.h"
	29
865e0527	30	static void __iomem *coherency_base;
e60304f8	31	static void __iomem *coherency_cpu_base;
009f1315 GC	32
	33	/* Coherency fabric registers */
	34	#define COHERENCY_FABRIC_CFG_OFFSET 0x4
	35
e60304f8 GC	36	#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
e60304f8 GC	37
009f1315 GC	38	static struct of_device_id of_coherency_table[] = {
	39	{.compatible = "marvell,coherency-fabric"},
	40	{ /* end of list */ },
	41	};
	42
009f1315 GC	43	/* Function defined in coherency_ll.S */
	44	int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
	45
	46	int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
	47	{
	48	if (!coherency_base) {
	49	pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
	50	pr_warn("Coherency fabric is not initialized\n");
	51	return 1;
	52	}
	53
	54	return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
	55	}
	56
e60304f8 GC	57	static inline void mvebu_hwcc_sync_io_barrier(void)
	58	{
	59	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	60	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
	61	}
	62
	63	static dma_addr_t mvebu_hwcc_dma_map_page(struct device dev, struct page page,
	64	unsigned long offset, size_t size,
	65	enum dma_data_direction dir,
	66	struct dma_attrs *attrs)
	67	{
	68	if (dir != DMA_TO_DEVICE)
	69	mvebu_hwcc_sync_io_barrier();
	70	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
	71	}
	72
	73
	74	static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
	75	size_t size, enum dma_data_direction dir,
	76	struct dma_attrs *attrs)
	77	{
	78	if (dir != DMA_TO_DEVICE)
	79	mvebu_hwcc_sync_io_barrier();
	80	}
	81
	82	static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
	83	size_t size, enum dma_data_direction dir)
	84	{
	85	if (dir != DMA_TO_DEVICE)
	86	mvebu_hwcc_sync_io_barrier();
	87	}
	88
	89	static struct dma_map_ops mvebu_hwcc_dma_ops = {
	90	.alloc = arm_dma_alloc,
	91	.free = arm_dma_free,
	92	.mmap = arm_dma_mmap,
	93	.map_page = mvebu_hwcc_dma_map_page,
	94	.unmap_page = mvebu_hwcc_dma_unmap_page,
	95	.get_sgtable = arm_dma_get_sgtable,
	96	.map_sg = arm_dma_map_sg,
	97	.unmap_sg = arm_dma_unmap_sg,
	98	.sync_single_for_cpu = mvebu_hwcc_dma_sync,
	99	.sync_single_for_device = mvebu_hwcc_dma_sync,
	100	.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
	101	.sync_sg_for_device = arm_dma_sync_sg_for_device,
	102	.set_dma_mask = arm_dma_set_mask,
	103	};
	104
	105	static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
	106	unsigned long event, void *__dev)
	107	{
	108	struct device *dev = __dev;
	109
	110	if (event != BUS_NOTIFY_ADD_DEVICE)
	111	return NOTIFY_DONE;
	112	set_dma_ops(dev, &mvebu_hwcc_dma_ops);
	113
	114	return NOTIFY_OK;
	115	}
	116
	117	static struct notifier_block mvebu_hwcc_platform_nb = {
	118	.notifier_call = mvebu_hwcc_platform_notifier,
	119	};
	120
009f1315 GC	121	int __init coherency_init(void)
	122	{
	123	struct device_node *np;
	124
	125	np = of_find_matching_node(NULL, of_coherency_table);
	126	if (np) {
	127	pr_info("Initializing Coherency fabric\n");
	128	coherency_base = of_iomap(np, 0);
e60304f8 GC	129	coherency_cpu_base = of_iomap(np, 1);
e60304f8 GC	130	set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
009f1315 GC	131	}
	132
	133	return 0;
	134	}
865e0527 TP	135
	136	static int __init coherency_late_init(void)
	137	{
	138	bus_register_notifier(&platform_bus_type,
	139	&mvebu_hwcc_platform_nb);
	140	return 0;
	141	}
	142
	143	postcore_initcall(coherency_late_init);