[deliverable/linux.git] / arch / arm / mach-mvebu / coherency.c

/*
 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370 and Armada XP SOCs have a coherency fabric which is
 * responsible for ensuring hardware coherency between all CPUs and between
 * CPUs and I/O masters. This file initializes the coherency fabric and
 * supplies basic routines for configuring and controlling hardware coherency
 */

#define pr_fmt(fmt) "mvebu-coherency: " fmt

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <linux/clk.h>
#include <linux/pci.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include "armada-370-xp.h"
#include "coherency.h"
#include "mvebu-soc-id.h"

unsigned long coherency_phys_base;
void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

/* Coherency fabric registers */
#define COHERENCY_FABRIC_CFG_OFFSET		   0x4

#define IO_SYNC_BARRIER_CTL_OFFSET		   0x0

enum {
	COHERENCY_FABRIC_TYPE_NONE,
	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
	COHERENCY_FABRIC_TYPE_ARMADA_375,
	COHERENCY_FABRIC_TYPE_ARMADA_380,
};

static struct of_device_id of_coherency_table[] = {
	{.compatible = "marvell,coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
	{.compatible = "marvell,armada-375-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
	{.compatible = "marvell,armada-380-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
	{ /* end of list */ },
};

/* Functions defined in coherency_ll.S */
int ll_enable_coherency(void);
void ll_add_cpu_to_smp_group(void);

int set_cpu_coherent(void)
{
	if (!coherency_base) {
		pr_warn("Can't make current CPU cache coherent.\n");
		pr_warn("Coherency fabric is not initialized\n");
		return 1;
	}

	ll_add_cpu_to_smp_group();
	return ll_enable_coherency();
}

/*
 * The below code implements the I/O coherency workaround on Armada
 * 375. This workaround consists in using the two channels of the
 * first XOR engine to trigger a XOR transaction that serves as the
 * I/O coherency barrier.
 */

static void __iomem *xor_base, *xor_high_base;
static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS];
static void *coherency_wa_buf[CONFIG_NR_CPUS];
static bool coherency_wa_enabled;

#define XOR_CONFIG(chan)            (0x10 + (chan * 4))
#define XOR_ACTIVATION(chan)        (0x20 + (chan * 4))
#define WINDOW_BAR_ENABLE(chan)     (0x240 + ((chan) << 2))
#define WINDOW_BASE(w)              (0x250 + ((w) << 2))
#define WINDOW_SIZE(w)              (0x270 + ((w) << 2))
#define WINDOW_REMAP_HIGH(w)        (0x290 + ((w) << 2))
#define WINDOW_OVERRIDE_CTRL(chan)  (0x2A0 + ((chan) << 2))
#define XOR_DEST_POINTER(chan)      (0x2B0 + (chan * 4))
#define XOR_BLOCK_SIZE(chan)        (0x2C0 + (chan * 4))
#define XOR_INIT_VALUE_LOW           0x2E0
#define XOR_INIT_VALUE_HIGH          0x2E4

static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void)
{
	int idx = smp_processor_id();

	/* Write '1' to the first word of the buffer */
	writel(0x1, coherency_wa_buf[idx]);

	/* Wait until the engine is idle */
	while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3)
		;

	dmb();

	/* Trigger channel */
	writel(0x1, xor_base + XOR_ACTIVATION(idx));

	/* Poll the data until it is cleared by the XOR transaction */
	while (readl(coherency_wa_buf[idx]))
		;
}

static void __init armada_375_coherency_init_wa(void)
{
	const struct mbus_dram_target_info *dram;
	struct device_node *xor_node;
	struct property *xor_status;
	struct clk *xor_clk;
	u32 win_enable = 0;
	int i;

	pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n");

	/*
	 * Since the workaround uses one XOR engine, we grab a
	 * reference to its Device Tree node first.
	 */
	xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor");
	BUG_ON(!xor_node);

	/*
	 * Then we mark it as disabled so that the real XOR driver
	 * will not use it.
	 */
	xor_status = kzalloc(sizeof(struct property), GFP_KERNEL);
	BUG_ON(!xor_status);

	xor_status->value = kstrdup("disabled", GFP_KERNEL);
	BUG_ON(!xor_status->value);

	xor_status->length = 8;
	xor_status->name = kstrdup("status", GFP_KERNEL);
	BUG_ON(!xor_status->name);

	of_update_property(xor_node, xor_status);

	/*
	 * And we remap the registers, get the clock, and do the
	 * initial configuration of the XOR engine.
	 */
	xor_base = of_iomap(xor_node, 0);
	xor_high_base = of_iomap(xor_node, 1);

	xor_clk = of_clk_get_by_name(xor_node, NULL);
	BUG_ON(!xor_clk);

	clk_prepare_enable(xor_clk);

	dram = mv_mbus_dram_info();

	for (i = 0; i < 8; i++) {
		writel(0, xor_base + WINDOW_BASE(i));
		writel(0, xor_base + WINDOW_SIZE(i));
		if (i < 4)
			writel(0, xor_base + WINDOW_REMAP_HIGH(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;
		writel((cs->base & 0xffff0000) |
		       (cs->mbus_attr << 8) |
		       dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i));
		writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i));

		win_enable |= (1 << i);
		win_enable |= 3 << (16 + (2 * i));
	}

	writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0));
	writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1));
	writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0));
	writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1));

	for (i = 0; i < CONFIG_NR_CPUS; i++) {
		coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL);
		BUG_ON(!coherency_wa_buf[i]);

		/*
		 * We can't use the DMA mapping API, since we don't
		 * have a valid 'struct device' pointer
		 */
		coherency_wa_buf_phys[i] =
			virt_to_phys(coherency_wa_buf[i]);
		BUG_ON(!coherency_wa_buf_phys[i]);

		/*
		 * Configure the XOR engine for memset operation, with
		 * a 128 bytes block size
		 */
		writel(0x444, xor_base + XOR_CONFIG(i));
		writel(128, xor_base + XOR_BLOCK_SIZE(i));
		writel(coherency_wa_buf_phys[i],
		       xor_base + XOR_DEST_POINTER(i));
	}

	writel(0x0, xor_base + XOR_INIT_VALUE_LOW);
	writel(0x0, xor_base + XOR_INIT_VALUE_HIGH);

	coherency_wa_enabled = true;
}

static inline void mvebu_hwcc_sync_io_barrier(void)
{
	if (coherency_wa_enabled) {
		mvebu_hwcc_armada375_sync_io_barrier_wa();
		return;
	}

	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
}

static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
				  unsigned long offset, size_t size,
				  enum dma_data_direction dir,
				  struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
}


static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
			      size_t size, enum dma_data_direction dir,
			      struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
			size_t size, enum dma_data_direction dir)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static struct dma_map_ops mvebu_hwcc_dma_ops = {
	.alloc			= arm_dma_alloc,
	.free			= arm_dma_free,
	.mmap			= arm_dma_mmap,
	.map_page		= mvebu_hwcc_dma_map_page,
	.unmap_page		= mvebu_hwcc_dma_unmap_page,
	.get_sgtable		= arm_dma_get_sgtable,
	.map_sg			= arm_dma_map_sg,
	.unmap_sg		= arm_dma_unmap_sg,
	.sync_single_for_cpu	= mvebu_hwcc_dma_sync,
	.sync_single_for_device	= mvebu_hwcc_dma_sync,
	.sync_sg_for_cpu	= arm_dma_sync_sg_for_cpu,
	.sync_sg_for_device	= arm_dma_sync_sg_for_device,
	.set_dma_mask		= arm_dma_set_mask,
};

static int mvebu_hwcc_notifier(struct notifier_block *nb,
			       unsigned long event, void *__dev)
{
	struct device *dev = __dev;

	if (event != BUS_NOTIFY_ADD_DEVICE)
		return NOTIFY_DONE;
	set_dma_ops(dev, &mvebu_hwcc_dma_ops);

	return NOTIFY_OK;
}

static struct notifier_block mvebu_hwcc_nb = {
	.notifier_call = mvebu_hwcc_notifier,
};

static void __init armada_370_coherency_init(struct device_node *np)
{
	struct resource res;

	of_address_to_resource(np, 0, &res);
	coherency_phys_base = res.start;
	/*
	 * Ensure secondary CPUs will see the updated value,
	 * which they read before they join the coherency
	 * fabric, and therefore before they are coherent with
	 * the boot CPU cache.
	 */
	sync_cache_w(&coherency_phys_base);
	coherency_base = of_iomap(np, 0);
	coherency_cpu_base = of_iomap(np, 1);
	set_cpu_coherent();
}

/*
 * This ioremap hook is used on Armada 375/38x to ensure that PCIe
 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
 * is needed as a workaround for a deadlock issue between the PCIe
 * interface and the cache controller.
 */
static void __iomem *
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
			      unsigned int mtype, void *caller)
{
	struct resource pcie_mem;

	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);

	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
		mtype = MT_UNCACHED;

	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}

static void __init armada_375_380_coherency_init(struct device_node *np)
{
	struct device_node *cache_dn;

	coherency_cpu_base = of_iomap(np, 0);
	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;

	/*
	 * Add the PL310 property "arm,io-coherent". This makes sure the
	 * outer sync operation is not used, which allows to
	 * workaround the system erratum that causes deadlocks when
	 * doing PCIe in an SMP situation on Armada 375 and Armada
	 * 38x.
	 */
	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
		struct property *p;

		p = kzalloc(sizeof(*p), GFP_KERNEL);
		p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
		of_add_property(cache_dn, p);
	}
}

static int coherency_type(void)
{
	struct device_node *np;
	const struct of_device_id *match;

	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
	if (np) {
		int type = (int) match->data;

		/* Armada 370/XP coherency works in both UP and SMP */
		if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
			return type;

		/* Armada 375 coherency works only on SMP */
		else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())
			return type;

		/* Armada 380 coherency works only on SMP */
		else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
			return type;
	}

	return COHERENCY_FABRIC_TYPE_NONE;
}

int coherency_available(void)
{
	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
}

int __init coherency_init(void)
{
	int type = coherency_type();
	struct device_node *np;

	np = of_find_matching_node(NULL, of_coherency_table);

	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
		armada_370_coherency_init(np);
	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
		 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
		armada_375_380_coherency_init(np);

	return 0;
}

static int __init coherency_late_init(void)
{
	int type = coherency_type();

	if (type == COHERENCY_FABRIC_TYPE_NONE)
		return 0;

	if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) {
		u32 dev, rev;

		if (mvebu_get_soc_id(&dev, &rev) == 0 &&
		    rev == ARMADA_375_Z1_REV)
			armada_375_coherency_init_wa();
	}

	bus_register_notifier(&platform_bus_type,
			      &mvebu_hwcc_nb);

	return 0;
}

postcore_initcall(coherency_late_init);

static int __init coherency_pci_init(void)
{
	if (coherency_available())
		bus_register_notifier(&pci_bus_type,
				       &mvebu_hwcc_nb);
	return 0;
}

arch_initcall(coherency_pci_init);
Commit	Line	Data
009f1315 GC	1	/*
	2	* Coherency fabric (Aurora) support for Armada 370 and XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Yehuda Yitschak <yehuday@marvell.com>
	7	* Gregory Clement <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* The Armada 370 and Armada XP SOCs have a coherency fabric which is
	15	* responsible for ensuring hardware coherency between all CPUs and between
	16	* CPUs and I/O masters. This file initializes the coherency fabric and
	17	* supplies basic routines for configuring and controlling hardware coherency
	18	*/
	19
5ab5afd8 TP	20	#define pr_fmt(fmt) "mvebu-coherency: " fmt
5ab5afd8 TP	21
009f1315 GC	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/of_address.h>
	25	#include <linux/io.h>
	26	#include <linux/smp.h>
e60304f8 GC	27	#include <linux/dma-mapping.h>
e60304f8 GC	28	#include <linux/platform_device.h>
5ab5afd8 TP	29	#include <linux/slab.h>
	30	#include <linux/mbus.h>
	31	#include <linux/clk.h>
b0063aad	32	#include <linux/pci.h>
009f1315	33	#include <asm/smp_plat.h>
580ff0ee	34	#include <asm/cacheflush.h>
497a9230	35	#include <asm/mach/map.h>
009f1315	36	#include "armada-370-xp.h"
b12634e3	37	#include "coherency.h"
39438567	38	#include "mvebu-soc-id.h"
009f1315	39
8bd26e3a	40	unsigned long coherency_phys_base;
ccd6a131	41	void __iomem *coherency_base;
e60304f8	42	static void __iomem *coherency_cpu_base;
009f1315 GC	43
	44	/* Coherency fabric registers */
	45	#define COHERENCY_FABRIC_CFG_OFFSET 0x4
	46
e60304f8 GC	47	#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
e60304f8 GC	48
924d38f4	49	enum {
501f928e	50	COHERENCY_FABRIC_TYPE_NONE,
924d38f4	51	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
77fa4b9a	52	COHERENCY_FABRIC_TYPE_ARMADA_375,
d0de9323	53	COHERENCY_FABRIC_TYPE_ARMADA_380,
924d38f4 TP	54	};
924d38f4 TP	55
009f1315	56	static struct of_device_id of_coherency_table[] = {
924d38f4 TP	57	{.compatible = "marvell,coherency-fabric",
924d38f4 TP	58	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
77fa4b9a TP	59	{.compatible = "marvell,armada-375-coherency-fabric",
77fa4b9a TP	60	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
d0de9323 TP	61	{.compatible = "marvell,armada-380-coherency-fabric",
d0de9323 TP	62	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
009f1315 GC	63	{ /* end of list */ },
	64	};
	65
2e8a5942 GC	66	/* Functions defined in coherency_ll.S */
	67	int ll_enable_coherency(void);
	68	void ll_add_cpu_to_smp_group(void);
009f1315	69
952f4ca7	70	int set_cpu_coherent(void)
009f1315 GC	71	{
009f1315 GC	72	if (!coherency_base) {
b41375f7	73	pr_warn("Can't make current CPU cache coherent.\n");
009f1315 GC	74	pr_warn("Coherency fabric is not initialized\n");
	75	return 1;
	76	}
	77
2e8a5942 GC	78	ll_add_cpu_to_smp_group();
2e8a5942 GC	79	return ll_enable_coherency();
009f1315 GC	80	}
009f1315 GC	81
5ab5afd8 TP	82	/*
	83	* The below code implements the I/O coherency workaround on Armada
	84	* 375. This workaround consists in using the two channels of the
	85	* first XOR engine to trigger a XOR transaction that serves as the
	86	* I/O coherency barrier.
	87	*/
	88
	89	static void __iomem xor_base, xor_high_base;
	90	static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS];
	91	static void *coherency_wa_buf[CONFIG_NR_CPUS];
	92	static bool coherency_wa_enabled;
	93
	94	#define XOR_CONFIG(chan) (0x10 + (chan * 4))
	95	#define XOR_ACTIVATION(chan) (0x20 + (chan * 4))
	96	#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
	97	#define WINDOW_BASE(w) (0x250 + ((w) << 2))
	98	#define WINDOW_SIZE(w) (0x270 + ((w) << 2))
	99	#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
	100	#define WINDOW_OVERRIDE_CTRL(chan) (0x2A0 + ((chan) << 2))
	101	#define XOR_DEST_POINTER(chan) (0x2B0 + (chan * 4))
	102	#define XOR_BLOCK_SIZE(chan) (0x2C0 + (chan * 4))
	103	#define XOR_INIT_VALUE_LOW 0x2E0
	104	#define XOR_INIT_VALUE_HIGH 0x2E4
	105
	106	static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void)
	107	{
	108	int idx = smp_processor_id();
	109
	110	/* Write '1' to the first word of the buffer */
	111	writel(0x1, coherency_wa_buf[idx]);
	112
	113	/* Wait until the engine is idle */
	114	while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3)
	115	;
	116
	117	dmb();
	118
	119	/* Trigger channel */
	120	writel(0x1, xor_base + XOR_ACTIVATION(idx));
	121
	122	/* Poll the data until it is cleared by the XOR transaction */
	123	while (readl(coherency_wa_buf[idx]))
	124	;
	125	}
	126
	127	static void __init armada_375_coherency_init_wa(void)
	128	{
	129	const struct mbus_dram_target_info *dram;
	130	struct device_node *xor_node;
	131	struct property *xor_status;
	132	struct clk *xor_clk;
	133	u32 win_enable = 0;
	134	int i;
	135
	136	pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n");
	137
	138	/*
	139	* Since the workaround uses one XOR engine, we grab a
	140	* reference to its Device Tree node first.
	141	*/
	142	xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor");
	143	BUG_ON(!xor_node);
	144
	145	/*
146	* Then we mark it as disabled so that the real XOR driver
147	* will not use it.
148	*/
149	xor_status = kzalloc(sizeof(struct property), GFP_KERNEL);
150	BUG_ON(!xor_status);
151
152	xor_status->value = kstrdup("disabled", GFP_KERNEL);
153	BUG_ON(!xor_status->value);
154
155	xor_status->length = 8;
156	xor_status->name = kstrdup("status", GFP_KERNEL);
157	BUG_ON(!xor_status->name);
158
159	of_update_property(xor_node, xor_status);
160
161	/*
162	* And we remap the registers, get the clock, and do the
163	* initial configuration of the XOR engine.
164	*/
165	xor_base = of_iomap(xor_node, 0);
166	xor_high_base = of_iomap(xor_node, 1);
167
168	xor_clk = of_clk_get_by_name(xor_node, NULL);
169	BUG_ON(!xor_clk);
170
171	clk_prepare_enable(xor_clk);
172
173	dram = mv_mbus_dram_info();
174
175	for (i = 0; i < 8; i++) {
176	writel(0, xor_base + WINDOW_BASE(i));
177	writel(0, xor_base + WINDOW_SIZE(i));
178	if (i < 4)
179	writel(0, xor_base + WINDOW_REMAP_HIGH(i));
180	}
181
182	for (i = 0; i < dram->num_cs; i++) {
183	const struct mbus_dram_window *cs = dram->cs + i;
184	writel((cs->base & 0xffff0000) \|
185	(cs->mbus_attr << 8) \|
186	dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i));
187	writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i));
188
189	win_enable \|= (1 << i);
190	win_enable \|= 3 << (16 + (2 * i));
191	}
192
193	writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0));
194	writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1));
195	writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0));
196	writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1));
197
198	for (i = 0; i < CONFIG_NR_CPUS; i++) {
199	coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL);
200	BUG_ON(!coherency_wa_buf[i]);
201
202	/*
203	* We can't use the DMA mapping API, since we don't
204	* have a valid 'struct device' pointer
205	*/
206	coherency_wa_buf_phys[i] =
207	virt_to_phys(coherency_wa_buf[i]);
208	BUG_ON(!coherency_wa_buf_phys[i]);
209
210	/*
211	* Configure the XOR engine for memset operation, with
212	* a 128 bytes block size
213	*/
214	writel(0x444, xor_base + XOR_CONFIG(i));
215	writel(128, xor_base + XOR_BLOCK_SIZE(i));
216	writel(coherency_wa_buf_phys[i],
217	xor_base + XOR_DEST_POINTER(i));
218	}
219
220	writel(0x0, xor_base + XOR_INIT_VALUE_LOW);
221	writel(0x0, xor_base + XOR_INIT_VALUE_HIGH);
222
223	coherency_wa_enabled = true;
224	}
225
e60304f8 GC	226	static inline void mvebu_hwcc_sync_io_barrier(void)
e60304f8 GC	227	{
5ab5afd8 TP	228	if (coherency_wa_enabled) {
	229	mvebu_hwcc_armada375_sync_io_barrier_wa();
	230	return;
	231	}
	232
e60304f8 GC	233	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	234	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
	235	}
	236
	237	static dma_addr_t mvebu_hwcc_dma_map_page(struct device dev, struct page page,
	238	unsigned long offset, size_t size,
	239	enum dma_data_direction dir,
	240	struct dma_attrs *attrs)
	241	{
	242	if (dir != DMA_TO_DEVICE)
	243	mvebu_hwcc_sync_io_barrier();
	244	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
	245	}
	246
	247
	248	static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
	249	size_t size, enum dma_data_direction dir,
	250	struct dma_attrs *attrs)
	251	{
	252	if (dir != DMA_TO_DEVICE)
	253	mvebu_hwcc_sync_io_barrier();
	254	}
	255
	256	static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
	257	size_t size, enum dma_data_direction dir)
	258	{
	259	if (dir != DMA_TO_DEVICE)
	260	mvebu_hwcc_sync_io_barrier();
	261	}
	262
	263	static struct dma_map_ops mvebu_hwcc_dma_ops = {
	264	.alloc = arm_dma_alloc,
	265	.free = arm_dma_free,
	266	.mmap = arm_dma_mmap,
	267	.map_page = mvebu_hwcc_dma_map_page,
	268	.unmap_page = mvebu_hwcc_dma_unmap_page,
	269	.get_sgtable = arm_dma_get_sgtable,
	270	.map_sg = arm_dma_map_sg,
	271	.unmap_sg = arm_dma_unmap_sg,
	272	.sync_single_for_cpu = mvebu_hwcc_dma_sync,
	273	.sync_single_for_device = mvebu_hwcc_dma_sync,
	274	.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
	275	.sync_sg_for_device = arm_dma_sync_sg_for_device,
	276	.set_dma_mask = arm_dma_set_mask,
	277	};
	278
b0063aad TP	279	static int mvebu_hwcc_notifier(struct notifier_block *nb,
b0063aad TP	280	unsigned long event, void *__dev)
e60304f8 GC	281	{
	282	struct device *dev = __dev;
	283
	284	if (event != BUS_NOTIFY_ADD_DEVICE)
	285	return NOTIFY_DONE;
	286	set_dma_ops(dev, &mvebu_hwcc_dma_ops);
	287
	288	return NOTIFY_OK;
	289	}
	290
b0063aad TP	291	static struct notifier_block mvebu_hwcc_nb = {
b0063aad TP	292	.notifier_call = mvebu_hwcc_notifier,
e60304f8 GC	293	};
e60304f8 GC	294
924d38f4 TP	295	static void __init armada_370_coherency_init(struct device_node *np)
	296	{
	297	struct resource res;
	298
	299	of_address_to_resource(np, 0, &res);
	300	coherency_phys_base = res.start;
	301	/*
	302	* Ensure secondary CPUs will see the updated value,
	303	* which they read before they join the coherency
	304	* fabric, and therefore before they are coherent with
	305	* the boot CPU cache.
	306	*/
	307	sync_cache_w(&coherency_phys_base);
	308	coherency_base = of_iomap(np, 0);
	309	coherency_cpu_base = of_iomap(np, 1);
952f4ca7	310	set_cpu_coherent();
924d38f4 TP	311	}
924d38f4 TP	312
497a9230 TP	313	/*
	314	* This ioremap hook is used on Armada 375/38x to ensure that PCIe
	315	* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
	316	* is needed as a workaround for a deadlock issue between the PCIe
	317	* interface and the cache controller.
	318	*/
	319	static void __iomem *
	320	armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
	321	unsigned int mtype, void *caller)
	322	{
	323	struct resource pcie_mem;
	324
	325	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
	326
	327	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
	328	mtype = MT_UNCACHED;
	329
	330	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
	331	}
	332
d0de9323	333	static void __init armada_375_380_coherency_init(struct device_node *np)
77fa4b9a	334	{
497a9230 TP	335	struct device_node *cache_dn;
497a9230 TP	336
77fa4b9a	337	coherency_cpu_base = of_iomap(np, 0);
497a9230 TP	338	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
	339
	340	/*
	341	* Add the PL310 property "arm,io-coherent". This makes sure the
	342	* outer sync operation is not used, which allows to
	343	* workaround the system erratum that causes deadlocks when
	344	* doing PCIe in an SMP situation on Armada 375 and Armada
	345	* 38x.
	346	*/
	347	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
	348	struct property *p;
	349
	350	p = kzalloc(sizeof(*p), GFP_KERNEL);
	351	p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
	352	of_add_property(cache_dn, p);
	353	}
77fa4b9a TP	354	}
77fa4b9a TP	355
501f928e	356	static int coherency_type(void)
009f1315 GC	357	{
009f1315 GC	358	struct device_node *np;
5fbba080	359	const struct of_device_id *match;
009f1315	360
5fbba080	361	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
009f1315	362	if (np) {
5fbba080	363	int type = (int) match->data;
924d38f4	364
501f928e	365	/* Armada 370/XP coherency works in both UP and SMP */
924d38f4	366	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
501f928e	367	return type;
924d38f4	368
77fa4b9a TP	369	/* Armada 375 coherency works only on SMP */
	370	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())
	371	return type;
	372
d0de9323 TP	373	/* Armada 380 coherency works only on SMP */
	374	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
	375	return type;
009f1315 GC	376	}
009f1315 GC	377
501f928e	378	return COHERENCY_FABRIC_TYPE_NONE;
009f1315	379	}
865e0527	380
501f928e	381	int coherency_available(void)
865e0527	382	{
501f928e TP	383	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
	384	}
	385
	386	int __init coherency_init(void)
	387	{
	388	int type = coherency_type();
abe511ac JZ	389	struct device_node *np;
	390
	391	np = of_find_matching_node(NULL, of_coherency_table);
501f928e TP	392
	393	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
	394	armada_370_coherency_init(np);
d0de9323 TP	395	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 \|\|
	396	type == COHERENCY_FABRIC_TYPE_ARMADA_380)
	397	armada_375_380_coherency_init(np);
501f928e TP	398
	399	return 0;
	400	}
	401
	402	static int __init coherency_late_init(void)
	403	{
5ab5afd8 TP	404	int type = coherency_type();
	405
	406	if (type == COHERENCY_FABRIC_TYPE_NONE)
	407	return 0;
	408
39438567 TP	409	if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) {
	410	u32 dev, rev;
	411
	412	if (mvebu_get_soc_id(&dev, &rev) == 0 &&
	413	rev == ARMADA_375_Z1_REV)
	414	armada_375_coherency_init_wa();
	415	}
5ab5afd8 TP	416
5ab5afd8 TP	417	bus_register_notifier(&platform_bus_type,
b0063aad	418	&mvebu_hwcc_nb);
5ab5afd8	419
865e0527 TP	420	return 0;
	421	}
	422
	423	postcore_initcall(coherency_late_init);
b0063aad TP	424
	425	static int __init coherency_pci_init(void)
	426	{
	427	if (coherency_available())
	428	bus_register_notifier(&pci_bus_type,
	429	&mvebu_hwcc_nb);
	430	return 0;
	431	}
	432
	433	arch_initcall(coherency_pci_init);