Commit | Line | Data |
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2cb536d1 SH |
1 | /* |
2 | * Copyright (C) 2009 by Sascha Hauer, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
16 | * MA 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | ||
25 | #include <asm/clkdev.h> | |
26 | ||
27 | #include <mach/clock.h> | |
28 | #include <mach/hardware.h> | |
29 | #include <mach/common.h> | |
30 | ||
31 | #define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) | |
32 | ||
33 | #define CCM_CCMR 0x00 | |
34 | #define CCM_PDR0 0x04 | |
35 | #define CCM_PDR1 0x08 | |
36 | #define CCM_PDR2 0x0C | |
37 | #define CCM_PDR3 0x10 | |
38 | #define CCM_PDR4 0x14 | |
39 | #define CCM_RCSR 0x18 | |
40 | #define CCM_MPCTL 0x1C | |
41 | #define CCM_PPCTL 0x20 | |
42 | #define CCM_ACMR 0x24 | |
43 | #define CCM_COSR 0x28 | |
44 | #define CCM_CGR0 0x2C | |
45 | #define CCM_CGR1 0x30 | |
46 | #define CCM_CGR2 0x34 | |
47 | #define CCM_CGR3 0x38 | |
48 | ||
49 | #ifdef HAVE_SET_RATE_SUPPORT | |
50 | static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) | |
51 | { | |
52 | u32 min_pre, temp_pre, old_err, err; | |
53 | ||
54 | min_pre = (div - 1) / maxpost + 1; | |
55 | old_err = 8; | |
56 | ||
57 | for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { | |
58 | if (div > (temp_pre * maxpost)) | |
59 | break; | |
60 | ||
61 | if (div < (temp_pre * temp_pre)) | |
62 | continue; | |
63 | ||
64 | err = div % temp_pre; | |
65 | ||
66 | if (err == 0) { | |
67 | *pre = temp_pre; | |
68 | break; | |
69 | } | |
70 | ||
71 | err = temp_pre - err; | |
72 | ||
73 | if (err < old_err) { | |
74 | old_err = err; | |
75 | *pre = temp_pre; | |
76 | } | |
77 | } | |
78 | ||
79 | *post = (div + *pre - 1) / *pre; | |
80 | } | |
81 | ||
82 | /* get the best values for a 3-bit divider combined with a 6-bit divider */ | |
83 | static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post) | |
84 | { | |
85 | if (div >= 512) { | |
86 | *pre = 8; | |
87 | *post = 64; | |
88 | } else if (div >= 64) { | |
89 | calc_dividers(div, pre, post, 64); | |
90 | } else if (div <= 8) { | |
91 | *pre = div; | |
92 | *post = 1; | |
93 | } else { | |
94 | *pre = 1; | |
95 | *post = div; | |
96 | } | |
97 | } | |
98 | ||
99 | /* get the best values for two cascaded 3-bit dividers */ | |
100 | static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post) | |
101 | { | |
102 | if (div >= 64) { | |
103 | *pre = *post = 8; | |
104 | } else if (div > 8) { | |
105 | calc_dividers(div, pre, post, 8); | |
106 | } else { | |
107 | *pre = 1; | |
108 | *post = div; | |
109 | } | |
110 | } | |
111 | #endif | |
112 | ||
113 | static unsigned long get_rate_mpll(void) | |
114 | { | |
115 | ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL); | |
116 | ||
117 | return mxc_decode_pll(mpctl, 24000000); | |
118 | } | |
119 | ||
120 | static unsigned long get_rate_ppll(void) | |
121 | { | |
122 | ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL); | |
123 | ||
124 | return mxc_decode_pll(ppctl, 24000000); | |
125 | } | |
126 | ||
127 | struct arm_ahb_div { | |
128 | unsigned char arm, ahb, sel; | |
129 | }; | |
130 | ||
131 | static struct arm_ahb_div clk_consumer[] = { | |
132 | { .arm = 1, .ahb = 4, .sel = 0}, | |
133 | { .arm = 1, .ahb = 3, .sel = 1}, | |
134 | { .arm = 2, .ahb = 2, .sel = 0}, | |
135 | { .arm = 0, .ahb = 0, .sel = 0}, | |
136 | { .arm = 0, .ahb = 0, .sel = 0}, | |
137 | { .arm = 0, .ahb = 0, .sel = 0}, | |
138 | { .arm = 4, .ahb = 1, .sel = 0}, | |
139 | { .arm = 1, .ahb = 5, .sel = 0}, | |
140 | { .arm = 1, .ahb = 8, .sel = 0}, | |
141 | { .arm = 1, .ahb = 6, .sel = 1}, | |
142 | { .arm = 2, .ahb = 4, .sel = 0}, | |
143 | { .arm = 0, .ahb = 0, .sel = 0}, | |
144 | { .arm = 0, .ahb = 0, .sel = 0}, | |
145 | { .arm = 0, .ahb = 0, .sel = 0}, | |
146 | { .arm = 4, .ahb = 2, .sel = 0}, | |
147 | { .arm = 0, .ahb = 0, .sel = 0}, | |
148 | }; | |
149 | ||
150 | static struct arm_ahb_div clk_automotive[] = { | |
151 | { .arm = 1, .ahb = 3, .sel = 0}, | |
152 | { .arm = 1, .ahb = 2, .sel = 1}, | |
153 | { .arm = 2, .ahb = 1, .sel = 1}, | |
154 | { .arm = 0, .ahb = 0, .sel = 0}, | |
155 | { .arm = 1, .ahb = 6, .sel = 0}, | |
156 | { .arm = 1, .ahb = 4, .sel = 1}, | |
157 | { .arm = 2, .ahb = 2, .sel = 1}, | |
158 | { .arm = 0, .ahb = 0, .sel = 0}, | |
159 | }; | |
160 | ||
161 | static unsigned long get_rate_arm(void) | |
162 | { | |
163 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | |
164 | struct arm_ahb_div *aad; | |
165 | unsigned long fref = get_rate_mpll(); | |
166 | ||
167 | if (pdr0 & 1) { | |
168 | /* consumer path */ | |
169 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | |
170 | if (aad->sel) | |
171 | fref = fref * 2 / 3; | |
172 | } else { | |
173 | /* auto path */ | |
174 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | |
175 | if (aad->sel) | |
176 | fref = fref * 3 / 4; | |
177 | } | |
178 | return fref / aad->arm; | |
179 | } | |
180 | ||
181 | static unsigned long get_rate_ahb(struct clk *clk) | |
182 | { | |
183 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | |
184 | struct arm_ahb_div *aad; | |
185 | unsigned long fref = get_rate_mpll(); | |
186 | ||
187 | if (pdr0 & 1) | |
188 | /* consumer path */ | |
189 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | |
190 | else | |
191 | /* auto path */ | |
192 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | |
193 | ||
194 | return fref / aad->ahb; | |
195 | } | |
196 | ||
197 | static unsigned long get_rate_ipg(struct clk *clk) | |
198 | { | |
199 | return get_rate_ahb(NULL) >> 1; | |
200 | } | |
201 | ||
202 | static unsigned long get_3_3_div(unsigned long in) | |
203 | { | |
204 | return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); | |
205 | } | |
206 | ||
207 | static unsigned long get_rate_uart(struct clk *clk) | |
208 | { | |
209 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | |
210 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | |
211 | unsigned long div = get_3_3_div(pdr4 >> 10); | |
212 | ||
213 | if (pdr3 & (1 << 14)) | |
214 | return get_rate_arm() / div; | |
215 | else | |
216 | return get_rate_ppll() / div; | |
217 | } | |
218 | ||
219 | static unsigned long get_rate_sdhc(struct clk *clk) | |
220 | { | |
221 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | |
222 | unsigned long div, rate; | |
223 | ||
224 | if (pdr3 & (1 << 6)) | |
225 | rate = get_rate_arm(); | |
226 | else | |
227 | rate = get_rate_ppll(); | |
228 | ||
229 | switch (clk->id) { | |
230 | default: | |
231 | case 0: | |
232 | div = pdr3 & 0x3f; | |
233 | break; | |
234 | case 1: | |
235 | div = (pdr3 >> 8) & 0x3f; | |
236 | break; | |
237 | case 2: | |
238 | div = (pdr3 >> 16) & 0x3f; | |
239 | break; | |
240 | } | |
241 | ||
242 | return rate / get_3_3_div(div); | |
243 | } | |
244 | ||
245 | static unsigned long get_rate_mshc(struct clk *clk) | |
246 | { | |
247 | unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1); | |
248 | unsigned long div1, div2, rate; | |
249 | ||
250 | if (pdr1 & (1 << 7)) | |
251 | rate = get_rate_arm(); | |
252 | else | |
253 | rate = get_rate_ppll(); | |
254 | ||
255 | div1 = (pdr1 >> 29) & 0x7; | |
256 | div2 = (pdr1 >> 22) & 0x3f; | |
257 | ||
258 | return rate / ((div1 + 1) * (div2 + 1)); | |
259 | } | |
260 | ||
261 | static unsigned long get_rate_ssi(struct clk *clk) | |
262 | { | |
263 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | |
264 | unsigned long div1, div2, rate; | |
265 | ||
266 | if (pdr2 & (1 << 6)) | |
267 | rate = get_rate_arm(); | |
268 | else | |
269 | rate = get_rate_ppll(); | |
270 | ||
271 | switch (clk->id) { | |
272 | default: | |
273 | case 0: | |
274 | div1 = pdr2 & 0x3f; | |
275 | div2 = (pdr2 >> 24) & 0x7; | |
276 | break; | |
277 | case 1: | |
278 | div1 = (pdr2 >> 8) & 0x3f; | |
279 | div2 = (pdr2 >> 27) & 0x7; | |
280 | break; | |
281 | } | |
282 | ||
283 | return rate / ((div1 + 1) * (div2 + 1)); | |
284 | } | |
285 | ||
286 | static unsigned long get_rate_csi(struct clk *clk) | |
287 | { | |
288 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | |
289 | unsigned long rate; | |
290 | ||
291 | if (pdr2 & (1 << 7)) | |
292 | rate = get_rate_arm(); | |
293 | else | |
294 | rate = get_rate_ppll(); | |
295 | ||
296 | return rate / get_3_3_div((pdr2 >> 16) & 0x3f); | |
297 | } | |
298 | ||
299 | static unsigned long get_rate_ipg_per(struct clk *clk) | |
300 | { | |
301 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | |
302 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | |
303 | unsigned long div1, div2; | |
304 | ||
305 | if (pdr0 & (1 << 26)) { | |
306 | div1 = (pdr4 >> 19) & 0x7; | |
307 | div2 = (pdr4 >> 16) & 0x7; | |
308 | return get_rate_arm() / ((div1 + 1) * (div2 + 1)); | |
309 | } else { | |
310 | div1 = (pdr0 >> 12) & 0x7; | |
311 | return get_rate_ahb(NULL) / div1; | |
312 | } | |
313 | } | |
314 | ||
315 | static int clk_cgr_enable(struct clk *clk) | |
316 | { | |
317 | u32 reg; | |
318 | ||
319 | reg = __raw_readl(clk->enable_reg); | |
320 | reg |= 3 << clk->enable_shift; | |
321 | __raw_writel(reg, clk->enable_reg); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static void clk_cgr_disable(struct clk *clk) | |
327 | { | |
328 | u32 reg; | |
329 | ||
330 | reg = __raw_readl(clk->enable_reg); | |
331 | reg &= ~(3 << clk->enable_shift); | |
332 | __raw_writel(reg, clk->enable_reg); | |
333 | } | |
334 | ||
335 | #define DEFINE_CLOCK(name, i, er, es, gr, sr) \ | |
336 | static struct clk name = { \ | |
337 | .id = i, \ | |
338 | .enable_reg = CCM_BASE + er, \ | |
339 | .enable_shift = es, \ | |
340 | .get_rate = gr, \ | |
341 | .set_rate = sr, \ | |
342 | .enable = clk_cgr_enable, \ | |
343 | .disable = clk_cgr_disable, \ | |
344 | } | |
345 | ||
346 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); | |
347 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); | |
348 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); | |
349 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); | |
350 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); | |
351 | DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); | |
352 | DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); | |
353 | DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); | |
354 | DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); | |
355 | DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); | |
356 | DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); | |
357 | DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); | |
358 | DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); | |
359 | DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); | |
360 | DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); | |
361 | DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL); | |
362 | ||
363 | DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL); | |
364 | DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL); | |
365 | DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL); | |
366 | DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL); | |
367 | DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL); | |
368 | DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); | |
369 | DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); | |
370 | DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); | |
371 | DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); | |
372 | DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); | |
373 | DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); | |
374 | DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); | |
375 | DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); | |
376 | DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL); | |
377 | DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL); | |
378 | DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL); | |
379 | ||
380 | DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL); | |
381 | DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL); | |
382 | DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL); | |
383 | DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL); | |
384 | DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL); | |
385 | DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL); | |
386 | DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL); | |
387 | DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL); | |
388 | DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL); | |
389 | DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL); | |
390 | DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); | |
391 | DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL); | |
392 | DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); | |
393 | DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); | |
394 | DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); | |
395 | ||
396 | DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); | |
397 | DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); | |
398 | DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | |
399 | ||
400 | #define _REGISTER_CLOCK(d, n, c) \ | |
401 | { \ | |
402 | .dev_id = d, \ | |
403 | .con_id = n, \ | |
404 | .clk = &c, \ | |
405 | }, | |
406 | ||
407 | static struct clk_lookup lookups[] __initdata = { | |
408 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | |
409 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | |
410 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | |
411 | _REGISTER_CLOCK(NULL, "can", can1_clk) | |
412 | _REGISTER_CLOCK(NULL, "can", can2_clk) | |
413 | _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) | |
414 | _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) | |
415 | _REGISTER_CLOCK(NULL, "ect", ect_clk) | |
416 | _REGISTER_CLOCK(NULL, "edio", edio_clk) | |
417 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | |
418 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | |
419 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | |
420 | _REGISTER_CLOCK(NULL, "esai", esai_clk) | |
421 | _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) | |
422 | _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) | |
423 | _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) | |
424 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | |
425 | _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) | |
426 | _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) | |
427 | _REGISTER_CLOCK(NULL, "gpio", gpio3_clk) | |
428 | _REGISTER_CLOCK("gpt.0", NULL, gpt_clk) | |
429 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | |
430 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | |
431 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) | |
432 | _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) | |
433 | _REGISTER_CLOCK(NULL, "ipu", ipu_clk) | |
434 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) | |
435 | _REGISTER_CLOCK(NULL, "mlb", mlb_clk) | |
436 | _REGISTER_CLOCK(NULL, "mshc", mshc_clk) | |
437 | _REGISTER_CLOCK("mxc_w1", NULL, owire_clk) | |
438 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | |
439 | _REGISTER_CLOCK(NULL, "rngc", rngc_clk) | |
440 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | |
441 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | |
442 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | |
443 | _REGISTER_CLOCK(NULL, "sdma", sdma_clk) | |
444 | _REGISTER_CLOCK(NULL, "spba", spba_clk) | |
445 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | |
446 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | |
447 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | |
448 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | |
449 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | |
450 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | |
451 | _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk) | |
452 | _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk) | |
453 | _REGISTER_CLOCK(NULL, "max", max_clk) | |
454 | _REGISTER_CLOCK(NULL, "admux", admux_clk) | |
455 | _REGISTER_CLOCK(NULL, "csi", csi_clk) | |
456 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | |
457 | _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) | |
458 | }; | |
459 | ||
460 | int __init mx35_clocks_init() | |
461 | { | |
462 | int i; | |
463 | unsigned int ll = 0; | |
464 | ||
465 | mxc_set_cpu_type(MXC_CPU_MX35); | |
466 | ||
467 | #ifdef CONFIG_DEBUG_LL_CONSOLE | |
468 | ll = (3 << 16); | |
469 | #endif | |
470 | ||
471 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | |
472 | clkdev_add(&lookups[i]); | |
473 | ||
474 | /* Turn off all clocks except the ones we need to survive, namely: | |
475 | * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart | |
476 | */ | |
477 | __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); | |
478 | __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), | |
479 | CCM_BASE + CCM_CGR1); | |
480 | __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); | |
481 | __raw_writel(0, CCM_BASE + CCM_CGR3); | |
482 | ||
483 | mxc_timer_init(&gpt_clk); | |
484 | ||
485 | return 0; | |
486 | } | |
487 |