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mach-mx31_3ds: Add support for framebuffer and LCD
[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
1553a1ec
FE		 16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
135cad36 20#include <linux/gpio.h>
2b0c3677 21#include <linux/platform_device.h>
ae7a3f13
AP		 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
e42010e0 24#include <linux/spi/l4f00242t03.h>
ae7a3f13 25#include <linux/regulator/machine.h>
1c50e672
FE		 26#include <linux/usb/otg.h>
27#include <linux/usb/ulpi.h>
1553a1ec
FE		 28
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/memory.h>
34#include <asm/mach/map.h>
35#include <mach/common.h>
1553a1ec 36#include <mach/iomux-mx3.h>
c5d38f08 37#include <mach/3ds_debugboard.h>
1c50e672 38#include <mach/ulpi.h>
0ce88b34 39#include <mach/mmc.h>
e42010e0
AP		 40#include <mach/ipu.h>
41#include <mach/mx3fb.h>
a2ceeef5
UKK		 42
43#include "devices-imx31.h"
1553a1ec
FE		 44#include "devices.h"
45
b396dc45
UKK		 46/* CPLD IRQ line for external uart, external ethernet etc */
47#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
48
11a332ad 49static int mx31_3ds_pins[] = {
153fa1d8 50 /* UART1 */
63d97667
VL		 51 MX31_PIN_CTS1__CTS1,
52 MX31_PIN_RTS1__RTS1,
53 MX31_PIN_TXD1__TXD1,
135cad36
ML		 54 MX31_PIN_RXD1__RXD1,
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0
AP		 56 /*SPI0*/
57 MX31_PIN_CSPI1_SCLK__SCLK,
58 MX31_PIN_CSPI1_MOSI__MOSI,
59 MX31_PIN_CSPI1_MISO__MISO,
60 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
61 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
a1ac4424
AP		 62 /* SPI 1 */
63 MX31_PIN_CSPI2_SCLK__SCLK,
64 MX31_PIN_CSPI2_MOSI__MOSI,
65 MX31_PIN_CSPI2_MISO__MISO,
66 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
67 MX31_PIN_CSPI2_SS0__SS0,
68 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 69 /* MC13783 IRQ */
70 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 71 /* USB OTG reset */
72 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
73 /* USB OTG */
74 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
75 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
76 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
77 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
78 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
79 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
80 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
81 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
82 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
83 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
84 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
85 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 86 /*Keyboard*/
87 MX31_PIN_KEY_ROW0_KEY_ROW0,
88 MX31_PIN_KEY_ROW1_KEY_ROW1,
89 MX31_PIN_KEY_ROW2_KEY_ROW2,
90 MX31_PIN_KEY_COL0_KEY_COL0,
91 MX31_PIN_KEY_COL1_KEY_COL1,
92 MX31_PIN_KEY_COL2_KEY_COL2,
93 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 94 /* USB Host 2 */
95 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
96 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
97 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
98 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
99 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
100 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
101 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
102 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
103 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
104 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
105 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
106 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
107 /* USB Host2 reset */
108 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 109 /* I2C1 */
110 MX31_PIN_I2C_CLK__I2C1_SCL,
111 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 112 /* SDHC1 */
113 MX31_PIN_SD1_DATA3__SD1_DATA3,
114 MX31_PIN_SD1_DATA2__SD1_DATA2,
115 MX31_PIN_SD1_DATA1__SD1_DATA1,
116 MX31_PIN_SD1_DATA0__SD1_DATA0,
117 MX31_PIN_SD1_CLK__SD1_CLK,
118 MX31_PIN_SD1_CMD__SD1_CMD,
119 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
120 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 121 /* Framebuffer */
122 MX31_PIN_LD0__LD0,
123 MX31_PIN_LD1__LD1,
124 MX31_PIN_LD2__LD2,
125 MX31_PIN_LD3__LD3,
126 MX31_PIN_LD4__LD4,
127 MX31_PIN_LD5__LD5,
128 MX31_PIN_LD6__LD6,
129 MX31_PIN_LD7__LD7,
130 MX31_PIN_LD8__LD8,
131 MX31_PIN_LD9__LD9,
132 MX31_PIN_LD10__LD10,
133 MX31_PIN_LD11__LD11,
134 MX31_PIN_LD12__LD12,
135 MX31_PIN_LD13__LD13,
136 MX31_PIN_LD14__LD14,
137 MX31_PIN_LD15__LD15,
138 MX31_PIN_LD16__LD16,
139 MX31_PIN_LD17__LD17,
140 MX31_PIN_VSYNC3__VSYNC3,
141 MX31_PIN_HSYNC__HSYNC,
142 MX31_PIN_FPSHIFT__FPSHIFT,
143 MX31_PIN_CONTRAST__CONTRAST,
144};
145
146/*
147 * FB support
148 */
149static const struct fb_videomode fb_modedb[] = {
150 { /* 480x640 @ 60 Hz */
151 .name = "Epson-VGA",
152 .refresh = 60,
153 .xres = 480,
154 .yres = 640,
155 .pixclock = 41701,
156 .left_margin = 20,
157 .right_margin = 41,
158 .upper_margin = 10,
159 .lower_margin = 5,
160 .hsync_len = 20,
161 .vsync_len = 10,
162 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
163 .vmode = FB_VMODE_NONINTERLACED,
164 .flag = 0,
165 },
166};
167
168static struct ipu_platform_data mx3_ipu_data = {
169 .irq_base = MXC_IPU_IRQ_START,
170};
171
172static struct mx3fb_platform_data mx3fb_pdata = {
173 .dma_dev = &mx3_ipu.dev,
174 .name = "Epson-VGA",
175 .mode = fb_modedb,
176 .num_modes = ARRAY_SIZE(fb_modedb),
177};
178
179/* LCD */
180static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
181 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
182 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
183 .core_supply = "lcd_2v8",
184 .io_supply = "vdd_lcdio",
0ce88b34
AP		 185};
186
187/*
188 * Support for SD card slot in personality board
189 */
190#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
191#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
192
193static struct gpio mx31_3ds_sdhc1_gpios[] = {
194 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
195 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
196};
197
198static int mx31_3ds_sdhc1_init(struct device *dev,
199 irq_handler_t detect_irq,
200 void *data)
201{
202 int ret;
203
204 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
205 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
206 if (ret) {
207 pr_warning("Unable to request the SD/MMC GPIOs.\n");
208 return ret;
209 }
210
211 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
212 detect_irq, IRQF_DISABLED |
213 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
214 "sdhc1-detect", data);
215 if (ret) {
216 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
217 goto gpio_free;
218 }
219
220 return 0;
221
222gpio_free:
223 gpio_free_array(mx31_3ds_sdhc1_gpios,
224 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
225 return ret;
226}
227
228static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
229{
230 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
231 gpio_free_array(mx31_3ds_sdhc1_gpios,
232 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
233}
234
235static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
236{
237 /*
238 * While the voltage stuff is done by the driver, activate the
239 * Buffer Enable Pin only if there is a card in slot to fix the card
240 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
241 * Done here because at this stage we have for sure a debounced value
242 * of the presence of the card, showed by the value of vdd.
243 * 7 == ilog2(MMC_VDD_165_195)
244 */
245 if (vdd > 7)
246 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
247 else
248 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
249}
250
251static struct imxmmc_platform_data sdhc1_pdata = {
252 .init = mx31_3ds_sdhc1_init,
253 .exit = mx31_3ds_sdhc1_exit,
254 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 255};
256
257/*
258 * Matrix keyboard
259 */
260
261static const uint32_t mx31_3ds_keymap[] = {
262 KEY(0, 0, KEY_UP),
263 KEY(0, 1, KEY_DOWN),
264 KEY(1, 0, KEY_RIGHT),
265 KEY(1, 1, KEY_LEFT),
266 KEY(1, 2, KEY_ENTER),
267 KEY(2, 0, KEY_F6),
268 KEY(2, 1, KEY_F8),
269 KEY(2, 2, KEY_F9),
270 KEY(2, 3, KEY_F10),
271};
272
d690b4c4 273static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 274 .keymap = mx31_3ds_keymap,
275 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 276};
277
278/* Regulators */
279static struct regulator_init_data pwgtx_init = {
280 .constraints = {
281 .boot_on = 1,
282 .always_on = 1,
283 },
284};
285
0d95b75e
FE		 286static struct regulator_init_data gpo_init = {
287 .constraints = {
288 .boot_on = 1,
289 .always_on = 1,
290 }
291};
292
0ce88b34
AP		 293static struct regulator_consumer_supply vmmc2_consumers[] = {
294 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
295};
296
297static struct regulator_init_data vmmc2_init = {
298 .constraints = {
299 .min_uV = 3000000,
300 .max_uV = 3000000,
301 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
302 REGULATOR_CHANGE_STATUS,
303 },
304 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
305 .consumer_supplies = vmmc2_consumers,
306};
307
e42010e0
AP		 308static struct regulator_consumer_supply vmmc1_consumers[] = {
309 REGULATOR_SUPPLY("lcd_2v8", NULL),
310};
311
312static struct regulator_init_data vmmc1_init = {
313 .constraints = {
314 .min_uV = 2800000,
315 .max_uV = 2800000,
316 .apply_uV = 1,
317 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
318 REGULATOR_CHANGE_STATUS,
319 },
320 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
321 .consumer_supplies = vmmc1_consumers,
322};
323
324static struct regulator_consumer_supply vgen_consumers[] = {
325 REGULATOR_SUPPLY("vdd_lcdio", NULL),
326};
327
328static struct regulator_init_data vgen_init = {
329 .constraints = {
330 .min_uV = 1800000,
331 .max_uV = 1800000,
332 .apply_uV = 1,
333 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
334 REGULATOR_CHANGE_STATUS,
335 },
336 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
337 .consumer_supplies = vgen_consumers,
338};
339
5836372e 340static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 341 {
57c78e35 342 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 343 .init_data = &pwgtx_init,
344 }, {
57c78e35 345 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 346 .init_data = &pwgtx_init,
0d95b75e
FE		 347 }, {
348
c97b7393 349 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 350 .init_data = &gpo_init,
351 }, {
c97b7393 352 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 353 .init_data = &gpo_init,
0ce88b34
AP		 354 }, {
355 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
356 .init_data = &vmmc2_init,
e42010e0
AP		 357 }, {
358 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
359 .init_data = &vmmc1_init,
360 }, {
361 .id = MC13783_REG_VGEN, /* Power LCD */
362 .init_data = &vgen_init,
ae7a3f13
AP		 363 },
364};
365
366/* MC13783 */
5836372e 367static struct mc13xxx_platform_data mc13783_pdata __initdata = {
ae7a3f13
AP		 368 .regulators = mx31_3ds_regulators,
369 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
5836372e 370 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
a1ac4424
AP		 371};
372
373/* SPI */
e42010e0
AP		 374static int spi0_internal_chipselect[] = {
375 MXC_SPI_CS(2),
376};
377
378static const struct spi_imx_master spi0_pdata __initconst = {
379 .chipselect = spi0_internal_chipselect,
380 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
381};
382
a1ac4424
AP		 383static int spi1_internal_chipselect[] = {
384 MXC_SPI_CS(0),
385 MXC_SPI_CS(2),
386};
387
06606ff1 388static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 389 .chipselect = spi1_internal_chipselect,
390 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 391};
392
ae7a3f13
AP		 393static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
394 {
395 .modalias = "mc13783",
396 .max_speed_hz = 1000000,
397 .bus_num = 1,
398 .chip_select = 1, /* SS2 */
399 .platform_data = &mc13783_pdata,
400 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
401 .mode = SPI_CS_HIGH,
e42010e0
AP		 402 }, {
403 .modalias = "l4f00242t03",
404 .max_speed_hz = 5000000,
405 .bus_num = 0,
406 .chip_select = 0, /* SS2 */
407 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 408 },
409};
410
a1b67b95
AP		 411/*
412 * NAND Flash
413 */
a2ceeef5
UKK		 414static const struct mxc_nand_platform_data
415mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 416 .width = 1,
417 .hw_ecc = 1,
418#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
419 .flash_bbt = 1,
420#endif
421};
422
a2ef4562
ML		 423/*
424 * USB OTG
425 */
426
427#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
428 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
429
430#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 431#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 432
41f63475 433static int mx31_3ds_usbotg_init(void)
a2ef4562 434{
41f63475
FE		 435 int err;
436
a2ef4562
ML		 437 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
438 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
439 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
440 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
441 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
442 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
443 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
444 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
445 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
446 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
447 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
448 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
449
41f63475
FE		 450 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
451 if (err) {
452 pr_err("Failed to request the USB OTG reset gpio\n");
453 return err;
454 }
455
456 err = gpio_direction_output(USBOTG_RST_B, 0);
457 if (err) {
458 pr_err("Failed to drive the USB OTG reset gpio\n");
459 goto usbotg_free_reset;
460 }
461
a2ef4562
ML		 462 mdelay(1);
463 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 464 return 0;
465
466usbotg_free_reset:
467 gpio_free(USBOTG_RST_B);
468 return err;
a2ef4562
ML		 469}
470
4bd597b6
SH		 471static int mx31_3ds_otg_init(struct platform_device *pdev)
472{
473 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
474}
475
476static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 477{
478 int err;
479
480 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
481 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
482 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
483 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
484 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
485 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
486 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
487 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
488 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
489 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
490 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
491 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
492
493 err = gpio_request(USBH2_RST_B, "usbh2-reset");
494 if (err) {
495 pr_err("Failed to request the USB Host 2 reset gpio\n");
496 return err;
497 }
498
499 err = gpio_direction_output(USBH2_RST_B, 0);
500 if (err) {
501 pr_err("Failed to drive the USB Host 2 reset gpio\n");
502 goto usbotg_free_reset;
503 }
504
505 mdelay(1);
506 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 507
508 mdelay(10);
509
510 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 511
512usbotg_free_reset:
513 gpio_free(USBH2_RST_B);
514 return err;
515}
516
1c50e672 517static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 518 .init = mx31_3ds_otg_init,
1c50e672 519 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 520};
0d95b75e
FE		 521
522static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
523 .init = mx31_3ds_host2_init,
524 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 525};
1c50e672 526
9e1dde33 527static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 528 .operating_mode = FSL_USB2_DR_DEVICE,
529 .phy_mode = FSL_USB2_PHY_ULPI,
530};
531
1c50e672
FE		 532static int otg_mode_host;
533
534static int __init mx31_3ds_otg_mode(char *options)
535{
536 if (!strcmp(options, "host"))
537 otg_mode_host = 1;
538 else if (!strcmp(options, "device"))
539 otg_mode_host = 0;
540 else
541 pr_info("otg_mode neither \"host\" nor \"device\". "
542 "Defaulting to device\n");
543 return 0;
544}
545__setup("otg_mode=", mx31_3ds_otg_mode);
546
16cf5c41 547static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 548 .flags = IMXUART_HAVE_RTSCTS,
549};
1553a1ec 550
3d943024
FE		 551static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
552 .bitrate = 100000,
553};
554
e134fb2b 555static void __init mx31_3ds_init(void)
1553a1ec 556{
11a332ad
AP		 557 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
558 "mx31_3ds");
153fa1d8 559
16cf5c41 560 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 561 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 562
4a74bddc 563 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 564 spi_register_board_info(mx31_3ds_spi_devs,
565 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 566
d690b4c4 567 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 568
a2ef4562 569 mx31_3ds_usbotg_init();
1c50e672 570 if (otg_mode_host) {
48f6b099
SH		 571 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
572 ULPI_OTG_DRVVBUS_EXT);
573 if (otg_pdata.otg)
574 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 575 }
48f6b099
SH		 576 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
577 ULPI_OTG_DRVVBUS_EXT);
578 if (usbh2_pdata.otg)
579 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
580
1c50e672
FE		 581 if (!otg_mode_host)
582 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 583
b8be7b9a
RP		 584 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
585 printk(KERN_WARNING "Init of the debug board failed, all "
586 "devices on the debug board are unusable.\n");
bfdde3a9 587 imx31_add_imx2_wdt(NULL);
3d943024 588 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 589 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 590
591 imx31_add_spi_imx0(&spi0_pdata);
592 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
593 mxc_register_device(&mx3_fb, &mx3fb_pdata);
1553a1ec
FE		 594}
595
11a332ad 596static void __init mx31_3ds_timer_init(void)
1553a1ec 597{
30c730f8 598 mx31_clocks_init(26000000);
1553a1ec
FE		 599}
600
11a332ad
AP		 601static struct sys_timer mx31_3ds_timer = {
602 .init = mx31_3ds_timer_init,
1553a1ec
FE		 603};
604
1553a1ec
FE		 605MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
606 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 607 .boot_params = MX3x_PHYS_OFFSET + 0x100,
608 .map_io = mx31_map_io,
609 .init_early = imx31_init_early,
610 .init_irq = mx31_init_irq,
611 .timer = &mx31_3ds_timer,
e134fb2b 612 .init_machine = mx31_3ds_init,
1553a1ec 613MACHINE_END
Linux kernel - Deliverables
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