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Merge branch 'upstream/core' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen
[deliverable/linux.git] / arch / arm / mach-mx3 / mach-pcm037.c
CommitLineData
ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
ce8ffef0
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
32c1ad9a 17#include <linux/dma-mapping.h>
ce8ffef0
SH		 18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
3dad21a9 20#include <linux/mtd/plat-ram.h>
ce8ffef0 21#include <linux/memory.h>
ba54b958 22#include <linux/gpio.h>
4353318e 23#include <linux/smsc911x.h>
ba54b958 24#include <linux/interrupt.h>
79206750
SH		 25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
dddd4a49
SH		 27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
eb05bbeb 30#include <linux/fsl_devices.h>
91bf9a25 31#include <linux/can/platform/sja1000.h>
ee14373c
SH		 32#include <linux/usb/otg.h>
33#include <linux/usb/ulpi.h>
5a0e3ad6 34#include <linux/gfp.h>
ce8ffef0 35
32c1ad9a
GL		 36#include <media/soc_camera.h>
37
ce8ffef0
SH		 38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41#include <asm/mach/map.h>
a09e64fb 42#include <mach/common.h>
32c1ad9a 43#include <mach/hardware.h>
a09e64fb 44#include <mach/iomux-mx3.h>
a8df0ee8 45#include <mach/ipu.h>
32c1ad9a
GL		 46#include <mach/mmc.h>
47#include <mach/mx3_camera.h>
a8df0ee8 48#include <mach/mx3fb.h>
ee14373c
SH		 49#include <mach/mxc_ehci.h>
50#include <mach/ulpi.h>
ce8ffef0 51
a2ceeef5 52#include "devices-imx31.h"
5cf09421 53#include "devices.h"
574ec547
GL		 54#include "pcm037.h"
55
56static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
57
58static int __init pcm037_variant_setup(char *str)
59{
60 if (!strcmp("eet", str))
61 pcm037_instance = PCM037_EET;
62 else if (strcmp("pcm970", str))
63 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
64
65 return 1;
66}
67
68/* Supported values: "pcm970" (default) and "eet" */
69__setup("pcm037_variant=", pcm037_variant_setup);
70
71enum pcm037_board_variant pcm037_variant(void)
72{
73 return pcm037_instance;
74}
75
76/* UART1 with RTS/CTS handshake signals */
77static unsigned int pcm037_uart1_handshake_pins[] = {
78 MX31_PIN_CTS1__CTS1,
79 MX31_PIN_RTS1__RTS1,
80 MX31_PIN_TXD1__TXD1,
81 MX31_PIN_RXD1__RXD1,
82};
83
84/* UART1 without RTS/CTS handshake signals */
85static unsigned int pcm037_uart1_pins[] = {
86 MX31_PIN_TXD1__TXD1,
87 MX31_PIN_RXD1__RXD1,
88};
5cf09421 89
01ac7d58
SH		 90static unsigned int pcm037_pins[] = {
91 /* I2C */
92 MX31_PIN_CSPI2_MOSI__SCL,
93 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 94 MX31_PIN_CSPI2_SS2__I2C3_SDA,
95 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 96 /* SDHC1 */
97 MX31_PIN_SD1_DATA3__SD1_DATA3,
98 MX31_PIN_SD1_DATA2__SD1_DATA2,
99 MX31_PIN_SD1_DATA1__SD1_DATA1,
100 MX31_PIN_SD1_DATA0__SD1_DATA0,
101 MX31_PIN_SD1_CLK__SD1_CLK,
102 MX31_PIN_SD1_CMD__SD1_CMD,
103 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
104 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
105 /* SPI1 */
106 MX31_PIN_CSPI1_MOSI__MOSI,
107 MX31_PIN_CSPI1_MISO__MISO,
108 MX31_PIN_CSPI1_SCLK__SCLK,
109 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
110 MX31_PIN_CSPI1_SS0__SS0,
111 MX31_PIN_CSPI1_SS1__SS1,
112 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 113 /* UART2 */
114 MX31_PIN_TXD2__TXD2,
115 MX31_PIN_RXD2__RXD2,
116 MX31_PIN_CTS2__CTS2,
117 MX31_PIN_RTS2__RTS2,
118 /* UART3 */
119 MX31_PIN_CSPI3_MOSI__RXD3,
120 MX31_PIN_CSPI3_MISO__TXD3,
121 MX31_PIN_CSPI3_SCLK__RTS3,
122 MX31_PIN_CSPI3_SPI_RDY__CTS3,
123 /* LAN9217 irq pin */
124 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
125 /* Onewire */
126 MX31_PIN_BATT_LINE__OWIRE,
127 /* Framebuffer */
128 MX31_PIN_LD0__LD0,
129 MX31_PIN_LD1__LD1,
130 MX31_PIN_LD2__LD2,
131 MX31_PIN_LD3__LD3,
132 MX31_PIN_LD4__LD4,
133 MX31_PIN_LD5__LD5,
134 MX31_PIN_LD6__LD6,
135 MX31_PIN_LD7__LD7,
136 MX31_PIN_LD8__LD8,
137 MX31_PIN_LD9__LD9,
138 MX31_PIN_LD10__LD10,
139 MX31_PIN_LD11__LD11,
140 MX31_PIN_LD12__LD12,
141 MX31_PIN_LD13__LD13,
142 MX31_PIN_LD14__LD14,
143 MX31_PIN_LD15__LD15,
144 MX31_PIN_LD16__LD16,
145 MX31_PIN_LD17__LD17,
146 MX31_PIN_VSYNC3__VSYNC3,
147 MX31_PIN_HSYNC__HSYNC,
148 MX31_PIN_FPSHIFT__FPSHIFT,
149 MX31_PIN_DRDY0__DRDY0,
150 MX31_PIN_D3_REV__D3_REV,
151 MX31_PIN_CONTRAST__CONTRAST,
152 MX31_PIN_D3_SPL__D3_SPL,
153 MX31_PIN_D3_CLS__D3_CLS,
154 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 155 /* CSI */
156 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
157 MX31_PIN_CSI_D6__CSI_D6,
158 MX31_PIN_CSI_D7__CSI_D7,
159 MX31_PIN_CSI_D8__CSI_D8,
160 MX31_PIN_CSI_D9__CSI_D9,
161 MX31_PIN_CSI_D10__CSI_D10,
162 MX31_PIN_CSI_D11__CSI_D11,
163 MX31_PIN_CSI_D12__CSI_D12,
164 MX31_PIN_CSI_D13__CSI_D13,
165 MX31_PIN_CSI_D14__CSI_D14,
166 MX31_PIN_CSI_D15__CSI_D15,
167 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
168 MX31_PIN_CSI_MCLK__CSI_MCLK,
169 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
170 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 171 /* GPIO */
172 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 173 /* OTG */
eb05bbeb
GL		 174 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
175 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
176 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
177 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
178 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
179 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
180 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
181 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
182 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
183 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
184 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
185 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 186 /* USB host 2 */
187 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
196 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
197 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
198 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 199};
200
ee14373c
SH		 201static struct physmap_flash_data pcm037_flash_data = {
202 .width = 2,
203};
eb05bbeb 204
ee14373c
SH		 205static struct resource pcm037_flash_resource = {
206 .start = 0xa0000000,
207 .end = 0xa1ffffff,
208 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 209};
210
ce8ffef0
SH		 211static struct platform_device pcm037_flash = {
212 .name = "physmap-flash",
213 .id = 0,
214 .dev = {
215 .platform_data = &pcm037_flash_data,
216 },
217 .resource = &pcm037_flash_resource,
218 .num_resources = 1,
219};
220
16cf5c41 221static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233 222 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 223};
224
4353318e 225static struct resource smsc911x_resources[] = {
3f4f54b4 226 {
f568dd7f
UKK		 227 .start = MX31_CS1_BASE_ADDR + 0x300,
228 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 229 .flags = IORESOURCE_MEM,
3f4f54b4 230 }, {
ba54b958
GL		 231 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
232 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 234 },
235};
236
4353318e
SG		 237static struct smsc911x_platform_config smsc911x_info = {
238 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
239 SMSC911X_SAVE_MAC_ADDRESS,
240 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
241 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
242 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 243};
244
245static struct platform_device pcm037_eth = {
4353318e 246 .name = "smsc911x",
ba54b958 247 .id = -1,
4353318e
SG		 248 .num_resources = ARRAY_SIZE(smsc911x_resources),
249 .resource = smsc911x_resources,
ba54b958 250 .dev = {
4353318e 251 .platform_data = &smsc911x_info,
ba54b958
GL		 252 },
253};
254
3dad21a9
SH		 255static struct platdata_mtd_ram pcm038_sram_data = {
256 .bankwidth = 2,
257};
258
259static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 260 .start = MX31_CS4_BASE_ADDR,
261 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 262 .flags = IORESOURCE_MEM,
263};
264
265static struct platform_device pcm037_sram_device = {
266 .name = "mtd-ram",
267 .id = 0,
268 .dev = {
269 .platform_data = &pcm038_sram_data,
270 },
271 .num_resources = 1,
272 .resource = &pcm038_sram_resource,
273};
274
a2ceeef5
UKK		 275static const struct mxc_nand_platform_data
276pcm037_nand_board_info __initconst = {
3287abbd
SH		 277 .width = 1,
278 .hw_ecc = 1,
279};
280
4a9b8b0b 281static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750 282 .bitrate = 100000,
79206750
SH		 283};
284
4a9b8b0b 285static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a
GL		 286 .bitrate = 20000,
287};
288
79206750
SH		 289static struct at24_platform_data board_eeprom = {
290 .byte_len = 4096,
291 .page_size = 32,
292 .flags = AT24_FLAG_ADDR16,
293};
294
32c1ad9a
GL		 295static int pcm037_camera_power(struct device *dev, int on)
296{
297 /* disable or enable the camera in X7 or X8 PCM970 connector */
298 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
299 return 0;
300}
301
9d00278d 302static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 303 {
304 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 305 }, {
306 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 307 },
308};
309
9d00278d
GL		 310static struct soc_camera_link iclink_mt9v022 = {
311 .bus_id = 0, /* Must match with the camera ID */
312 .board_info = &pcm037_i2c_camera[1],
313 .i2c_adapter_id = 2,
9d00278d
GL		 314};
315
316static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 317 .bus_id = 0, /* Must match with the camera ID */
318 .power = pcm037_camera_power,
9d00278d 319 .board_info = &pcm037_i2c_camera[0],
32c1ad9a 320 .i2c_adapter_id = 2,
32c1ad9a
GL		 321};
322
79206750 323static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 324 {
79206750
SH		 325 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
326 .platform_data = &board_eeprom,
327 }, {
cf87a6e2 328 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 329 }
330};
32c1ad9a 331
9d00278d 332static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 333 .name = "soc-camera-pdrv",
334 .id = 0,
335 .dev = {
9d00278d
GL		 336 .platform_data = &iclink_mt9t031,
337 },
338};
339
340static struct platform_device pcm037_mt9v022 = {
341 .name = "soc-camera-pdrv",
342 .id = 1,
343 .dev = {
344 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 345 },
346};
79206750 347
dddd4a49
SH		 348/* Not connected by default */
349#ifdef PCM970_SDHC_RW_SWITCH
350static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 351{
dddd4a49
SH		 352 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
353}
354#endif
355
4f163eb8
SH		 356#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
357#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
358
dddd4a49
SH		 359static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
360 void *data)
361{
362 int ret;
dddd4a49 363
4f163eb8
SH		 364 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
365 if (ret)
366 return ret;
367
368 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 369
4f163eb8
SH		 370#ifdef PCM970_SDHC_RW_SWITCH
371 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
372 if (ret)
373 goto err_gpio_free;
374 gpio_direction_input(SDHC1_GPIO_WP);
375#endif
dddd4a49
SH		 376
377 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
378 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
379 "sdhc-detect", data);
4f163eb8
SH		 380 if (ret)
381 goto err_gpio_free_2;
382
383 return 0;
384
385err_gpio_free_2:
386#ifdef PCM970_SDHC_RW_SWITCH
387 gpio_free(SDHC1_GPIO_WP);
388err_gpio_free:
389#endif
390 gpio_free(SDHC1_GPIO_DET);
391
dddd4a49 392 return ret;
f2cb641f
SH		 393}
394
395static void pcm970_sdhc1_exit(struct device *dev, void *data)
396{
dddd4a49 397 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8
SH		 398 gpio_free(SDHC1_GPIO_DET);
399 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 400}
401
f2cb641f 402static struct imxmmc_platform_data sdhc_pdata = {
dddd4a49
SH		 403#ifdef PCM970_SDHC_RW_SWITCH
404 .get_ro = pcm970_sdhc1_get_ro,
405#endif
f2cb641f
SH		 406 .init = pcm970_sdhc1_init,
407 .exit = pcm970_sdhc1_exit,
408};
409
32c1ad9a
GL		 410struct mx3_camera_pdata camera_pdata = {
411 .dma_dev = &mx3_ipu.dev,
412 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
413 .mclk_10khz = 2000,
414};
415
416static int __init pcm037_camera_alloc_dma(const size_t buf_size)
417{
418 dma_addr_t dma_handle;
419 void *buf;
420 int dma;
421
422 if (buf_size < 2 * 1024 * 1024)
423 return -EINVAL;
424
425 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
426 if (!buf) {
427 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
428 return -ENOMEM;
429 }
430
431 memset(buf, 0, buf_size);
432
433 dma = dma_declare_coherent_memory(&mx3_camera.dev,
434 dma_handle, dma_handle, buf_size,
435 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
436
437 /* The way we call dma_declare_coherent_memory only a malloc can fail */
438 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
439}
440
ce8ffef0
SH		 441static struct platform_device *devices[] __initdata = {
442 &pcm037_flash,
3dad21a9 443 &pcm037_sram_device,
3170ba54 444 &imx_wdt_device0,
9d00278d
GL		 445 &pcm037_mt9t031,
446 &pcm037_mt9v022,
ce8ffef0
SH		 447};
448
a8df0ee8
GL		 449static struct ipu_platform_data mx3_ipu_data = {
450 .irq_base = MXC_IPU_IRQ_START,
451};
452
453static const struct fb_videomode fb_modedb[] = {
454 {
455 /* 240x320 @ 60 Hz Sharp */
456 .name = "Sharp-LQ035Q7DH06-QVGA",
457 .refresh = 60,
458 .xres = 240,
459 .yres = 320,
460 .pixclock = 185925,
461 .left_margin = 9,
462 .right_margin = 16,
463 .upper_margin = 7,
464 .lower_margin = 9,
465 .hsync_len = 1,
466 .vsync_len = 1,
467 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
468 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
469 .vmode = FB_VMODE_NONINTERLACED,
470 .flag = 0,
471 }, {
472 /* 240x320 @ 60 Hz */
473 .name = "TX090",
474 .refresh = 60,
475 .xres = 240,
476 .yres = 320,
477 .pixclock = 38255,
478 .left_margin = 144,
479 .right_margin = 0,
480 .upper_margin = 7,
481 .lower_margin = 40,
482 .hsync_len = 96,
483 .vsync_len = 1,
484 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
485 .vmode = FB_VMODE_NONINTERLACED,
486 .flag = 0,
574ec547
GL		 487 }, {
488 /* 240x320 @ 60 Hz */
489 .name = "CMEL-OLED",
490 .refresh = 60,
491 .xres = 240,
492 .yres = 320,
493 .pixclock = 185925,
494 .left_margin = 9,
495 .right_margin = 16,
496 .upper_margin = 7,
497 .lower_margin = 9,
498 .hsync_len = 1,
499 .vsync_len = 1,
500 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
501 .vmode = FB_VMODE_NONINTERLACED,
502 .flag = 0,
a8df0ee8
GL		 503 },
504};
505
506static struct mx3fb_platform_data mx3fb_pdata = {
507 .dma_dev = &mx3_ipu.dev,
508 .name = "Sharp-LQ035Q7DH06-QVGA",
509 .mode = fb_modedb,
510 .num_modes = ARRAY_SIZE(fb_modedb),
511};
512
91bf9a25
SH		 513static struct resource pcm970_sja1000_resources[] = {
514 {
f568dd7f
UKK		 515 .start = MX31_CS5_BASE_ADDR,
516 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 517 .flags = IORESOURCE_MEM,
518 }, {
519 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
520 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
521 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
522 },
523};
524
525struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b
WG		 526 .osc_freq = 16000000,
527 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
528 .cdr = CDR_CBP,
91bf9a25
SH		 529};
530
531static struct platform_device pcm970_sja1000 = {
532 .name = "sja1000_platform",
533 .dev = {
534 .platform_data = &pcm970_sja1000_platform_data,
535 },
536 .resource = pcm970_sja1000_resources,
537 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
538};
539
c18e8fa5 540#if defined(CONFIG_USB_ULPI)
ee14373c
SH		 541static struct mxc_usbh_platform_data otg_pdata = {
542 .portsc = MXC_EHCI_MODE_ULPI,
543 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
544};
545
546static struct mxc_usbh_platform_data usbh2_pdata = {
547 .portsc = MXC_EHCI_MODE_ULPI,
548 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
549};
c18e8fa5 550#endif
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SH		 551
552static struct fsl_usb2_platform_data otg_device_pdata = {
553 .operating_mode = FSL_USB2_DR_DEVICE,
554 .phy_mode = FSL_USB2_PHY_ULPI,
555};
556
557static int otg_mode_host;
558
559static int __init pcm037_otg_mode(char *options)
560{
561 if (!strcmp(options, "host"))
562 otg_mode_host = 1;
563 else if (!strcmp(options, "device"))
564 otg_mode_host = 0;
565 else
566 pr_info("otg_mode neither \"host\" nor \"device\". "
567 "Defaulting to device\n");
568 return 0;
569}
570__setup("otg_mode=", pcm037_otg_mode);
571
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SH		 572/*
573 * Board specific initialization.
574 */
575static void __init mxc_board_init(void)
576{
4f163eb8 577 int ret;
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SH		 578
579 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 580
01ac7d58
SH		 581 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
582 "pcm037");
583
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SH		 584#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
585 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
586
587 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
588 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
589 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
591 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
592 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
593 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
594 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
595 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
596 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
597 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
598 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
599
574ec547
GL		 600 if (pcm037_variant() == PCM037_EET)
601 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
602 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
603 else
604 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
605 ARRAY_SIZE(pcm037_uart1_handshake_pins),
606 "pcm037_uart1");
607
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SH		 608 platform_add_devices(devices, ARRAY_SIZE(devices));
609
16cf5c41
UKK		 610 imx31_add_imx_uart0(&uart_pdata);
611 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
612 imx31_add_imx_uart1(&uart_pdata);
613 imx31_add_imx_uart2(&uart_pdata);
d517cab1 614
d517cab1 615 mxc_register_device(&mxc_w1_master_device, NULL);
ba54b958 616
f8e5143b 617 /* LAN9217 IRQ pin */
4f163eb8
SH		 618 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
619 if (ret)
620 pr_warning("could not get LAN irq gpio\n");
621 else {
622 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
623 platform_device_register(&pcm037_eth);
624 }
625
3287abbd 626
32c1ad9a 627 /* I2C adapters and devices */
79206750
SH		 628 i2c_register_board_info(1, pcm037_i2c_devices,
629 ARRAY_SIZE(pcm037_i2c_devices));
630
4a9b8b0b
UKK		 631 imx31_add_imx_i2c1(&pcm037_i2c1_data);
632 imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a 633
a2ceeef5 634 imx31_add_mxc_nand(&pcm037_nand_board_info);
f2cb641f 635 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
a8df0ee8
GL		 636 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
637 mxc_register_device(&mx3_fb, &mx3fb_pdata);
32c1ad9a
GL		 638
639 /* CSI */
640 /* Camera power: default - off */
641 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
642 if (!ret)
643 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
644 else
9d00278d 645 iclink_mt9t031.power = NULL;
32c1ad9a
GL		 646
647 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
648 mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25
SH		 649
650 platform_device_register(&pcm970_sja1000);
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SH		 651
652#if defined(CONFIG_USB_ULPI)
653 if (otg_mode_host) {
654 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 655 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
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SH		 656
657 mxc_register_device(&mxc_otg_host, &otg_pdata);
658 }
659
660 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 661 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
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SH		 662
663 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
664#endif
665 if (!otg_mode_host)
666 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
667
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SH		 668}
669
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SH		 670static void __init pcm037_timer_init(void)
671{
30c730f8 672 mx31_clocks_init(26000000);
ce8ffef0
SH		 673}
674
675struct sys_timer pcm037_timer = {
676 .init = pcm037_timer_init,
677};
678
679MACHINE_START(PCM037, "Phytec Phycore pcm037")
680 /* Maintainer: Pengutronix */
34101237 681 .boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9 682 .map_io = mx31_map_io,
c5aa0ad0 683 .init_irq = mx31_init_irq,
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SH		 684 .init_machine = mxc_board_init,
685 .timer = &pcm037_timer,
686MACHINE_END
Linux kernel - Deliverables
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