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11f9562a JK |
1 | /* |
2 | * Amstrad E3 FIQ handling | |
3 | * | |
4 | * Copyright (C) 2009 Janusz Krzysztofik | |
5 | * Copyright (c) 2006 Matt Callow | |
6 | * Copyright (c) 2004 Amstrad Plc | |
7 | * Copyright (C) 2001 RidgeRun, Inc. | |
8 | * | |
9 | * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c | |
10 | * in the MontaVista 2.4 kernel (and the Amstrad changes therein) | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License version 2 as published by | |
14 | * the Free Software Foundation. | |
15 | */ | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/io.h> | |
21 | ||
e27e35ec | 22 | #include <mach/board-ams-delta.h> |
11f9562a JK |
23 | |
24 | #include <asm/fiq.h> | |
2e3ee9f4 | 25 | |
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26 | #include <mach/ams-delta-fiq.h> |
27 | ||
28 | static struct fiq_handler fh = { | |
29 | .name = "ams-delta-fiq" | |
30 | }; | |
31 | ||
32 | /* | |
33 | * This buffer is shared between FIQ and IRQ contexts. | |
34 | * The FIQ and IRQ isrs can both read and write it. | |
35 | * It is structured as a header section several 32bit slots, | |
36 | * followed by the circular buffer where the FIQ isr stores | |
37 | * keystrokes received from the qwerty keyboard. | |
38 | * See ams-delta-fiq.h for details of offsets. | |
39 | */ | |
40 | unsigned int fiq_buffer[1024]; | |
41 | EXPORT_SYMBOL(fiq_buffer); | |
42 | ||
43 | static unsigned int irq_counter[16]; | |
44 | ||
45 | static irqreturn_t deferred_fiq(int irq, void *dev_id) | |
46 | { | |
11f9562a | 47 | int gpio, irq_num, fiq_count; |
8435cf75 | 48 | struct irq_chip *irq_chip; |
11f9562a | 49 | |
b524ca74 | 50 | irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK)); |
11f9562a JK |
51 | |
52 | /* | |
53 | * For each handled GPIO interrupt, keep calling its interrupt handler | |
54 | * until the IRQ counter catches the FIQ incremented interrupt counter. | |
55 | */ | |
56 | for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; | |
57 | gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { | |
58 | irq_num = gpio_to_irq(gpio); | |
59 | fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; | |
60 | ||
61 | while (irq_counter[gpio] < fiq_count) { | |
62 | if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { | |
a51eef7e LB |
63 | struct irq_data *d = irq_get_irq_data(irq_num); |
64 | ||
11f9562a JK |
65 | /* |
66 | * It looks like handle_edge_irq() that | |
67 | * OMAP GPIO edge interrupts default to, | |
68 | * expects interrupt already unmasked. | |
69 | */ | |
a51eef7e LB |
70 | if (irq_chip && irq_chip->irq_unmask) |
71 | irq_chip->irq_unmask(d); | |
11f9562a JK |
72 | } |
73 | generic_handle_irq(irq_num); | |
74 | ||
75 | irq_counter[gpio]++; | |
76 | } | |
77 | } | |
78 | return IRQ_HANDLED; | |
79 | } | |
80 | ||
81 | void __init ams_delta_init_fiq(void) | |
82 | { | |
83 | void *fiqhandler_start; | |
84 | unsigned int fiqhandler_length; | |
85 | struct pt_regs FIQ_regs; | |
86 | unsigned long val, offset; | |
87 | int i, retval; | |
88 | ||
89 | fiqhandler_start = &qwerty_fiqin_start; | |
90 | fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; | |
91 | pr_info("Installing fiq handler from %p, length 0x%x\n", | |
92 | fiqhandler_start, fiqhandler_length); | |
93 | ||
94 | retval = claim_fiq(&fh); | |
95 | if (retval) { | |
96 | pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", | |
97 | retval); | |
98 | return; | |
99 | } | |
100 | ||
101 | retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, | |
a7022d60 | 102 | IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL); |
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103 | if (retval < 0) { |
104 | pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); | |
105 | release_fiq(&fh); | |
106 | return; | |
107 | } | |
108 | /* | |
109 | * Since no set_type() method is provided by OMAP irq chip, | |
110 | * switch to edge triggered interrupt type manually. | |
111 | */ | |
112 | offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; | |
113 | val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); | |
114 | omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); | |
115 | ||
116 | set_fiq_handler(fiqhandler_start, fiqhandler_length); | |
117 | ||
118 | /* | |
119 | * Initialise the buffer which is shared | |
120 | * between FIQ mode and IRQ mode | |
121 | */ | |
122 | fiq_buffer[FIQ_GPIO_INT_MASK] = 0; | |
123 | fiq_buffer[FIQ_MASK] = 0; | |
124 | fiq_buffer[FIQ_STATE] = 0; | |
125 | fiq_buffer[FIQ_KEY] = 0; | |
126 | fiq_buffer[FIQ_KEYS_CNT] = 0; | |
127 | fiq_buffer[FIQ_KEYS_HICNT] = 0; | |
128 | fiq_buffer[FIQ_TAIL_OFFSET] = 0; | |
129 | fiq_buffer[FIQ_HEAD_OFFSET] = 0; | |
130 | fiq_buffer[FIQ_BUF_LEN] = 256; | |
131 | fiq_buffer[FIQ_MISSED_KEYS] = 0; | |
132 | fiq_buffer[FIQ_BUFFER_START] = | |
133 | (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF]; | |
134 | ||
135 | for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++) | |
136 | fiq_buffer[i] = 0; | |
137 | ||
138 | /* | |
139 | * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr | |
140 | * will run in an unpredictable context. The fiq_buffer is the FIQ isr's | |
141 | * only means of communication with the IRQ level and other kernel | |
142 | * context code. | |
143 | */ | |
144 | FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer; | |
145 | set_fiq_regs(&FIQ_regs); | |
146 | ||
147 | pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer); | |
148 | ||
149 | /* | |
150 | * Redirect GPIO interrupts to FIQ | |
151 | */ | |
152 | offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; | |
153 | val = omap_readl(OMAP_IH1_BASE + offset) | 1; | |
154 | omap_writel(val, OMAP_IH1_BASE + offset); | |
155 | } |