[deliverable/linux.git] / arch / arm / mach-omap1 / board-fsample.c

/*
 * linux/arch/arm/mach-omap1/board-fsample.c
 *
 * Modified from board-perseus2.c
 *
 * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
 * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>

#include <plat/tc.h>
#include <mach/gpio.h>
#include <plat/mux.h>
#include <plat/fpga.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/board.h>

/* fsample is pretty close to p2-sample */

#define fsample_cpld_read(reg) __raw_readb(reg)
#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)

#define FSAMPLE_CPLD_BASE    0xE8100000
#define FSAMPLE_CPLD_SIZE    SZ_4K
#define FSAMPLE_CPLD_START   0x05080000

#define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
#define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
#define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
#define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)

#define FSAMPLE_CPLD_BIT_BT_RESET         0
#define FSAMPLE_CPLD_BIT_LCD_RESET        1
#define FSAMPLE_CPLD_BIT_CAM_PWDN         2
#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
#define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
#define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
#define FSAMPLE_CPLD_BIT_BACKLIGHT        6
#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
#define FSAMPLE_CPLD_BIT_OTG_RESET        9

#define fsample_cpld_set(bit) \
    fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)

#define fsample_cpld_clear(bit) \
    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)

static int fsample_keymap[] = {
	KEY(0,0,KEY_UP),
	KEY(0,1,KEY_RIGHT),
	KEY(0,2,KEY_LEFT),
	KEY(0,3,KEY_DOWN),
	KEY(0,4,KEY_ENTER),
	KEY(1,0,KEY_F10),
	KEY(1,1,KEY_SEND),
	KEY(1,2,KEY_END),
	KEY(1,3,KEY_VOLUMEDOWN),
	KEY(1,4,KEY_VOLUMEUP),
	KEY(1,5,KEY_RECORD),
	KEY(2,0,KEY_F9),
	KEY(2,1,KEY_3),
	KEY(2,2,KEY_6),
	KEY(2,3,KEY_9),
	KEY(2,4,KEY_KPDOT),
	KEY(3,0,KEY_BACK),
	KEY(3,1,KEY_2),
	KEY(3,2,KEY_5),
	KEY(3,3,KEY_8),
	KEY(3,4,KEY_0),
	KEY(3,5,KEY_KPSLASH),
	KEY(4,0,KEY_HOME),
	KEY(4,1,KEY_1),
	KEY(4,2,KEY_4),
	KEY(4,3,KEY_7),
	KEY(4,4,KEY_KPASTERISK),
	KEY(4,5,KEY_POWER),
	0
};

static struct smc91x_platdata smc91x_info = {
	.flags	= SMC91X_USE_16BIT | SMC91X_NOWAIT,
	.leda	= RPC_LED_100_10,
	.ledb	= RPC_LED_TX_RX,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= H2P2_DBG_FPGA_ETHR_START,	/* Physical */
		.end	= H2P2_DBG_FPGA_ETHR_START + 0xf,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= INT_7XX_MPU_EXT_NIRQ,
		.end	= 0,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
};

static struct mtd_partition nor_partitions[] = {
	/* bootloader (U-Boot, etc) in first sector */
	{
	      .name		= "bootloader",
	      .offset		= 0,
	      .size		= SZ_128K,
	      .mask_flags	= MTD_WRITEABLE, /* force read-only */
	},
	/* bootloader params in the next sector */
	{
	      .name		= "params",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= SZ_128K,
	      .mask_flags	= 0,
	},
	/* kernel */
	{
	      .name		= "kernel",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= SZ_2M,
	      .mask_flags	= 0
	},
	/* rest of flash is a file system */
	{
	      .name		= "rootfs",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= MTDPART_SIZ_FULL,
	      .mask_flags	= 0
	},
};

static struct flash_platform_data nor_data = {
	.map_name	= "cfi_probe",
	.width		= 2,
	.parts		= nor_partitions,
	.nr_parts	= ARRAY_SIZE(nor_partitions),
};

static struct resource nor_resource = {
	.start		= OMAP_CS0_PHYS,
	.end		= OMAP_CS0_PHYS + SZ_32M - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device nor_device = {
	.name		= "omapflash",
	.id		= 0,
	.dev		= {
		.platform_data	= &nor_data,
	},
	.num_resources	= 1,
	.resource	= &nor_resource,
};

static void nand_cmd_ctl(struct mtd_info *mtd, int cmd,	unsigned int ctrl)
{
	struct nand_chip *this = mtd->priv;
	unsigned long mask;

	if (cmd == NAND_CMD_NONE)
		return;

	mask = (ctrl & NAND_CLE) ? 0x02 : 0;
	if (ctrl & NAND_ALE)
		mask |= 0x04;
	writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}

#define FSAMPLE_NAND_RB_GPIO_PIN	62

static int nand_dev_ready(struct mtd_info *mtd)
{
	return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
}

static const char *part_probes[] = { "cmdlinepart", NULL };

static struct platform_nand_data nand_data = {
	.chip	= {
		.nr_chips		= 1,
		.chip_offset		= 0,
		.options		= NAND_SAMSUNG_LP_OPTIONS,
		.part_probe_types	= part_probes,
	},
	.ctrl	= {
		.cmd_ctrl	= nand_cmd_ctl,
		.dev_ready	= nand_dev_ready,
	},
};

static struct resource nand_resource = {
	.start		= OMAP_CS3_PHYS,
	.end		= OMAP_CS3_PHYS + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device nand_device = {
	.name		= "gen_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &nand_data,
	},
	.num_resources	= 1,
	.resource	= &nand_resource,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct resource kp_resources[] = {
	[0] = {
		.start	= INT_7XX_MPUIO_KEYPAD,
		.end	= INT_7XX_MPUIO_KEYPAD,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct omap_kp_platform_data kp_data = {
	.rows		= 8,
	.cols		= 8,
	.keymap		= fsample_keymap,
	.keymapsize	= ARRAY_SIZE(fsample_keymap),
	.delay		= 4,
};

static struct platform_device kp_device = {
	.name		= "omap-keypad",
	.id		= -1,
	.dev		= {
		.platform_data = &kp_data,
	},
	.num_resources	= ARRAY_SIZE(kp_resources),
	.resource	= kp_resources,
};

static struct platform_device lcd_device = {
	.name		= "lcd_p2",
	.id		= -1,
};

static struct platform_device *devices[] __initdata = {
	&nor_device,
	&nand_device,
	&smc91x_device,
	&kp_device,
	&lcd_device,
};

static struct omap_lcd_config fsample_lcd_config __initdata = {
	.ctrl_name	= "internal",
};

static struct omap_board_config_kernel fsample_config[] = {
	{ OMAP_TAG_LCD,		&fsample_lcd_config },
};

static void __init omap_fsample_init(void)
{
	if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
		BUG();
	gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);

	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);

	platform_add_devices(devices, ARRAY_SIZE(devices));

	omap_board_config = fsample_config;
	omap_board_config_size = ARRAY_SIZE(fsample_config);
	omap_serial_init();
	omap_register_i2c_bus(1, 100, NULL, 0);
}

static void __init fsample_init_smc91x(void)
{
	fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
	mdelay(50);
	fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
		   H2P2_DBG_FPGA_LAN_RESET);
	mdelay(50);
}

static void __init omap_fsample_init_irq(void)
{
	omap1_init_common_hw();
	omap_init_irq();
	omap_gpio_init();
	fsample_init_smc91x();
}

/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_fsample_io_desc[] __initdata = {
	{
		.virtual	= H2P2_DBG_FPGA_BASE,
		.pfn		= __phys_to_pfn(H2P2_DBG_FPGA_START),
		.length		= H2P2_DBG_FPGA_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= FSAMPLE_CPLD_BASE,
		.pfn		= __phys_to_pfn(FSAMPLE_CPLD_START),
		.length		= FSAMPLE_CPLD_SIZE,
		.type		= MT_DEVICE
	}
};

static void __init omap_fsample_map_io(void)
{
	omap1_map_common_io();
	iotable_init(omap_fsample_io_desc,
		     ARRAY_SIZE(omap_fsample_io_desc));

	/* Early, board-dependent init */

	/*
	 * Hold GSM Reset until needed
	 */
	omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);

	/*
	 * UARTs -> done automagically by 8250 driver
	 */

	/*
	 * CSx timings, GPIO Mux ... setup
	 */

	/* Flash: CS0 timings setup */
	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
	omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);

	/*
	 * Ethernet support through the debug board
	 * CS1 timings setup
	 */
	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
	omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);

	/*
	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
	 * It is used as the Ethernet controller interrupt
	 */
	omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
}

MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
/* Maintainer: Brian Swetland <swetland@google.com> */
	.phys_io	= 0xfff00000,
	.io_pg_offst	= ((0xfef00000) >> 18) & 0xfffc,
	.boot_params	= 0x10000100,
	.map_io		= omap_fsample_map_io,
	.init_irq	= omap_fsample_init_irq,
	.init_machine	= omap_fsample_init,
	.timer		= &omap_timer,
MACHINE_END
Commit	Line	Data
495f71db BS	1	/*
	2	* linux/arch/arm/mach-omap1/board-fsample.c
	3	*
	4	* Modified from board-perseus2.c
	5	*
	6	* Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
	7	* Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/delay.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/nand.h>
	20	#include <linux/mtd/partitions.h>
	21	#include <linux/input.h>
3bc48014	22	#include <linux/smc91x.h>
495f71db	23
a09e64fb	24	#include <mach/hardware.h>
495f71db BS	25	#include <asm/mach-types.h>
	26	#include <asm/mach/arch.h>
	27	#include <asm/mach/flash.h>
	28	#include <asm/mach/map.h>
	29
ce491cf8	30	#include <plat/tc.h>
a09e64fb	31	#include <mach/gpio.h>
ce491cf8 TL	32	#include <plat/mux.h>
ce491cf8 TL	33	#include <plat/fpga.h>
ce491cf8 TL	34	#include <plat/keypad.h>
	35	#include <plat/common.h>
	36	#include <plat/board.h>
d9558b19 TL	37
	38	/* fsample is pretty close to p2-sample */
	39
	40	#define fsample_cpld_read(reg) __raw_readb(reg)
	41	#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
	42
	43	#define FSAMPLE_CPLD_BASE 0xE8100000
	44	#define FSAMPLE_CPLD_SIZE SZ_4K
	45	#define FSAMPLE_CPLD_START 0x05080000
	46
	47	#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
	48	#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
	49	#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
	50	#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
	51	#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
	52	#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
	53
	54	#define FSAMPLE_CPLD_BIT_BT_RESET 0
	55	#define FSAMPLE_CPLD_BIT_LCD_RESET 1
	56	#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
	57	#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
	58	#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
	59	#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
	60	#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
	61	#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
	62	#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
	63	#define FSAMPLE_CPLD_BIT_OTG_RESET 9
	64
	65	#define fsample_cpld_set(bit) \
	66	fsample_cpld_write((((bit) & 15) << 4) \| 0x0f, FSAMPLE_CPLD_SET_CLR)
	67
	68	#define fsample_cpld_clear(bit) \
	69	fsample_cpld_write(0xf0 \| ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
495f71db BS	70
	71	static int fsample_keymap[] = {
	72	KEY(0,0,KEY_UP),
	73	KEY(0,1,KEY_RIGHT),
	74	KEY(0,2,KEY_LEFT),
	75	KEY(0,3,KEY_DOWN),
496bcb81 VK	76	KEY(0,4,KEY_ENTER),
496bcb81 VK	77	KEY(1,0,KEY_F10),
495f71db BS	78	KEY(1,1,KEY_SEND),
	79	KEY(1,2,KEY_END),
	80	KEY(1,3,KEY_VOLUMEDOWN),
	81	KEY(1,4,KEY_VOLUMEUP),
	82	KEY(1,5,KEY_RECORD),
496bcb81	83	KEY(2,0,KEY_F9),
495f71db BS	84	KEY(2,1,KEY_3),
	85	KEY(2,2,KEY_6),
	86	KEY(2,3,KEY_9),
496bcb81	87	KEY(2,4,KEY_KPDOT),
495f71db BS	88	KEY(3,0,KEY_BACK),
	89	KEY(3,1,KEY_2),
	90	KEY(3,2,KEY_5),
	91	KEY(3,3,KEY_8),
	92	KEY(3,4,KEY_0),
496bcb81	93	KEY(3,5,KEY_KPSLASH),
495f71db BS	94	KEY(4,0,KEY_HOME),
	95	KEY(4,1,KEY_1),
	96	KEY(4,2,KEY_4),
	97	KEY(4,3,KEY_7),
496bcb81	98	KEY(4,4,KEY_KPASTERISK),
495f71db BS	99	KEY(4,5,KEY_POWER),
	100	0
	101	};
	102
3bc48014 LM	103	static struct smc91x_platdata smc91x_info = {
	104	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
	105	.leda = RPC_LED_100_10,
	106	.ledb = RPC_LED_TX_RX,
	107	};
	108
495f71db BS	109	static struct resource smc91x_resources[] = {
	110	[0] = {
	111	.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
	112	.end = H2P2_DBG_FPGA_ETHR_START + 0xf,
	113	.flags = IORESOURCE_MEM,
	114	},
	115	[1] = {
372b1c32	116	.start = INT_7XX_MPU_EXT_NIRQ,
495f71db	117	.end = 0,
e7b3dc7e	118	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
495f71db BS	119	},
	120	};
	121
	122	static struct mtd_partition nor_partitions[] = {
	123	/* bootloader (U-Boot, etc) in first sector */
	124	{
	125	.name = "bootloader",
	126	.offset = 0,
	127	.size = SZ_128K,
	128	.mask_flags = MTD_WRITEABLE, /* force read-only */
	129	},
	130	/* bootloader params in the next sector */
	131	{
	132	.name = "params",
	133	.offset = MTDPART_OFS_APPEND,
	134	.size = SZ_128K,
	135	.mask_flags = 0,
	136	},
	137	/* kernel */
	138	{
	139	.name = "kernel",
	140	.offset = MTDPART_OFS_APPEND,
	141	.size = SZ_2M,
	142	.mask_flags = 0
	143	},
	144	/* rest of flash is a file system */
	145	{
	146	.name = "rootfs",
	147	.offset = MTDPART_OFS_APPEND,
	148	.size = MTDPART_SIZ_FULL,
	149	.mask_flags = 0
	150	},
	151	};
	152
	153	static struct flash_platform_data nor_data = {
	154	.map_name = "cfi_probe",
	155	.width = 2,
	156	.parts = nor_partitions,
	157	.nr_parts = ARRAY_SIZE(nor_partitions),
	158	};
	159
	160	static struct resource nor_resource = {
	161	.start = OMAP_CS0_PHYS,
	162	.end = OMAP_CS0_PHYS + SZ_32M - 1,
	163	.flags = IORESOURCE_MEM,
	164	};
	165
	166	static struct platform_device nor_device = {
	167	.name = "omapflash",
	168	.id = 0,
	169	.dev = {
	170	.platform_data = &nor_data,
	171	},
	172	.num_resources = 1,
	173	.resource = &nor_resource,
	174	};
	175
414f552a LM	176	static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	177	{
	178	struct nand_chip *this = mtd->priv;
	179	unsigned long mask;
	180
	181	if (cmd == NAND_CMD_NONE)
	182	return;
	183
	184	mask = (ctrl & NAND_CLE) ? 0x02 : 0;
	185	if (ctrl & NAND_ALE)
	186	mask \|= 0x04;
	187	writeb(cmd, (unsigned long)this->IO_ADDR_W \| mask);
	188	}
	189
	190	#define FSAMPLE_NAND_RB_GPIO_PIN 62
	191
	192	static int nand_dev_ready(struct mtd_info *mtd)
	193	{
	194	return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
	195	}
	196
	197	static const char *part_probes[] = { "cmdlinepart", NULL };
	198
	199	static struct platform_nand_data nand_data = {
	200	.chip = {
	201	.nr_chips = 1,
	202	.chip_offset = 0,
	203	.options = NAND_SAMSUNG_LP_OPTIONS,
	204	.part_probe_types = part_probes,
	205	},
	206	.ctrl = {
	207	.cmd_ctrl = nand_cmd_ctl,
	208	.dev_ready = nand_dev_ready,
	209	},
495f71db BS	210	};
	211
	212	static struct resource nand_resource = {
	213	.start = OMAP_CS3_PHYS,
	214	.end = OMAP_CS3_PHYS + SZ_4K - 1,
	215	.flags = IORESOURCE_MEM,
	216	};
	217
	218	static struct platform_device nand_device = {
414f552a	219	.name = "gen_nand",
495f71db BS	220	.id = 0,
	221	.dev = {
	222	.platform_data = &nand_data,
	223	},
	224	.num_resources = 1,
	225	.resource = &nand_resource,
	226	};
	227
	228	static struct platform_device smc91x_device = {
	229	.name = "smc91x",
	230	.id = 0,
3bc48014 LM	231	.dev = {
	232	.platform_data = &smc91x_info,
	233	},
495f71db BS	234	.num_resources = ARRAY_SIZE(smc91x_resources),
	235	.resource = smc91x_resources,
	236	};
	237
	238	static struct resource kp_resources[] = {
	239	[0] = {
372b1c32 AB	240	.start = INT_7XX_MPUIO_KEYPAD,
372b1c32 AB	241	.end = INT_7XX_MPUIO_KEYPAD,
495f71db BS	242	.flags = IORESOURCE_IRQ,
	243	},
	244	};
	245
	246	static struct omap_kp_platform_data kp_data = {
4d24607b KS	247	.rows = 8,
	248	.cols = 8,
	249	.keymap = fsample_keymap,
	250	.keymapsize = ARRAY_SIZE(fsample_keymap),
	251	.delay = 4,
495f71db BS	252	};
	253
	254	static struct platform_device kp_device = {
	255	.name = "omap-keypad",
	256	.id = -1,
	257	.dev = {
	258	.platform_data = &kp_data,
	259	},
	260	.num_resources = ARRAY_SIZE(kp_resources),
	261	.resource = kp_resources,
	262	};
	263
	264	static struct platform_device lcd_device = {
	265	.name = "lcd_p2",
	266	.id = -1,
	267	};
	268
	269	static struct platform_device *devices[] __initdata = {
	270	&nor_device,
	271	&nand_device,
	272	&smc91x_device,
	273	&kp_device,
	274	&lcd_device,
	275	};
	276
495f71db BS	277	static struct omap_lcd_config fsample_lcd_config __initdata = {
	278	.ctrl_name = "internal",
	279	};
	280
	281	static struct omap_board_config_kernel fsample_config[] = {
495f71db BS	282	{ OMAP_TAG_LCD, &fsample_lcd_config },
	283	};
	284
	285	static void __init omap_fsample_init(void)
	286	{
414f552a	287	if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
f2d18fea	288	BUG();
414f552a	289	gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
495f71db BS	290
	291	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
	292	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
	293
	294	platform_add_devices(devices, ARRAY_SIZE(devices));
	295
	296	omap_board_config = fsample_config;
	297	omap_board_config_size = ARRAY_SIZE(fsample_config);
	298	omap_serial_init();
1ed16a86	299	omap_register_i2c_bus(1, 100, NULL, 0);
495f71db BS	300	}
	301
	302	static void __init fsample_init_smc91x(void)
	303	{
	304	fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
	305	mdelay(50);
	306	fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
	307	H2P2_DBG_FPGA_LAN_RESET);
	308	mdelay(50);
	309	}
	310
277d58ef	311	static void __init omap_fsample_init_irq(void)
495f71db BS	312	{
	313	omap1_init_common_hw();
	314	omap_init_irq();
	315	omap_gpio_init();
	316	fsample_init_smc91x();
	317	}
	318
	319	/* Only FPGA needs to be mapped here. All others are done with ioremap */
	320	static struct map_desc omap_fsample_io_desc[] __initdata = {
	321	{
	322	.virtual = H2P2_DBG_FPGA_BASE,
	323	.pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
	324	.length = H2P2_DBG_FPGA_SIZE,
	325	.type = MT_DEVICE
	326	},
	327	{
	328	.virtual = FSAMPLE_CPLD_BASE,
	329	.pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
	330	.length = FSAMPLE_CPLD_SIZE,
	331	.type = MT_DEVICE
	332	}
	333	};
	334
	335	static void __init omap_fsample_map_io(void)
	336	{
	337	omap1_map_common_io();
	338	iotable_init(omap_fsample_io_desc,
	339	ARRAY_SIZE(omap_fsample_io_desc));
	340
	341	/* Early, board-dependent init */
	342
	343	/*
	344	* Hold GSM Reset until needed
	345	*/
b51988db	346	omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
495f71db BS	347
	348	/*
	349	* UARTs -> done automagically by 8250 driver
	350	*/
	351
	352	/*
	353	* CSx timings, GPIO Mux ... setup
	354	*/
	355
	356	/* Flash: CS0 timings setup */
b51988db AB	357	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
b51988db AB	358	omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
495f71db BS	359
	360	/*
	361	* Ethernet support through the debug board
	362	* CS1 timings setup
	363	*/
b51988db AB	364	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
b51988db AB	365	omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
495f71db BS	366
	367	/*
	368	* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
	369	* It is used as the Ethernet controller interrupt
	370	*/
b51988db	371	omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
495f71db BS	372	}
	373
	374	MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
	375	/* Maintainer: Brian Swetland <swetland@google.com> */
	376	.phys_io = 0xfff00000,
	377	.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
	378	.boot_params = 0x10000100,
	379	.map_io = omap_fsample_map_io,
	380	.init_irq = omap_fsample_init_irq,
	381	.init_machine = omap_fsample_init,
	382	.timer = &omap_timer,
	383	MACHINE_END