[deliverable/linux.git] / arch / arm / mach-omap1 / dma.c

/*
 * OMAP1/OMAP7xx - specific DMA driver
 *
 * Copyright (C) 2003 - 2008 Nokia Corporation
 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
 * Graphics DMA and LCD DMA graphics tranformations
 * by Imre Deak <imre.deak@nokia.com>
 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 * Converted DMA library into platform driver
 *                   - G, Manjunath Kondaiah <manjugk@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/io.h>

#include <plat/dma.h>
#include <plat/tc.h>

#include <mach/irqs.h>

#define OMAP1_DMA_BASE			(0xfffed800)
#define OMAP1_LOGICAL_DMA_CH_COUNT	17
#define OMAP1_DMA_STRIDE		0x40

static u32 errata;
static u32 enable_1510_mode;
static u8 dma_stride;
static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;

static u16 reg_map[] = {
	[GCR]		= 0x400,
	[GSCR]		= 0x404,
	[GRST1]		= 0x408,
	[HW_ID]		= 0x442,
	[PCH2_ID]	= 0x444,
	[PCH0_ID]	= 0x446,
	[PCH1_ID]	= 0x448,
	[PCHG_ID]	= 0x44a,
	[PCHD_ID]	= 0x44c,
	[CAPS_0]	= 0x44e,
	[CAPS_1]	= 0x452,
	[CAPS_2]	= 0x456,
	[CAPS_3]	= 0x458,
	[CAPS_4]	= 0x45a,
	[PCH2_SR]	= 0x460,
	[PCH0_SR]	= 0x480,
	[PCH1_SR]	= 0x482,
	[PCHD_SR]	= 0x4c0,

	/* Common Registers */
	[CSDP]		= 0x00,
	[CCR]		= 0x02,
	[CICR]		= 0x04,
	[CSR]		= 0x06,
	[CEN]		= 0x10,
	[CFN]		= 0x12,
	[CSFI]		= 0x14,
	[CSEI]		= 0x16,
	[CPC]		= 0x18,	/* 15xx only */
	[CSAC]		= 0x18,
	[CDAC]		= 0x1a,
	[CDEI]		= 0x1c,
	[CDFI]		= 0x1e,
	[CLNK_CTRL]	= 0x28,

	/* Channel specific register offsets */
	[CSSA]		= 0x08,
	[CDSA]		= 0x0c,
	[COLOR]		= 0x20,
	[CCR2]		= 0x24,
	[LCH_CTRL]	= 0x2a,
};

static struct resource res[] __initdata = {
	[0] = {
		.start	= OMAP1_DMA_BASE,
		.end	= OMAP1_DMA_BASE + SZ_2K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.name   = "0",
		.start  = INT_DMA_CH0_6,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		.name   = "1",
		.start  = INT_DMA_CH1_7,
		.flags  = IORESOURCE_IRQ,
	},
	[3] = {
		.name   = "2",
		.start  = INT_DMA_CH2_8,
		.flags  = IORESOURCE_IRQ,
	},
	[4] = {
		.name   = "3",
		.start  = INT_DMA_CH3,
		.flags  = IORESOURCE_IRQ,
	},
	[5] = {
		.name   = "4",
		.start  = INT_DMA_CH4,
		.flags  = IORESOURCE_IRQ,
	},
	[6] = {
		.name   = "5",
		.start  = INT_DMA_CH5,
		.flags  = IORESOURCE_IRQ,
	},
	/* Handled in lcd_dma.c */
	[7] = {
		.name   = "6",
		.start  = INT_1610_DMA_CH6,
		.flags  = IORESOURCE_IRQ,
	},
	/* irq's for omap16xx and omap7xx */
	[8] = {
		.name   = "7",
		.start  = INT_1610_DMA_CH7,
		.flags  = IORESOURCE_IRQ,
	},
	[9] = {
		.name   = "8",
		.start  = INT_1610_DMA_CH8,
		.flags  = IORESOURCE_IRQ,
	},
	[10] = {
		.name  = "9",
		.start = INT_1610_DMA_CH9,
		.flags = IORESOURCE_IRQ,
	},
	[11] = {
		.name  = "10",
		.start = INT_1610_DMA_CH10,
		.flags = IORESOURCE_IRQ,
	},
	[12] = {
		.name  = "11",
		.start = INT_1610_DMA_CH11,
		.flags = IORESOURCE_IRQ,
	},
	[13] = {
		.name  = "12",
		.start = INT_1610_DMA_CH12,
		.flags = IORESOURCE_IRQ,
	},
	[14] = {
		.name  = "13",
		.start = INT_1610_DMA_CH13,
		.flags = IORESOURCE_IRQ,
	},
	[15] = {
		.name  = "14",
		.start = INT_1610_DMA_CH14,
		.flags = IORESOURCE_IRQ,
	},
	[16] = {
		.name  = "15",
		.start = INT_1610_DMA_CH15,
		.flags = IORESOURCE_IRQ,
	},
	[17] = {
		.name  = "16",
		.start = INT_DMA_LCD,
		.flags = IORESOURCE_IRQ,
	},
};

static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
	u8  stride;
	u32 offset;

	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
	offset = reg_map[reg] + (stride * lch);

	__raw_writew(val, dma_base + offset);
	if ((reg > CLNK_CTRL && reg < CCEN) ||
			(reg > PCHD_ID && reg < CAPS_2)) {
		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
		__raw_writew(val >> 16, dma_base + offset2);
	}
}

static inline u32 dma_read(int reg, int lch)
{
	u8 stride;
	u32 offset, val;

	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
	offset = reg_map[reg] + (stride * lch);

	val = __raw_readw(dma_base + offset);
	if ((reg > CLNK_CTRL && reg < CCEN) ||
			(reg > PCHD_ID && reg < CAPS_2)) {
		u16 upper;
		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
		upper = __raw_readw(dma_base + offset2);
		val |= (upper << 16);
	}
	return val;
}

static void omap1_clear_lch_regs(int lch)
{
	int i = dma_common_ch_start;

	for (; i <= dma_common_ch_end; i += 1)
		dma_write(0, i, lch);
}

static void omap1_clear_dma(int lch)
{
	u32 l;

	l = dma_read(CCR, lch);
	l &= ~OMAP_DMA_CCR_EN;
	dma_write(l, CCR, lch);

	/* Clear pending interrupts */
	l = dma_read(CSR, lch);
}

static void omap1_show_dma_caps(void)
{
	if (enable_1510_mode) {
		printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
	} else {
		u16 w;
		printk(KERN_INFO "OMAP DMA hardware version %d\n",
							dma_read(HW_ID, 0));
		printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
			dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
			dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
			dma_read(CAPS_4, 0));

		/* Disable OMAP 3.0/3.1 compatibility mode. */
		w = dma_read(GSCR, 0);
		w |= 1 << 3;
		dma_write(w, GSCR, 0);
	}
	return;
}

static u32 configure_dma_errata(void)
{

	/*
	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
	 * read before the DMA controller finished disabling the channel.
	 */
	if (!cpu_is_omap15xx())
		SET_DMA_ERRATA(DMA_ERRATA_3_3);

	return errata;
}

static int __init omap1_system_dma_init(void)
{
	struct omap_system_dma_plat_info	*p;
	struct omap_dma_dev_attr		*d;
	struct platform_device			*pdev;
	int ret;

	pdev = platform_device_alloc("omap_dma_system", 0);
	if (!pdev) {
		pr_err("%s: Unable to device alloc for dma\n",
			__func__);
		return -ENOMEM;
	}

	dma_base = ioremap(res[0].start, resource_size(&res[0]));
	if (!dma_base) {
		pr_err("%s: Unable to ioremap\n", __func__);
		ret = -ENODEV;
		goto exit_device_put;
	}

	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
	if (ret) {
		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
			__func__, pdev->name, pdev->id);
		goto exit_device_put;
	}

	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
	if (!p) {
		dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
			__func__, pdev->name);
		ret = -ENOMEM;
		goto exit_device_del;
	}

	d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
	if (!d) {
		dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
			__func__, pdev->name);
		ret = -ENOMEM;
		goto exit_release_p;
	}

	d->lch_count		= OMAP1_LOGICAL_DMA_CH_COUNT;

	/* Valid attributes for omap1 plus processors */
	if (cpu_is_omap15xx())
		d->dev_caps = ENABLE_1510_MODE;
	enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;

	d->dev_caps		|= SRC_PORT;
	d->dev_caps		|= DST_PORT;
	d->dev_caps		|= SRC_INDEX;
	d->dev_caps		|= DST_INDEX;
	d->dev_caps		|= IS_BURST_ONLY4;
	d->dev_caps		|= CLEAR_CSR_ON_READ;
	d->dev_caps		|= IS_WORD_16;


	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
					(d->lch_count), GFP_KERNEL);
	if (!d->chan) {
		dev_err(&pdev->dev,
			"%s: Memory allocation failed for d->chan!\n",
			__func__);
		goto exit_release_d;
	}

	if (cpu_is_omap15xx())
		d->chan_count = 9;
	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
		if (!(d->dev_caps & ENABLE_1510_MODE))
			d->chan_count = 16;
		else
			d->chan_count = 9;
	}

	p->dma_attr = d;

	p->show_dma_caps	= omap1_show_dma_caps;
	p->clear_lch_regs	= omap1_clear_lch_regs;
	p->clear_dma		= omap1_clear_dma;
	p->dma_write		= dma_write;
	p->dma_read		= dma_read;
	p->disable_irq_lch	= NULL;

	p->errata = configure_dma_errata();

	ret = platform_device_add_data(pdev, p, sizeof(*p));
	if (ret) {
		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
			__func__, pdev->name, pdev->id);
		goto exit_release_chan;
	}

	ret = platform_device_add(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
			__func__, pdev->name, pdev->id);
		goto exit_release_chan;
	}

	dma_stride		= OMAP1_DMA_STRIDE;
	dma_common_ch_start	= CPC;
	dma_common_ch_end	= COLOR;

	return ret;

exit_release_chan:
	kfree(d->chan);
exit_release_d:
	kfree(d);
exit_release_p:
	kfree(p);
exit_device_del:
	platform_device_del(pdev);
exit_device_put:
	platform_device_put(pdev);

	return ret;
}
arch_initcall(omap1_system_dma_init);
Commit	Line	Data
6568f7c4 MK	1	/*
	2	* OMAP1/OMAP7xx - specific DMA driver
	3	*
	4	* Copyright (C) 2003 - 2008 Nokia Corporation
	5	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
	6	* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
	7	* Graphics DMA and LCD DMA graphics tranformations
	8	* by Imre Deak <imre.deak@nokia.com>
	9	* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
	10	* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
	11	*
	12	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	13	* Converted DMA library into platform driver
	14	* - G, Manjunath Kondaiah <manjugk@ti.com>
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/err.h>
6568f7c4 MK	22	#include <linux/slab.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/device.h>
2e3ee9f4	26	#include <linux/io.h>
6568f7c4 MK	27
	28	#include <plat/dma.h>
	29	#include <plat/tc.h>
8afc5e08 TL	30
8afc5e08 TL	31	#include <mach/irqs.h>
6568f7c4 MK	32
6568f7c4 MK	33	#define OMAP1_DMA_BASE (0xfffed800)
f31cc962 MK	34	#define OMAP1_LOGICAL_DMA_CH_COUNT 17
	35	#define OMAP1_DMA_STRIDE 0x40
	36
	37	static u32 errata;
	38	static u32 enable_1510_mode;
	39	static u8 dma_stride;
	40	static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
	41
	42	static u16 reg_map[] = {
	43	[GCR] = 0x400,
	44	[GSCR] = 0x404,
	45	[GRST1] = 0x408,
	46	[HW_ID] = 0x442,
	47	[PCH2_ID] = 0x444,
	48	[PCH0_ID] = 0x446,
	49	[PCH1_ID] = 0x448,
	50	[PCHG_ID] = 0x44a,
	51	[PCHD_ID] = 0x44c,
	52	[CAPS_0] = 0x44e,
	53	[CAPS_1] = 0x452,
	54	[CAPS_2] = 0x456,
	55	[CAPS_3] = 0x458,
	56	[CAPS_4] = 0x45a,
	57	[PCH2_SR] = 0x460,
	58	[PCH0_SR] = 0x480,
	59	[PCH1_SR] = 0x482,
	60	[PCHD_SR] = 0x4c0,
	61
	62	/* Common Registers */
	63	[CSDP] = 0x00,
	64	[CCR] = 0x02,
	65	[CICR] = 0x04,
	66	[CSR] = 0x06,
	67	[CEN] = 0x10,
	68	[CFN] = 0x12,
	69	[CSFI] = 0x14,
	70	[CSEI] = 0x16,
	71	[CPC] = 0x18, /* 15xx only */
	72	[CSAC] = 0x18,
	73	[CDAC] = 0x1a,
	74	[CDEI] = 0x1c,
	75	[CDFI] = 0x1e,
	76	[CLNK_CTRL] = 0x28,
	77
	78	/* Channel specific register offsets */
	79	[CSSA] = 0x08,
	80	[CDSA] = 0x0c,
	81	[COLOR] = 0x20,
	82	[CCR2] = 0x24,
	83	[LCH_CTRL] = 0x2a,
	84	};
6568f7c4 MK	85
	86	static struct resource res[] __initdata = {
	87	[0] = {
	88	.start = OMAP1_DMA_BASE,
	89	.end = OMAP1_DMA_BASE + SZ_2K - 1,
	90	.flags = IORESOURCE_MEM,
	91	},
	92	[1] = {
	93	.name = "0",
	94	.start = INT_DMA_CH0_6,
	95	.flags = IORESOURCE_IRQ,
	96	},
	97	[2] = {
	98	.name = "1",
	99	.start = INT_DMA_CH1_7,
	100	.flags = IORESOURCE_IRQ,
	101	},
	102	[3] = {
	103	.name = "2",
	104	.start = INT_DMA_CH2_8,
	105	.flags = IORESOURCE_IRQ,
	106	},
	107	[4] = {
	108	.name = "3",
	109	.start = INT_DMA_CH3,
	110	.flags = IORESOURCE_IRQ,
	111	},
	112	[5] = {
	113	.name = "4",
	114	.start = INT_DMA_CH4,
	115	.flags = IORESOURCE_IRQ,
	116	},
	117	[6] = {
	118	.name = "5",
	119	.start = INT_DMA_CH5,
	120	.flags = IORESOURCE_IRQ,
	121	},
f31cc962	122	/* Handled in lcd_dma.c */
6568f7c4 MK	123	[7] = {
	124	.name = "6",
	125	.start = INT_1610_DMA_CH6,
	126	.flags = IORESOURCE_IRQ,
	127	},
	128	/* irq's for omap16xx and omap7xx */
	129	[8] = {
	130	.name = "7",
	131	.start = INT_1610_DMA_CH7,
	132	.flags = IORESOURCE_IRQ,
	133	},
	134	[9] = {
	135	.name = "8",
	136	.start = INT_1610_DMA_CH8,
	137	.flags = IORESOURCE_IRQ,
	138	},
	139	[10] = {
	140	.name = "9",
	141	.start = INT_1610_DMA_CH9,
	142	.flags = IORESOURCE_IRQ,
	143	},
	144	[11] = {
	145	.name = "10",
	146	.start = INT_1610_DMA_CH10,
	147	.flags = IORESOURCE_IRQ,
	148	},
	149	[12] = {
	150	.name = "11",
	151	.start = INT_1610_DMA_CH11,
	152	.flags = IORESOURCE_IRQ,
	153	},
	154	[13] = {
	155	.name = "12",
	156	.start = INT_1610_DMA_CH12,
	157	.flags = IORESOURCE_IRQ,
	158	},
	159	[14] = {
	160	.name = "13",
	161	.start = INT_1610_DMA_CH13,
	162	.flags = IORESOURCE_IRQ,
	163	},
	164	[15] = {
	165	.name = "14",
	166	.start = INT_1610_DMA_CH14,
	167	.flags = IORESOURCE_IRQ,
	168	},
	169	[16] = {
	170	.name = "15",
	171	.start = INT_1610_DMA_CH15,
	172	.flags = IORESOURCE_IRQ,
	173	},
	174	[17] = {
	175	.name = "16",
	176	.start = INT_DMA_LCD,
	177	.flags = IORESOURCE_IRQ,
	178	},
	179	};
	180
f31cc962 MK	181	static void __iomem *dma_base;
	182	static inline void dma_write(u32 val, int reg, int lch)
	183	{
	184	u8 stride;
	185	u32 offset;
	186
	187	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
	188	offset = reg_map[reg] + (stride * lch);
	189
	190	__raw_writew(val, dma_base + offset);
	191	if ((reg > CLNK_CTRL && reg < CCEN) \|\|
	192	(reg > PCHD_ID && reg < CAPS_2)) {
	193	u32 offset2 = reg_map[reg] + 2 + (stride * lch);
	194	__raw_writew(val >> 16, dma_base + offset2);
	195	}
	196	}
	197
	198	static inline u32 dma_read(int reg, int lch)
	199	{
	200	u8 stride;
	201	u32 offset, val;
	202
	203	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
	204	offset = reg_map[reg] + (stride * lch);
	205
	206	val = __raw_readw(dma_base + offset);
	207	if ((reg > CLNK_CTRL && reg < CCEN) \|\|
	208	(reg > PCHD_ID && reg < CAPS_2)) {
	209	u16 upper;
	210	u32 offset2 = reg_map[reg] + 2 + (stride * lch);
	211	upper = __raw_readw(dma_base + offset2);
	212	val \|= (upper << 16);
	213	}
	214	return val;
	215	}
	216
	217	static void omap1_clear_lch_regs(int lch)
	218	{
	219	int i = dma_common_ch_start;
	220
	221	for (; i <= dma_common_ch_end; i += 1)
	222	dma_write(0, i, lch);
	223	}
	224
	225	static void omap1_clear_dma(int lch)
	226	{
	227	u32 l;
	228
	229	l = dma_read(CCR, lch);
	230	l &= ~OMAP_DMA_CCR_EN;
	231	dma_write(l, CCR, lch);
	232
	233	/* Clear pending interrupts */
	234	l = dma_read(CSR, lch);
	235	}
	236
	237	static void omap1_show_dma_caps(void)
	238	{
	239	if (enable_1510_mode) {
	240	printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
	241	} else {
	242	u16 w;
	243	printk(KERN_INFO "OMAP DMA hardware version %d\n",
	244	dma_read(HW_ID, 0));
245	printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
246	dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
247	dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
248	dma_read(CAPS_4, 0));
249
250	/* Disable OMAP 3.0/3.1 compatibility mode. */
251	w = dma_read(GSCR, 0);
252	w \|= 1 << 3;
253	dma_write(w, GSCR, 0);
254	}
255	return;
256	}
257
258	static u32 configure_dma_errata(void)
259	{
260
261	/*
262	* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
263	* read before the DMA controller finished disabling the channel.
264	*/
265	if (!cpu_is_omap15xx())
266	SET_DMA_ERRATA(DMA_ERRATA_3_3);
267
268	return errata;
269	}
270
6568f7c4 MK	271	static int __init omap1_system_dma_init(void)
	272	{
	273	struct omap_system_dma_plat_info *p;
f31cc962	274	struct omap_dma_dev_attr *d;
6568f7c4 MK	275	struct platform_device *pdev;
	276	int ret;
	277
	278	pdev = platform_device_alloc("omap_dma_system", 0);
	279	if (!pdev) {
	280	pr_err("%s: Unable to device alloc for dma\n",
	281	__func__);
	282	return -ENOMEM;
	283	}
	284
f31cc962 MK	285	dma_base = ioremap(res[0].start, resource_size(&res[0]));
	286	if (!dma_base) {
	287	pr_err("%s: Unable to ioremap\n", __func__);
77f7059a JL	288	ret = -ENODEV;
77f7059a JL	289	goto exit_device_put;
f31cc962 MK	290	}
f31cc962 MK	291
6568f7c4 MK	292	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
	293	if (ret) {
	294	dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
	295	__func__, pdev->name, pdev->id);
77f7059a	296	goto exit_device_put;
6568f7c4 MK	297	}
	298
	299	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
	300	if (!p) {
	301	dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
	302	__func__, pdev->name);
	303	ret = -ENOMEM;
77f7059a	304	goto exit_device_del;
6568f7c4 MK	305	}
6568f7c4 MK	306
f31cc962 MK	307	d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
	308	if (!d) {
	309	dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
	310	__func__, pdev->name);
	311	ret = -ENOMEM;
	312	goto exit_release_p;
	313	}
	314
	315	d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
	316
	317	/* Valid attributes for omap1 plus processors */
	318	if (cpu_is_omap15xx())
	319	d->dev_caps = ENABLE_1510_MODE;
	320	enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
	321
	322	d->dev_caps \|= SRC_PORT;
	323	d->dev_caps \|= DST_PORT;
	324	d->dev_caps \|= SRC_INDEX;
	325	d->dev_caps \|= DST_INDEX;
	326	d->dev_caps \|= IS_BURST_ONLY4;
	327	d->dev_caps \|= CLEAR_CSR_ON_READ;
	328	d->dev_caps \|= IS_WORD_16;
	329
	330
	331	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
	332	(d->lch_count), GFP_KERNEL);
	333	if (!d->chan) {
7852ec05 PW	334	dev_err(&pdev->dev,
	335	"%s: Memory allocation failed for d->chan!\n",
	336	__func__);
f31cc962 MK	337	goto exit_release_d;
	338	}
	339
	340	if (cpu_is_omap15xx())
	341	d->chan_count = 9;
	342	else if (cpu_is_omap16xx() \|\| cpu_is_omap7xx()) {
	343	if (!(d->dev_caps & ENABLE_1510_MODE))
	344	d->chan_count = 16;
	345	else
	346	d->chan_count = 9;
	347	}
	348
	349	p->dma_attr = d;
	350
	351	p->show_dma_caps = omap1_show_dma_caps;
	352	p->clear_lch_regs = omap1_clear_lch_regs;
	353	p->clear_dma = omap1_clear_dma;
	354	p->dma_write = dma_write;
	355	p->dma_read = dma_read;
	356	p->disable_irq_lch = NULL;
	357
	358	p->errata = configure_dma_errata();
	359
6568f7c4 MK	360	ret = platform_device_add_data(pdev, p, sizeof(*p));
	361	if (ret) {
	362	dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
	363	__func__, pdev->name, pdev->id);
f31cc962	364	goto exit_release_chan;
6568f7c4 MK	365	}
	366
	367	ret = platform_device_add(pdev);
	368	if (ret) {
	369	dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
	370	__func__, pdev->name, pdev->id);
f31cc962	371	goto exit_release_chan;
6568f7c4 MK	372	}
6568f7c4 MK	373
f31cc962 MK	374	dma_stride = OMAP1_DMA_STRIDE;
	375	dma_common_ch_start = CPC;
	376	dma_common_ch_end = COLOR;
	377
6568f7c4 MK	378	return ret;
6568f7c4 MK	379
f31cc962 MK	380	exit_release_chan:
	381	kfree(d->chan);
	382	exit_release_d:
	383	kfree(d);
	384	exit_release_p:
	385	kfree(p);
6568f7c4 MK	386	exit_device_del:
6568f7c4 MK	387	platform_device_del(pdev);
77f7059a JL	388	exit_device_put:
77f7059a JL	389	platform_device_put(pdev);
6568f7c4 MK	390
	391	return ret;
	392	}
	393	arch_initcall(omap1_system_dma_init);