Commit | Line | Data |
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1da177e4 | 1 | /* |
7c38cf02 | 2 | * linux/arch/arm/mach-omap1/fpga.c |
1da177e4 LT |
3 | * |
4 | * Interrupt handler for OMAP-1510 Innovator FPGA | |
5 | * | |
6 | * Copyright (C) 2001 RidgeRun, Inc. | |
7 | * Author: Greg Lonnon <glonnon@ridgerun.com> | |
8 | * | |
9 | * Copyright (C) 2002 MontaVista Software, Inc. | |
10 | * | |
11 | * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 | |
12 | * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
1da177e4 | 19 | #include <linux/types.h> |
2f8163ba | 20 | #include <linux/gpio.h> |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/errno.h> | |
fced80c7 | 25 | #include <linux/io.h> |
1da177e4 | 26 | |
1da177e4 LT |
27 | #include <asm/irq.h> |
28 | #include <asm/mach/irq.h> | |
29 | ||
4c98dc6b | 30 | #include <../plat-omap/fpga.h> |
1da177e4 | 31 | |
2e3ee9f4 TL |
32 | #include <mach/hardware.h> |
33 | ||
34 | #include "iomap.h" | |
35 | ||
a51eef7e | 36 | static void fpga_mask_irq(struct irq_data *d) |
1da177e4 | 37 | { |
a51eef7e | 38 | unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; |
1da177e4 LT |
39 | |
40 | if (irq < 8) | |
41 | __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | |
42 | & ~(1 << irq)), OMAP1510_FPGA_IMR_LO); | |
43 | else if (irq < 16) | |
44 | __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) | |
45 | & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); | |
46 | else | |
47 | __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) | |
48 | & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2); | |
49 | } | |
50 | ||
51 | ||
52 | static inline u32 get_fpga_unmasked_irqs(void) | |
53 | { | |
54 | return | |
55 | ((__raw_readb(OMAP1510_FPGA_ISR_LO) & | |
56 | __raw_readb(OMAP1510_FPGA_IMR_LO))) | | |
57 | ((__raw_readb(OMAP1510_FPGA_ISR_HI) & | |
58 | __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) | | |
59 | ((__raw_readb(INNOVATOR_FPGA_ISR2) & | |
60 | __raw_readb(INNOVATOR_FPGA_IMR2)) << 16); | |
61 | } | |
62 | ||
63 | ||
a51eef7e | 64 | static void fpga_ack_irq(struct irq_data *d) |
1da177e4 LT |
65 | { |
66 | /* Don't need to explicitly ACK FPGA interrupts */ | |
67 | } | |
68 | ||
a51eef7e | 69 | static void fpga_unmask_irq(struct irq_data *d) |
1da177e4 | 70 | { |
a51eef7e | 71 | unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; |
1da177e4 LT |
72 | |
73 | if (irq < 8) | |
74 | __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), | |
75 | OMAP1510_FPGA_IMR_LO); | |
76 | else if (irq < 16) | |
77 | __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) | |
78 | | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); | |
79 | else | |
80 | __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) | |
81 | | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); | |
82 | } | |
83 | ||
a51eef7e | 84 | static void fpga_mask_ack_irq(struct irq_data *d) |
1da177e4 | 85 | { |
a51eef7e LB |
86 | fpga_mask_irq(d); |
87 | fpga_ack_irq(d); | |
1da177e4 LT |
88 | } |
89 | ||
8c3d4534 | 90 | static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) |
1da177e4 | 91 | { |
1da177e4 LT |
92 | u32 stat; |
93 | int fpga_irq; | |
94 | ||
95 | stat = get_fpga_unmasked_irqs(); | |
96 | ||
97 | if (!stat) | |
98 | return; | |
99 | ||
44f78f43 TL |
100 | for (fpga_irq = OMAP_FPGA_IRQ_BASE; |
101 | (fpga_irq < OMAP_FPGA_IRQ_END) && stat; | |
1da177e4 LT |
102 | fpga_irq++, stat >>= 1) { |
103 | if (stat & 1) { | |
d8aa0251 | 104 | generic_handle_irq(fpga_irq); |
1da177e4 LT |
105 | } |
106 | } | |
107 | } | |
108 | ||
38c677cb DB |
109 | static struct irq_chip omap_fpga_irq_ack = { |
110 | .name = "FPGA-ack", | |
a51eef7e LB |
111 | .irq_ack = fpga_mask_ack_irq, |
112 | .irq_mask = fpga_mask_irq, | |
113 | .irq_unmask = fpga_unmask_irq, | |
1da177e4 LT |
114 | }; |
115 | ||
116 | ||
38c677cb DB |
117 | static struct irq_chip omap_fpga_irq = { |
118 | .name = "FPGA", | |
a51eef7e LB |
119 | .irq_ack = fpga_ack_irq, |
120 | .irq_mask = fpga_mask_irq, | |
121 | .irq_unmask = fpga_unmask_irq, | |
1da177e4 LT |
122 | }; |
123 | ||
124 | /* | |
125 | * All of the FPGA interrupt request inputs except for the touchscreen are | |
126 | * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive | |
127 | * interrupts are acknowledged as a side-effect of reading the interrupt | |
128 | * status register from the FPGA. The edge-sensitive interrupt inputs | |
129 | * cause a problem with level interrupt requests, such as Ethernet. The | |
130 | * problem occurs when a level interrupt request is asserted while its | |
131 | * interrupt input is masked in the FPGA, which results in a missed | |
132 | * interrupt. | |
133 | * | |
134 | * In an attempt to workaround the problem with missed interrupts, the | |
135 | * mask_ack routine for all of the FPGA interrupts has been changed from | |
136 | * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt | |
137 | * being serviced is left unmasked. We can do this because the FPGA cascade | |
52e405ea | 138 | * interrupt is installed with the IRQF_DISABLED flag, which leaves all |
1da177e4 LT |
139 | * interrupts masked at the CPU while an FPGA interrupt handler executes. |
140 | * | |
141 | * Limited testing indicates that this workaround appears to be effective | |
142 | * for the smc9194 Ethernet driver used on the Innovator. It should work | |
143 | * on other FPGA interrupts as well, but any drivers that explicitly mask | |
144 | * interrupts at the interrupt controller via disable_irq/enable_irq | |
145 | * could pose a problem. | |
146 | */ | |
147 | void omap1510_fpga_init_irq(void) | |
148 | { | |
65dd4c16 | 149 | int i, res; |
1da177e4 LT |
150 | |
151 | __raw_writeb(0, OMAP1510_FPGA_IMR_LO); | |
152 | __raw_writeb(0, OMAP1510_FPGA_IMR_HI); | |
153 | __raw_writeb(0, INNOVATOR_FPGA_IMR2); | |
154 | ||
44f78f43 | 155 | for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) { |
1da177e4 LT |
156 | |
157 | if (i == OMAP1510_INT_FPGA_TS) { | |
158 | /* | |
159 | * The touchscreen interrupt is level-sensitive, so | |
160 | * we'll use the regular mask_ack routine for it. | |
161 | */ | |
6845664a | 162 | irq_set_chip(i, &omap_fpga_irq_ack); |
1da177e4 LT |
163 | } |
164 | else { | |
165 | /* | |
166 | * All FPGA interrupts except the touchscreen are | |
167 | * edge-sensitive, so we won't mask them. | |
168 | */ | |
6845664a | 169 | irq_set_chip(i, &omap_fpga_irq); |
1da177e4 LT |
170 | } |
171 | ||
6845664a | 172 | irq_set_handler(i, handle_edge_irq); |
1da177e4 LT |
173 | set_irq_flags(i, IRQF_VALID); |
174 | } | |
175 | ||
176 | /* | |
177 | * The FPGA interrupt line is connected to GPIO13. Claim this pin for | |
178 | * the ARM. | |
179 | * | |
180 | * NOTE: For general GPIO/MPUIO access and interrupts, please see | |
181 | * gpio.[ch] | |
182 | */ | |
65dd4c16 TL |
183 | res = gpio_request(13, "FPGA irq"); |
184 | if (res) { | |
185 | pr_err("%s failed to get gpio\n", __func__); | |
186 | return; | |
187 | } | |
40e3925b | 188 | gpio_direction_input(13); |
6845664a TG |
189 | irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
190 | irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); | |
1da177e4 | 191 | } |