Commit | Line | Data |
---|---|---|
340a614a | 1 | /* |
d742709e | 2 | * Mailbox reservation modules for OMAP1 |
340a614a | 3 | * |
f98d67a0 | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
340a614a HD |
5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
340a614a HD |
12 | #include <linux/interrupt.h> |
13 | #include <linux/platform_device.h> | |
fced80c7 | 14 | #include <linux/io.h> |
ce491cf8 | 15 | #include <plat/mailbox.h> |
340a614a HD |
16 | |
17 | #define MAILBOX_ARM2DSP1 0x00 | |
18 | #define MAILBOX_ARM2DSP1b 0x04 | |
19 | #define MAILBOX_DSP2ARM1 0x08 | |
20 | #define MAILBOX_DSP2ARM1b 0x0c | |
21 | #define MAILBOX_DSP2ARM2 0x10 | |
22 | #define MAILBOX_DSP2ARM2b 0x14 | |
23 | #define MAILBOX_ARM2DSP1_Flag 0x18 | |
24 | #define MAILBOX_DSP2ARM1_Flag 0x1c | |
25 | #define MAILBOX_DSP2ARM2_Flag 0x20 | |
26 | ||
f98d67a0 | 27 | static void __iomem *mbox_base; |
340a614a HD |
28 | |
29 | struct omap_mbox1_fifo { | |
30 | unsigned long cmd; | |
31 | unsigned long data; | |
32 | unsigned long flag; | |
33 | }; | |
34 | ||
35 | struct omap_mbox1_priv { | |
36 | struct omap_mbox1_fifo tx_fifo; | |
37 | struct omap_mbox1_fifo rx_fifo; | |
38 | }; | |
39 | ||
f98d67a0 | 40 | static inline int mbox_read_reg(size_t ofs) |
340a614a | 41 | { |
f98d67a0 | 42 | return __raw_readw(mbox_base + ofs); |
340a614a HD |
43 | } |
44 | ||
f98d67a0 | 45 | static inline void mbox_write_reg(u32 val, size_t ofs) |
340a614a | 46 | { |
f98d67a0 | 47 | __raw_writew(val, mbox_base + ofs); |
340a614a HD |
48 | } |
49 | ||
50 | /* msg */ | |
e27a93a9 | 51 | static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox) |
340a614a HD |
52 | { |
53 | struct omap_mbox1_fifo *fifo = | |
54 | &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; | |
55 | mbox_msg_t msg; | |
56 | ||
57 | msg = mbox_read_reg(fifo->data); | |
58 | msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16; | |
59 | ||
60 | return msg; | |
61 | } | |
62 | ||
e27a93a9 | 63 | static void |
340a614a HD |
64 | omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) |
65 | { | |
66 | struct omap_mbox1_fifo *fifo = | |
67 | &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo; | |
68 | ||
69 | mbox_write_reg(msg & 0xffff, fifo->data); | |
70 | mbox_write_reg(msg >> 16, fifo->cmd); | |
71 | } | |
72 | ||
e27a93a9 | 73 | static int omap1_mbox_fifo_empty(struct omap_mbox *mbox) |
340a614a HD |
74 | { |
75 | return 0; | |
76 | } | |
77 | ||
e27a93a9 | 78 | static int omap1_mbox_fifo_full(struct omap_mbox *mbox) |
340a614a HD |
79 | { |
80 | struct omap_mbox1_fifo *fifo = | |
81 | &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; | |
82 | ||
909f9dc7 | 83 | return mbox_read_reg(fifo->flag); |
340a614a HD |
84 | } |
85 | ||
86 | /* irq */ | |
e27a93a9 | 87 | static void |
340a614a HD |
88 | omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) |
89 | { | |
90 | if (irq == IRQ_RX) | |
91 | enable_irq(mbox->irq); | |
92 | } | |
93 | ||
e27a93a9 | 94 | static void |
340a614a HD |
95 | omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) |
96 | { | |
97 | if (irq == IRQ_RX) | |
98 | disable_irq(mbox->irq); | |
99 | } | |
100 | ||
e27a93a9 | 101 | static int |
340a614a HD |
102 | omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) |
103 | { | |
104 | if (irq == IRQ_TX) | |
105 | return 0; | |
106 | return 1; | |
107 | } | |
108 | ||
109 | static struct omap_mbox_ops omap1_mbox_ops = { | |
110 | .type = OMAP_MBOX_TYPE1, | |
111 | .fifo_read = omap1_mbox_fifo_read, | |
112 | .fifo_write = omap1_mbox_fifo_write, | |
113 | .fifo_empty = omap1_mbox_fifo_empty, | |
114 | .fifo_full = omap1_mbox_fifo_full, | |
115 | .enable_irq = omap1_mbox_enable_irq, | |
116 | .disable_irq = omap1_mbox_disable_irq, | |
117 | .is_irq = omap1_mbox_is_irq, | |
118 | }; | |
119 | ||
120 | /* FIXME: the following struct should be created automatically by the user id */ | |
121 | ||
122 | /* DSP */ | |
123 | static struct omap_mbox1_priv omap1_mbox_dsp_priv = { | |
124 | .tx_fifo = { | |
125 | .cmd = MAILBOX_ARM2DSP1b, | |
126 | .data = MAILBOX_ARM2DSP1, | |
127 | .flag = MAILBOX_ARM2DSP1_Flag, | |
128 | }, | |
129 | .rx_fifo = { | |
130 | .cmd = MAILBOX_DSP2ARM1b, | |
131 | .data = MAILBOX_DSP2ARM1, | |
132 | .flag = MAILBOX_DSP2ARM1_Flag, | |
133 | }, | |
134 | }; | |
135 | ||
dba5e190 | 136 | static struct omap_mbox mbox_dsp_info = { |
340a614a HD |
137 | .name = "dsp", |
138 | .ops = &omap1_mbox_ops, | |
139 | .priv = &omap1_mbox_dsp_priv, | |
140 | }; | |
340a614a | 141 | |
dba5e190 | 142 | static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; |
898ee756 | 143 | |
f98d67a0 | 144 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
340a614a | 145 | { |
898ee756 | 146 | struct resource *mem; |
5f1af5c7 | 147 | int ret; |
9c80c8cd | 148 | struct omap_mbox **list; |
340a614a | 149 | |
898ee756 | 150 | list = omap1_mboxes; |
898ee756 | 151 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); |
d761585a | 152 | |
898ee756 FC |
153 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
154 | mbox_base = ioremap(mem->start, resource_size(mem)); | |
5f1af5c7 FC |
155 | if (!mbox_base) |
156 | return -ENOMEM; | |
340a614a | 157 | |
9c80c8cd FC |
158 | ret = omap_mbox_register(&pdev->dev, list); |
159 | if (ret) { | |
160 | iounmap(mbox_base); | |
161 | return ret; | |
340a614a | 162 | } |
5f1af5c7 | 163 | |
9c80c8cd | 164 | return 0; |
340a614a HD |
165 | } |
166 | ||
f98d67a0 | 167 | static int __devexit omap1_mbox_remove(struct platform_device *pdev) |
340a614a | 168 | { |
9c80c8cd | 169 | omap_mbox_unregister(); |
5f1af5c7 | 170 | iounmap(mbox_base); |
340a614a HD |
171 | return 0; |
172 | } | |
173 | ||
174 | static struct platform_driver omap1_mbox_driver = { | |
175 | .probe = omap1_mbox_probe, | |
f98d67a0 | 176 | .remove = __devexit_p(omap1_mbox_remove), |
340a614a | 177 | .driver = { |
d742709e | 178 | .name = "omap-mailbox", |
340a614a HD |
179 | }, |
180 | }; | |
181 | ||
182 | static int __init omap1_mbox_init(void) | |
183 | { | |
184 | return platform_driver_register(&omap1_mbox_driver); | |
185 | } | |
186 | ||
187 | static void __exit omap1_mbox_exit(void) | |
188 | { | |
189 | platform_driver_unregister(&omap1_mbox_driver); | |
190 | } | |
191 | ||
192 | module_init(omap1_mbox_init); | |
193 | module_exit(omap1_mbox_exit); | |
194 | ||
f98d67a0 HD |
195 | MODULE_LICENSE("GPL v2"); |
196 | MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); | |
0c405b33 | 197 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); |
f98d67a0 | 198 | MODULE_ALIAS("platform:omap1-mailbox"); |