Commit | Line | Data |
---|---|---|
5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/ocpi.c | |
3 | * | |
4 | * Minimal OCP bus support for omap16xx | |
5 | * | |
6 | * Copyright (C) 2003 - 2005 Nokia Corporation | |
6f3c1af2 | 7 | * Copyright (C) 2012 Texas Instruments, Inc. |
5e1c5ff4 TL |
8 | * Written by Tony Lindgren <tony@atomide.com> |
9 | * | |
10 | * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
5e1c5ff4 | 27 | #include <linux/module.h> |
5e1c5ff4 TL |
28 | #include <linux/types.h> |
29 | #include <linux/errno.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/err.h> | |
f8ce2547 | 34 | #include <linux/clk.h> |
fced80c7 | 35 | #include <linux/io.h> |
5e1c5ff4 | 36 | |
a09e64fb | 37 | #include <mach/hardware.h> |
5e1c5ff4 | 38 | |
6f3c1af2 PW |
39 | #include "common.h" |
40 | ||
5e1c5ff4 TL |
41 | #define OCPI_BASE 0xfffec320 |
42 | #define OCPI_FAULT (OCPI_BASE + 0x00) | |
43 | #define OCPI_CMD_FAULT (OCPI_BASE + 0x04) | |
44 | #define OCPI_SINT0 (OCPI_BASE + 0x08) | |
45 | #define OCPI_TABORT (OCPI_BASE + 0x0c) | |
46 | #define OCPI_SINT1 (OCPI_BASE + 0x10) | |
47 | #define OCPI_PROT (OCPI_BASE + 0x14) | |
48 | #define OCPI_SEC (OCPI_BASE + 0x18) | |
49 | ||
50 | /* USB OHCI OCPI access error registers */ | |
51 | #define HOSTUEADDR 0xfffba0e0 | |
52 | #define HOSTUESTATUS 0xfffba0e4 | |
53 | ||
54 | static struct clk *ocpi_ck; | |
55 | ||
56 | /* | |
57 | * Enables device access to OMAP buses via the OCPI bridge | |
5e1c5ff4 TL |
58 | */ |
59 | int ocpi_enable(void) | |
60 | { | |
61 | unsigned int val; | |
62 | ||
63 | if (!cpu_is_omap16xx()) | |
64 | return -ENODEV; | |
65 | ||
5e1c5ff4 TL |
66 | /* Enable access for OHCI in OCPI */ |
67 | val = omap_readl(OCPI_PROT); | |
68 | val &= ~0xff; | |
6f3c1af2 | 69 | /* val &= (1 << 0); Allow access only to EMIFS */ |
5e1c5ff4 TL |
70 | omap_writel(val, OCPI_PROT); |
71 | ||
72 | val = omap_readl(OCPI_SEC); | |
73 | val &= ~0xff; | |
74 | omap_writel(val, OCPI_SEC); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | EXPORT_SYMBOL(ocpi_enable); | |
79 | ||
80 | static int __init omap_ocpi_init(void) | |
81 | { | |
82 | if (!cpu_is_omap16xx()) | |
83 | return -ENODEV; | |
84 | ||
85 | ocpi_ck = clk_get(NULL, "l3_ocpi_ck"); | |
86 | if (IS_ERR(ocpi_ck)) | |
87 | return PTR_ERR(ocpi_ck); | |
88 | ||
30ff720b | 89 | clk_enable(ocpi_ck); |
5e1c5ff4 | 90 | ocpi_enable(); |
6f3c1af2 | 91 | pr_info("OMAP OCPI interconnect driver loaded\n"); |
5e1c5ff4 TL |
92 | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static void __exit omap_ocpi_exit(void) | |
97 | { | |
98 | /* REVISIT: Disable OCPI */ | |
99 | ||
100 | if (!cpu_is_omap16xx()) | |
101 | return; | |
102 | ||
30ff720b | 103 | clk_disable(ocpi_ck); |
5e1c5ff4 TL |
104 | clk_put(ocpi_ck); |
105 | } | |
106 | ||
107 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
108 | MODULE_DESCRIPTION("OMAP OCPI bus controller module"); | |
109 | MODULE_LICENSE("GPL"); | |
110 | module_init(omap_ocpi_init); | |
111 | module_exit(omap_ocpi_exit); |