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670c104a TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/pm.c | |
3 | * | |
4 | * OMAP Power Management Routines | |
5 | * | |
6 | * Original code for the SA11x0: | |
7 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> | |
8 | * | |
9 | * Modified for the PXA250 by Nicolas Pitre: | |
10 | * Copyright (c) 2002 Monta Vista Software, Inc. | |
11 | * | |
12 | * Modified for the OMAP1510 by David Singleton: | |
13 | * Copyright (c) 2002 Monta Vista Software, Inc. | |
14 | * | |
15 | * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify it | |
18 | * under the terms of the GNU General Public License as published by the | |
19 | * Free Software Foundation; either version 2 of the License, or (at your | |
20 | * option) any later version. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
95d9ffbe | 38 | #include <linux/suspend.h> |
670c104a | 39 | #include <linux/sched.h> |
f9368c18 TL |
40 | #include <linux/debugfs.h> |
41 | #include <linux/seq_file.h> | |
670c104a TL |
42 | #include <linux/interrupt.h> |
43 | #include <linux/sysfs.h> | |
44 | #include <linux/module.h> | |
fced80c7 | 45 | #include <linux/io.h> |
0bcd24b0 | 46 | #include <linux/atomic.h> |
f7b861b7 | 47 | #include <linux/cpu.h> |
670c104a | 48 | |
bf027ca1 | 49 | #include <asm/fncpy.h> |
335aece5 | 50 | #include <asm/system_misc.h> |
670c104a | 51 | #include <asm/irq.h> |
670c104a TL |
52 | #include <asm/mach/time.h> |
53 | #include <asm/mach/irq.h> | |
670c104a | 54 | |
54b693d4 | 55 | #include <mach/tc.h> |
70c494c3 | 56 | #include <mach/mux.h> |
45c3eb7d | 57 | #include <linux/omap-dma.h> |
ce491cf8 | 58 | #include <plat/dmtimer.h> |
670c104a | 59 | |
2e3ee9f4 TL |
60 | #include <mach/irqs.h> |
61 | ||
62 | #include "iomap.h" | |
a135eaae | 63 | #include "clock.h" |
c912f7e1 | 64 | #include "pm.h" |
e99b32e2 | 65 | #include "soc.h" |
bf027ca1 | 66 | #include "sram.h" |
c912f7e1 | 67 | |
670c104a TL |
68 | static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; |
69 | static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; | |
70 | static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; | |
7c006926 | 71 | static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; |
670c104a TL |
72 | static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; |
73 | static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; | |
74 | ||
7239d309 | 75 | static unsigned short enable_dyn_sleep; |
670c104a | 76 | |
851324c6 GKH |
77 | static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, |
78 | char *buf) | |
670c104a TL |
79 | { |
80 | return sprintf(buf, "%hu\n", enable_dyn_sleep); | |
81 | } | |
82 | ||
851324c6 GKH |
83 | static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, |
84 | const char * buf, size_t n) | |
670c104a TL |
85 | { |
86 | unsigned short value; | |
87 | if (sscanf(buf, "%hu", &value) != 1 || | |
7239d309 PW |
88 | (value != 0 && value != 1) || |
89 | (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) { | |
90 | pr_err("idle_sleep_store: Invalid value\n"); | |
670c104a TL |
91 | return -EINVAL; |
92 | } | |
93 | enable_dyn_sleep = value; | |
94 | return n; | |
95 | } | |
96 | ||
851324c6 GKH |
97 | static struct kobj_attribute sleep_while_idle_attr = |
98 | __ATTR(sleep_while_idle, 0644, idle_show, idle_store); | |
670c104a | 99 | |
010bb0cf | 100 | |
670c104a TL |
101 | static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; |
102 | ||
103 | /* | |
104 | * Let's power down on idle, but only if we are really | |
105 | * idle, because once we start down the path of | |
106 | * going idle we continue to do idle even if we get | |
107 | * a clock tick interrupt . . | |
108 | */ | |
c912f7e1 | 109 | void omap1_pm_idle(void) |
670c104a TL |
110 | { |
111 | extern __u32 arm_idlect1_mask; | |
112 | __u32 use_idlect1 = arm_idlect1_mask; | |
670c104a | 113 | |
670c104a | 114 | local_fiq_disable(); |
670c104a | 115 | |
be26a008 | 116 | #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) |
670c104a | 117 | use_idlect1 = use_idlect1 & ~(1 << 9); |
010bb0cf VK |
118 | #endif |
119 | ||
670c104a TL |
120 | #ifdef CONFIG_OMAP_DM_TIMER |
121 | use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); | |
122 | #endif | |
123 | ||
6ea59bb3 | 124 | if (omap_dma_running()) |
670c104a | 125 | use_idlect1 &= ~(1 << 6); |
670c104a | 126 | |
7239d309 PW |
127 | /* |
128 | * We should be able to remove the do_sleep variable and multiple | |
670c104a | 129 | * tests above as soon as drivers, timer and DMA code have been fixed. |
7239d309 PW |
130 | * Even the sleep block count should become obsolete. |
131 | */ | |
132 | if ((use_idlect1 != ~0) || !enable_dyn_sleep) { | |
670c104a TL |
133 | |
134 | __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); | |
135 | if (cpu_is_omap15xx()) | |
136 | use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; | |
137 | else | |
138 | use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; | |
139 | omap_writel(use_idlect1, ARM_IDLECT1); | |
140 | __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); | |
141 | omap_writel(saved_idlect1, ARM_IDLECT1); | |
142 | ||
143 | local_fiq_enable(); | |
670c104a TL |
144 | return; |
145 | } | |
146 | omap_sram_suspend(omap_readl(ARM_IDLECT1), | |
147 | omap_readl(ARM_IDLECT2)); | |
670c104a TL |
148 | |
149 | local_fiq_enable(); | |
670c104a TL |
150 | } |
151 | ||
152 | /* | |
153 | * Configuration of the wakeup event is board specific. For the | |
154 | * moment we put it into this helper function. Later it may move | |
155 | * to board specific files. | |
156 | */ | |
157 | static void omap_pm_wakeup_setup(void) | |
158 | { | |
159 | u32 level1_wake = 0; | |
160 | u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); | |
161 | ||
162 | /* | |
163 | * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, | |
164 | * and the L2 wakeup interrupts: keypad and UART2. Note that the | |
165 | * drivers must still separately call omap_set_gpio_wakeup() to | |
166 | * wake up to a GPIO interrupt. | |
167 | */ | |
4b9100dd | 168 | if (cpu_is_omap7xx()) |
372b1c32 AB |
169 | level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | |
170 | OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); | |
670c104a TL |
171 | else if (cpu_is_omap15xx()) |
172 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | | |
173 | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); | |
174 | else if (cpu_is_omap16xx()) | |
175 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | | |
176 | OMAP_IRQ_BIT(INT_1610_IH2_IRQ); | |
177 | ||
178 | omap_writel(~level1_wake, OMAP_IH1_MIR); | |
179 | ||
4b9100dd | 180 | if (cpu_is_omap7xx()) { |
670c104a | 181 | omap_writel(~level2_wake, OMAP_IH2_0_MIR); |
372b1c32 AB |
182 | omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | |
183 | OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), | |
670c104a TL |
184 | OMAP_IH2_1_MIR); |
185 | } else if (cpu_is_omap15xx()) { | |
186 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); | |
187 | omap_writel(~level2_wake, OMAP_IH2_MIR); | |
188 | } else if (cpu_is_omap16xx()) { | |
189 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); | |
190 | omap_writel(~level2_wake, OMAP_IH2_0_MIR); | |
191 | ||
192 | /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ | |
193 | omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), | |
194 | OMAP_IH2_1_MIR); | |
195 | omap_writel(~0x0, OMAP_IH2_2_MIR); | |
196 | omap_writel(~0x0, OMAP_IH2_3_MIR); | |
197 | } | |
198 | ||
199 | /* New IRQ agreement, recalculate in cascade order */ | |
200 | omap_writel(1, OMAP_IH2_CONTROL); | |
201 | omap_writel(1, OMAP_IH1_CONTROL); | |
202 | } | |
203 | ||
204 | #define EN_DSPCK 13 /* ARM_CKCTL */ | |
205 | #define EN_APICK 6 /* ARM_IDLECT2 */ | |
206 | #define DSP_EN 1 /* ARM_RSTCT1 */ | |
207 | ||
c912f7e1 | 208 | void omap1_pm_suspend(void) |
670c104a TL |
209 | { |
210 | unsigned long arg0 = 0, arg1 = 0; | |
211 | ||
84a34344 LL |
212 | printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n", |
213 | omap_rev()); | |
670c104a TL |
214 | |
215 | omap_serial_wake_trigger(1); | |
216 | ||
ef557d76 AZ |
217 | if (!cpu_is_omap15xx()) |
218 | omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); | |
670c104a TL |
219 | |
220 | /* | |
221 | * Step 1: turn off interrupts (FIXME: NOTE: already disabled) | |
222 | */ | |
223 | ||
224 | local_irq_disable(); | |
225 | local_fiq_disable(); | |
226 | ||
227 | /* | |
228 | * Step 2: save registers | |
229 | * | |
230 | * The omap is a strange/beautiful device. The caches, memory | |
231 | * and register state are preserved across power saves. | |
232 | * We have to save and restore very little register state to | |
233 | * idle the omap. | |
234 | * | |
235 | * Save interrupt, MPUI, ARM and UPLD control registers. | |
236 | */ | |
237 | ||
4b9100dd | 238 | if (cpu_is_omap7xx()) { |
7c006926 AB |
239 | MPUI7XX_SAVE(OMAP_IH1_MIR); |
240 | MPUI7XX_SAVE(OMAP_IH2_0_MIR); | |
241 | MPUI7XX_SAVE(OMAP_IH2_1_MIR); | |
242 | MPUI7XX_SAVE(MPUI_CTRL); | |
243 | MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); | |
244 | MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); | |
245 | MPUI7XX_SAVE(EMIFS_CONFIG); | |
246 | MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); | |
670c104a TL |
247 | |
248 | } else if (cpu_is_omap15xx()) { | |
249 | MPUI1510_SAVE(OMAP_IH1_MIR); | |
250 | MPUI1510_SAVE(OMAP_IH2_MIR); | |
251 | MPUI1510_SAVE(MPUI_CTRL); | |
252 | MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); | |
253 | MPUI1510_SAVE(MPUI_DSP_API_CONFIG); | |
254 | MPUI1510_SAVE(EMIFS_CONFIG); | |
255 | MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); | |
256 | } else if (cpu_is_omap16xx()) { | |
257 | MPUI1610_SAVE(OMAP_IH1_MIR); | |
258 | MPUI1610_SAVE(OMAP_IH2_0_MIR); | |
259 | MPUI1610_SAVE(OMAP_IH2_1_MIR); | |
260 | MPUI1610_SAVE(OMAP_IH2_2_MIR); | |
261 | MPUI1610_SAVE(OMAP_IH2_3_MIR); | |
262 | MPUI1610_SAVE(MPUI_CTRL); | |
263 | MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); | |
264 | MPUI1610_SAVE(MPUI_DSP_API_CONFIG); | |
265 | MPUI1610_SAVE(EMIFS_CONFIG); | |
266 | MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); | |
267 | } | |
268 | ||
269 | ARM_SAVE(ARM_CKCTL); | |
270 | ARM_SAVE(ARM_IDLECT1); | |
271 | ARM_SAVE(ARM_IDLECT2); | |
272 | if (!(cpu_is_omap15xx())) | |
273 | ARM_SAVE(ARM_IDLECT3); | |
274 | ARM_SAVE(ARM_EWUPCT); | |
275 | ARM_SAVE(ARM_RSTCT1); | |
276 | ARM_SAVE(ARM_RSTCT2); | |
277 | ARM_SAVE(ARM_SYSST); | |
278 | ULPD_SAVE(ULPD_CLOCK_CTRL); | |
279 | ULPD_SAVE(ULPD_STATUS_REQ); | |
280 | ||
281 | /* (Step 3 removed - we now allow deep sleep by default) */ | |
282 | ||
283 | /* | |
284 | * Step 4: OMAP DSP Shutdown | |
285 | */ | |
286 | ||
287 | /* stop DSP */ | |
288 | omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); | |
289 | ||
495f71db | 290 | /* shut down dsp_ck */ |
4b9100dd | 291 | if (!cpu_is_omap7xx()) |
495f71db | 292 | omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); |
670c104a TL |
293 | |
294 | /* temporarily enabling api_ck to access DSP registers */ | |
295 | omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); | |
296 | ||
297 | /* save DSP registers */ | |
298 | DSP_SAVE(DSP_IDLECT2); | |
299 | ||
300 | /* Stop all DSP domain clocks */ | |
301 | __raw_writew(0, DSP_IDLECT2); | |
302 | ||
303 | /* | |
304 | * Step 5: Wakeup Event Setup | |
305 | */ | |
306 | ||
307 | omap_pm_wakeup_setup(); | |
308 | ||
309 | /* | |
310 | * Step 6: ARM and Traffic controller shutdown | |
311 | */ | |
312 | ||
313 | /* disable ARM watchdog */ | |
314 | omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); | |
315 | omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); | |
316 | ||
317 | /* | |
318 | * Step 6b: ARM and Traffic controller shutdown | |
319 | * | |
320 | * Step 6 continues here. Prepare jump to power management | |
321 | * assembly code in internal SRAM. | |
322 | * | |
323 | * Since the omap_cpu_suspend routine has been copied to | |
324 | * SRAM, we'll do an indirect procedure call to it and pass the | |
325 | * contents of arm_idlect1 and arm_idlect2 so it can restore | |
326 | * them when it wakes up and it will return. | |
327 | */ | |
328 | ||
329 | arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; | |
330 | arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; | |
331 | ||
332 | /* | |
333 | * Step 6c: ARM and Traffic controller shutdown | |
334 | * | |
335 | * Jump to assembly code. The processor will stay there | |
336 | * until wake up. | |
337 | */ | |
d30c7369 | 338 | omap_sram_suspend(arg0, arg1); |
670c104a TL |
339 | |
340 | /* | |
341 | * If we are here, processor is woken up! | |
342 | */ | |
343 | ||
344 | /* | |
345 | * Restore DSP clocks | |
346 | */ | |
347 | ||
348 | /* again temporarily enabling api_ck to access DSP registers */ | |
349 | omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); | |
350 | ||
351 | /* Restore DSP domain clocks */ | |
352 | DSP_RESTORE(DSP_IDLECT2); | |
353 | ||
354 | /* | |
355 | * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did | |
356 | */ | |
357 | ||
358 | if (!(cpu_is_omap15xx())) | |
359 | ARM_RESTORE(ARM_IDLECT3); | |
360 | ARM_RESTORE(ARM_CKCTL); | |
361 | ARM_RESTORE(ARM_EWUPCT); | |
362 | ARM_RESTORE(ARM_RSTCT1); | |
363 | ARM_RESTORE(ARM_RSTCT2); | |
364 | ARM_RESTORE(ARM_SYSST); | |
365 | ULPD_RESTORE(ULPD_CLOCK_CTRL); | |
366 | ULPD_RESTORE(ULPD_STATUS_REQ); | |
367 | ||
4b9100dd | 368 | if (cpu_is_omap7xx()) { |
7c006926 AB |
369 | MPUI7XX_RESTORE(EMIFS_CONFIG); |
370 | MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); | |
371 | MPUI7XX_RESTORE(OMAP_IH1_MIR); | |
372 | MPUI7XX_RESTORE(OMAP_IH2_0_MIR); | |
373 | MPUI7XX_RESTORE(OMAP_IH2_1_MIR); | |
670c104a TL |
374 | } else if (cpu_is_omap15xx()) { |
375 | MPUI1510_RESTORE(MPUI_CTRL); | |
376 | MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); | |
377 | MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); | |
378 | MPUI1510_RESTORE(EMIFS_CONFIG); | |
379 | MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); | |
380 | MPUI1510_RESTORE(OMAP_IH1_MIR); | |
381 | MPUI1510_RESTORE(OMAP_IH2_MIR); | |
382 | } else if (cpu_is_omap16xx()) { | |
383 | MPUI1610_RESTORE(MPUI_CTRL); | |
384 | MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); | |
385 | MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); | |
386 | MPUI1610_RESTORE(EMIFS_CONFIG); | |
387 | MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); | |
388 | ||
389 | MPUI1610_RESTORE(OMAP_IH1_MIR); | |
390 | MPUI1610_RESTORE(OMAP_IH2_0_MIR); | |
391 | MPUI1610_RESTORE(OMAP_IH2_1_MIR); | |
392 | MPUI1610_RESTORE(OMAP_IH2_2_MIR); | |
393 | MPUI1610_RESTORE(OMAP_IH2_3_MIR); | |
394 | } | |
395 | ||
ef557d76 AZ |
396 | if (!cpu_is_omap15xx()) |
397 | omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); | |
670c104a TL |
398 | |
399 | /* | |
6cbdc8c5 | 400 | * Re-enable interrupts |
670c104a TL |
401 | */ |
402 | ||
403 | local_irq_enable(); | |
404 | local_fiq_enable(); | |
405 | ||
406 | omap_serial_wake_trigger(0); | |
407 | ||
84a34344 LL |
408 | printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n", |
409 | omap_rev()); | |
670c104a TL |
410 | } |
411 | ||
f9368c18 | 412 | #ifdef CONFIG_DEBUG_FS |
670c104a TL |
413 | /* |
414 | * Read system PM registers for debugging | |
415 | */ | |
f9368c18 | 416 | static int omap_pm_debug_show(struct seq_file *m, void *v) |
670c104a | 417 | { |
670c104a TL |
418 | ARM_SAVE(ARM_CKCTL); |
419 | ARM_SAVE(ARM_IDLECT1); | |
420 | ARM_SAVE(ARM_IDLECT2); | |
421 | if (!(cpu_is_omap15xx())) | |
422 | ARM_SAVE(ARM_IDLECT3); | |
423 | ARM_SAVE(ARM_EWUPCT); | |
424 | ARM_SAVE(ARM_RSTCT1); | |
425 | ARM_SAVE(ARM_RSTCT2); | |
426 | ARM_SAVE(ARM_SYSST); | |
427 | ||
428 | ULPD_SAVE(ULPD_IT_STATUS); | |
429 | ULPD_SAVE(ULPD_CLOCK_CTRL); | |
430 | ULPD_SAVE(ULPD_SOFT_REQ); | |
431 | ULPD_SAVE(ULPD_STATUS_REQ); | |
432 | ULPD_SAVE(ULPD_DPLL_CTRL); | |
433 | ULPD_SAVE(ULPD_POWER_CTRL); | |
434 | ||
4b9100dd | 435 | if (cpu_is_omap7xx()) { |
7c006926 AB |
436 | MPUI7XX_SAVE(MPUI_CTRL); |
437 | MPUI7XX_SAVE(MPUI_DSP_STATUS); | |
438 | MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); | |
439 | MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); | |
440 | MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); | |
441 | MPUI7XX_SAVE(EMIFS_CONFIG); | |
670c104a TL |
442 | } else if (cpu_is_omap15xx()) { |
443 | MPUI1510_SAVE(MPUI_CTRL); | |
444 | MPUI1510_SAVE(MPUI_DSP_STATUS); | |
445 | MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); | |
446 | MPUI1510_SAVE(MPUI_DSP_API_CONFIG); | |
447 | MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); | |
448 | MPUI1510_SAVE(EMIFS_CONFIG); | |
449 | } else if (cpu_is_omap16xx()) { | |
450 | MPUI1610_SAVE(MPUI_CTRL); | |
451 | MPUI1610_SAVE(MPUI_DSP_STATUS); | |
452 | MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); | |
453 | MPUI1610_SAVE(MPUI_DSP_API_CONFIG); | |
454 | MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); | |
455 | MPUI1610_SAVE(EMIFS_CONFIG); | |
456 | } | |
457 | ||
f9368c18 | 458 | seq_printf(m, |
670c104a TL |
459 | "ARM_CKCTL_REG: 0x%-8x \n" |
460 | "ARM_IDLECT1_REG: 0x%-8x \n" | |
461 | "ARM_IDLECT2_REG: 0x%-8x \n" | |
462 | "ARM_IDLECT3_REG: 0x%-8x \n" | |
463 | "ARM_EWUPCT_REG: 0x%-8x \n" | |
464 | "ARM_RSTCT1_REG: 0x%-8x \n" | |
465 | "ARM_RSTCT2_REG: 0x%-8x \n" | |
466 | "ARM_SYSST_REG: 0x%-8x \n" | |
467 | "ULPD_IT_STATUS_REG: 0x%-4x \n" | |
468 | "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" | |
469 | "ULPD_SOFT_REQ_REG: 0x%-4x \n" | |
470 | "ULPD_DPLL_CTRL_REG: 0x%-4x \n" | |
471 | "ULPD_STATUS_REQ_REG: 0x%-4x \n" | |
472 | "ULPD_POWER_CTRL_REG: 0x%-4x \n", | |
473 | ARM_SHOW(ARM_CKCTL), | |
474 | ARM_SHOW(ARM_IDLECT1), | |
475 | ARM_SHOW(ARM_IDLECT2), | |
476 | ARM_SHOW(ARM_IDLECT3), | |
477 | ARM_SHOW(ARM_EWUPCT), | |
478 | ARM_SHOW(ARM_RSTCT1), | |
479 | ARM_SHOW(ARM_RSTCT2), | |
480 | ARM_SHOW(ARM_SYSST), | |
481 | ULPD_SHOW(ULPD_IT_STATUS), | |
482 | ULPD_SHOW(ULPD_CLOCK_CTRL), | |
483 | ULPD_SHOW(ULPD_SOFT_REQ), | |
484 | ULPD_SHOW(ULPD_DPLL_CTRL), | |
485 | ULPD_SHOW(ULPD_STATUS_REQ), | |
486 | ULPD_SHOW(ULPD_POWER_CTRL)); | |
487 | ||
f9368c18 TL |
488 | if (cpu_is_omap7xx()) { |
489 | seq_printf(m, | |
7c006926 AB |
490 | "MPUI7XX_CTRL_REG 0x%-8x \n" |
491 | "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" | |
492 | "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" | |
493 | "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" | |
494 | "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" | |
495 | "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", | |
496 | MPUI7XX_SHOW(MPUI_CTRL), | |
497 | MPUI7XX_SHOW(MPUI_DSP_STATUS), | |
498 | MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), | |
499 | MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), | |
500 | MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), | |
501 | MPUI7XX_SHOW(EMIFS_CONFIG)); | |
f9368c18 TL |
502 | } else if (cpu_is_omap15xx()) { |
503 | seq_printf(m, | |
670c104a TL |
504 | "MPUI1510_CTRL_REG 0x%-8x \n" |
505 | "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" | |
506 | "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" | |
507 | "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" | |
508 | "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" | |
509 | "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", | |
510 | MPUI1510_SHOW(MPUI_CTRL), | |
511 | MPUI1510_SHOW(MPUI_DSP_STATUS), | |
512 | MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), | |
513 | MPUI1510_SHOW(MPUI_DSP_API_CONFIG), | |
514 | MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), | |
515 | MPUI1510_SHOW(EMIFS_CONFIG)); | |
f9368c18 TL |
516 | } else if (cpu_is_omap16xx()) { |
517 | seq_printf(m, | |
670c104a TL |
518 | "MPUI1610_CTRL_REG 0x%-8x \n" |
519 | "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" | |
520 | "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" | |
521 | "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" | |
522 | "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" | |
523 | "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", | |
524 | MPUI1610_SHOW(MPUI_CTRL), | |
525 | MPUI1610_SHOW(MPUI_DSP_STATUS), | |
526 | MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), | |
527 | MPUI1610_SHOW(MPUI_DSP_API_CONFIG), | |
528 | MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), | |
529 | MPUI1610_SHOW(EMIFS_CONFIG)); | |
670c104a | 530 | } |
670c104a | 531 | |
f9368c18 TL |
532 | return 0; |
533 | } | |
534 | ||
535 | static int omap_pm_debug_open(struct inode *inode, struct file *file) | |
536 | { | |
537 | return single_open(file, omap_pm_debug_show, | |
538 | &inode->i_private); | |
670c104a TL |
539 | } |
540 | ||
f9368c18 TL |
541 | static const struct file_operations omap_pm_debug_fops = { |
542 | .open = omap_pm_debug_open, | |
543 | .read = seq_read, | |
544 | .llseek = seq_lseek, | |
b11ac20e | 545 | .release = single_release, |
f9368c18 TL |
546 | }; |
547 | ||
548 | static void omap_pm_init_debugfs(void) | |
670c104a | 549 | { |
f9368c18 TL |
550 | struct dentry *d; |
551 | ||
552 | d = debugfs_create_dir("pm_debug", NULL); | |
553 | if (!d) | |
554 | return; | |
555 | ||
556 | (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, | |
557 | d, NULL, &omap_pm_debug_fops); | |
670c104a TL |
558 | } |
559 | ||
f9368c18 | 560 | #endif /* CONFIG_DEBUG_FS */ |
670c104a | 561 | |
670c104a TL |
562 | /* |
563 | * omap_pm_prepare - Do preliminary suspend work. | |
670c104a TL |
564 | * |
565 | */ | |
e6c5eb95 | 566 | static int omap_pm_prepare(void) |
670c104a | 567 | { |
670c104a | 568 | /* We cannot sleep in idle until we have resumed */ |
f7b861b7 | 569 | cpu_idle_poll_ctrl(true); |
e6c5eb95 | 570 | return 0; |
670c104a TL |
571 | } |
572 | ||
573 | ||
574 | /* | |
575 | * omap_pm_enter - Actually enter a sleep state. | |
576 | * @state: State we're entering. | |
577 | * | |
578 | */ | |
579 | ||
580 | static int omap_pm_enter(suspend_state_t state) | |
581 | { | |
582 | switch (state) | |
583 | { | |
584 | case PM_SUSPEND_STANDBY: | |
585 | case PM_SUSPEND_MEM: | |
c912f7e1 | 586 | omap1_pm_suspend(); |
670c104a | 587 | break; |
670c104a TL |
588 | default: |
589 | return -EINVAL; | |
590 | } | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | ||
596 | /** | |
597 | * omap_pm_finish - Finish up suspend sequence. | |
670c104a TL |
598 | * |
599 | * This is called after we wake back up (or if entering the sleep state | |
600 | * failed). | |
601 | */ | |
602 | ||
e6c5eb95 | 603 | static void omap_pm_finish(void) |
670c104a | 604 | { |
f7b861b7 | 605 | cpu_idle_poll_ctrl(false); |
670c104a TL |
606 | } |
607 | ||
608 | ||
e8f2af17 | 609 | static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) |
670c104a TL |
610 | { |
611 | return IRQ_HANDLED; | |
612 | } | |
613 | ||
614 | static struct irqaction omap_wakeup_irq = { | |
615 | .name = "peripheral wakeup", | |
670c104a TL |
616 | .handler = omap_wakeup_interrupt |
617 | }; | |
618 | ||
619 | ||
620 | ||
2f55ac07 | 621 | static const struct platform_suspend_ops omap_pm_ops = { |
670c104a TL |
622 | .prepare = omap_pm_prepare, |
623 | .enter = omap_pm_enter, | |
624 | .finish = omap_pm_finish, | |
26398a70 | 625 | .valid = suspend_valid_only_mem, |
670c104a TL |
626 | }; |
627 | ||
628 | static int __init omap_pm_init(void) | |
629 | { | |
7239d309 | 630 | int error = 0; |
2f5c4b6f | 631 | |
7f9187c2 TL |
632 | if (!cpu_class_is_omap1()) |
633 | return -ENODEV; | |
634 | ||
7239d309 PW |
635 | pr_info("Power Management for TI OMAP.\n"); |
636 | ||
637 | if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER)) | |
638 | pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n"); | |
639 | ||
640 | if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER)) | |
641 | pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n"); | |
642 | ||
643 | if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) && | |
644 | IS_ENABLED(CONFIG_OMAP_DM_TIMER)) { | |
645 | /* OMAP16xx only */ | |
646 | pr_info("OMAP1 PM: sleep states in idle enabled\n"); | |
647 | enable_dyn_sleep = 1; | |
648 | } | |
670c104a TL |
649 | |
650 | /* | |
651 | * We copy the assembler sleep/wakeup routines to SRAM. | |
652 | * These routines need to be in SRAM as that's the only | |
653 | * memory the MPU can see when it wakes up. | |
654 | */ | |
4b9100dd | 655 | if (cpu_is_omap7xx()) { |
7c006926 AB |
656 | omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, |
657 | omap7xx_cpu_suspend_sz); | |
670c104a | 658 | } else if (cpu_is_omap15xx()) { |
670c104a TL |
659 | omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, |
660 | omap1510_cpu_suspend_sz); | |
661 | } else if (cpu_is_omap16xx()) { | |
670c104a TL |
662 | omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, |
663 | omap1610_cpu_suspend_sz); | |
664 | } | |
665 | ||
feb72f3b | 666 | if (omap_sram_suspend == NULL) { |
670c104a TL |
667 | printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); |
668 | return -ENODEV; | |
669 | } | |
670 | ||
0bcd24b0 | 671 | arm_pm_idle = omap1_pm_idle; |
670c104a | 672 | |
4b9100dd | 673 | if (cpu_is_omap7xx()) |
372b1c32 | 674 | setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq); |
670c104a TL |
675 | else if (cpu_is_omap16xx()) |
676 | setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); | |
677 | ||
678 | /* Program new power ramp-up time | |
679 | * (0 for most boards since we don't lower voltage when in deep sleep) | |
680 | */ | |
681 | omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); | |
682 | ||
683 | /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ | |
684 | omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); | |
685 | ||
686 | /* Configure IDLECT3 */ | |
4b9100dd | 687 | if (cpu_is_omap7xx()) |
7c006926 | 688 | omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); |
670c104a TL |
689 | else if (cpu_is_omap16xx()) |
690 | omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); | |
691 | ||
26398a70 | 692 | suspend_set_ops(&omap_pm_ops); |
670c104a | 693 | |
f9368c18 TL |
694 | #ifdef CONFIG_DEBUG_FS |
695 | omap_pm_init_debugfs(); | |
670c104a TL |
696 | #endif |
697 | ||
02bad5f9 | 698 | error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); |
2f5c4b6f | 699 | if (error) |
851324c6 | 700 | printk(KERN_ERR "sysfs_create_file failed: %d\n", error); |
670c104a TL |
701 | |
702 | if (cpu_is_omap16xx()) { | |
703 | /* configure LOW_PWR pin */ | |
704 | omap_cfg_reg(T20_1610_LOW_PWR); | |
705 | } | |
706 | ||
7239d309 | 707 | return error; |
670c104a TL |
708 | } |
709 | __initcall(omap_pm_init); |