[deliverable/linux.git] / arch / arm / mach-omap1 / serial.c

/*
 * linux/arch/arm/mach-omap1/serial.c
 *
 * OMAP1 CPU identification code
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>

#include <asm/io.h>
#include <asm/mach-types.h>

#include <asm/arch/board.h>
#include <asm/arch/mux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/fpga.h>
#ifdef CONFIG_PM
#include <asm/arch/pm.h>
#endif

static struct clk * uart1_ck;
static struct clk * uart2_ck;
static struct clk * uart3_ck;

static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
					  int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
				    int value)
{
	offset <<= p->regshift;
	__raw_writeb(value, p->membase + offset);
}

/*
 * Internal UARTs need to be initialized for the 8250 autoconfig to work
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */
static void __init omap_serial_reset(struct plat_serial8250_port *p)
{
	omap_serial_outp(p, UART_OMAP_MDR1, 0x07);	/* disable UART */
	omap_serial_outp(p, UART_OMAP_SCR, 0x08);	/* TX watermark */
	omap_serial_outp(p, UART_OMAP_MDR1, 0x00);	/* enable UART */

	if (!cpu_is_omap1510()) {
		omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
		while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
	}
}

static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase	= (char*)IO_ADDRESS(OMAP_UART1_BASE),
		.mapbase	= (unsigned long)OMAP_UART1_BASE,
		.irq		= INT_UART1,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{
		.membase	= (char*)IO_ADDRESS(OMAP_UART2_BASE),
		.mapbase	= (unsigned long)OMAP_UART2_BASE,
		.irq		= INT_UART2,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{
		.membase	= (char*)IO_ADDRESS(OMAP_UART3_BASE),
		.mapbase	= (unsigned long)OMAP_UART3_BASE,
		.irq		= INT_UART3,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP16XX_BASE_BAUD * 16,
	},
	{ },
};

static struct platform_device serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= serial_platform_data,
	},
};

/*
 * Note that on Innovator-1510 UART2 pins conflict with USB2.
 * By default UART2 does not work on Innovator-1510 if you have
 * USB OHCI enabled. To use UART2, you must disable USB2 first.
 */
void __init omap_serial_init(void)
{
	int i;
	const struct omap_uart_config *info;

	if (cpu_is_omap730()) {
		serial_platform_data[0].regshift = 0;
		serial_platform_data[1].regshift = 0;
		serial_platform_data[0].irq = INT_730_UART_MODEM_1;
		serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
	}

	if (cpu_is_omap1510()) {
		serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
		serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
		serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
	}

	info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
	if (info == NULL)
		return;

	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
		unsigned char reg;

		if (!((1 << i) & info->enabled_uarts)) {
			serial_platform_data[i].membase = NULL;
			serial_platform_data[i].mapbase = 0;
			continue;
		}

		switch (i) {
		case 0:
			uart1_ck = clk_get(NULL, "uart1_ck");
			if (IS_ERR(uart1_ck))
				printk("Could not get uart1_ck\n");
			else {
				clk_enable(uart1_ck);
				if (cpu_is_omap1510())
					clk_set_rate(uart1_ck, 12000000);
			}
			if (cpu_is_omap1510()) {
				omap_cfg_reg(UART1_TX);
				omap_cfg_reg(UART1_RTS);
				if (machine_is_omap_innovator()) {
					reg = fpga_read(OMAP1510_FPGA_POWER);
					reg |= OMAP1510_FPGA_PCR_COM1_EN;
					fpga_write(reg, OMAP1510_FPGA_POWER);
					udelay(10);
				}
			}
			break;
		case 1:
			uart2_ck = clk_get(NULL, "uart2_ck");
			if (IS_ERR(uart2_ck))
				printk("Could not get uart2_ck\n");
			else {
				clk_enable(uart2_ck);
				if (cpu_is_omap1510())
					clk_set_rate(uart2_ck, 12000000);
				else
					clk_set_rate(uart2_ck, 48000000);
			}
			if (cpu_is_omap1510()) {
				omap_cfg_reg(UART2_TX);
				omap_cfg_reg(UART2_RTS);
				if (machine_is_omap_innovator()) {
					reg = fpga_read(OMAP1510_FPGA_POWER);
					reg |= OMAP1510_FPGA_PCR_COM2_EN;
					fpga_write(reg, OMAP1510_FPGA_POWER);
					udelay(10);
				}
			}
			break;
		case 2:
			uart3_ck = clk_get(NULL, "uart3_ck");
			if (IS_ERR(uart3_ck))
				printk("Could not get uart3_ck\n");
			else {
				clk_enable(uart3_ck);
				if (cpu_is_omap1510())
					clk_set_rate(uart3_ck, 12000000);
			}
			if (cpu_is_omap1510()) {
				omap_cfg_reg(UART3_TX);
				omap_cfg_reg(UART3_RX);
			}
			break;
		}
		omap_serial_reset(&serial_platform_data[i]);
	}
}

#ifdef CONFIG_OMAP_SERIAL_WAKE

static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
{
	/* Need to do something with serial port right after wake-up? */
	return IRQ_HANDLED;
}

/*
 * Reroutes serial RX lines to GPIO lines for the duration of
 * sleep to allow waking up the device from serial port even
 * in deep sleep.
 */
void omap_serial_wake_trigger(int enable)
{
	if (!cpu_is_omap16xx())
		return;

	if (uart1_ck != NULL) {
		if (enable)
			omap_cfg_reg(V14_16XX_GPIO37);
		else
			omap_cfg_reg(V14_16XX_UART1_RX);
	}
	if (uart2_ck != NULL) {
		if (enable)
			omap_cfg_reg(R9_16XX_GPIO18);
		else
			omap_cfg_reg(R9_16XX_UART2_RX);
	}
	if (uart3_ck != NULL) {
		if (enable)
			omap_cfg_reg(L14_16XX_GPIO49);
		else
			omap_cfg_reg(L14_16XX_UART3_RX);
	}
}

static void __init omap_serial_set_port_wakeup(int gpio_nr)
{
	int ret;

	ret = omap_request_gpio(gpio_nr);
	if (ret < 0) {
		printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
		       gpio_nr);
		return;
	}
	omap_set_gpio_direction(gpio_nr, 1);
	ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt,
			  IRQF_TRIGGER_RISING, "serial wakeup", NULL);
	if (ret) {
		omap_free_gpio(gpio_nr);
		printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
		       gpio_nr);
		return;
	}
	enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr));
}

static int __init omap_serial_wakeup_init(void)
{
	if (!cpu_is_omap16xx())
		return 0;

	if (uart1_ck != NULL)
		omap_serial_set_port_wakeup(37);
	if (uart2_ck != NULL)
		omap_serial_set_port_wakeup(18);
	if (uart3_ck != NULL)
		omap_serial_set_port_wakeup(49);

	return 0;
}
late_initcall(omap_serial_wakeup_init);

#endif	/* CONFIG_OMAP_SERIAL_WAKE */

static int __init omap_init(void)
{
	return platform_device_register(&serial_device);
}
arch_initcall(omap_init);
Commit	Line	Data
f577ffd7	1	/*
f30c2269	2	* linux/arch/arm/mach-omap1/serial.c
f577ffd7 TL	3	*
	4	* OMAP1 CPU identification code
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
f577ffd7 TL	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
d533c128	14	#include <linux/irq.h>
f577ffd7 TL	15	#include <linux/delay.h>
	16	#include <linux/serial.h>
	17	#include <linux/tty.h>
	18	#include <linux/serial_8250.h>
	19	#include <linux/serial_reg.h>
f8ce2547	20	#include <linux/clk.h>
f577ffd7 TL	21
	22	#include <asm/io.h>
	23	#include <asm/mach-types.h>
f577ffd7 TL	24
	25	#include <asm/arch/board.h>
	26	#include <asm/arch/mux.h>
7c38cf02	27	#include <asm/arch/gpio.h>
f577ffd7	28	#include <asm/arch/fpga.h>
7c38cf02 TL	29	#ifdef CONFIG_PM
	30	#include <asm/arch/pm.h>
	31	#endif
f577ffd7	32
120db2cb TL	33	static struct clk * uart1_ck;
	34	static struct clk * uart2_ck;
	35	static struct clk * uart3_ck;
f577ffd7 TL	36
	37	static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
	38	int offset)
	39	{
	40	offset <<= up->regshift;
	41	return (unsigned int)__raw_readb(up->membase + offset);
	42	}
	43
	44	static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
	45	int value)
	46	{
	47	offset <<= p->regshift;
	48	__raw_writeb(value, p->membase + offset);
	49	}
	50
	51	/*
	52	* Internal UARTs need to be initialized for the 8250 autoconfig to work
	53	* properly. Note that the TX watermark initialization may not be needed
	54	* once the 8250.c watermark handling code is merged.
	55	*/
	56	static void __init omap_serial_reset(struct plat_serial8250_port *p)
	57	{
	58	omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */
	59	omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */
	60	omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */
	61
	62	if (!cpu_is_omap1510()) {
	63	omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
	64	while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
	65	}
	66	}
	67
	68	static struct plat_serial8250_port serial_platform_data[] = {
	69	{
	70	.membase = (char*)IO_ADDRESS(OMAP_UART1_BASE),
	71	.mapbase = (unsigned long)OMAP_UART1_BASE,
	72	.irq = INT_UART1,
	73	.flags = UPF_BOOT_AUTOCONF,
	74	.iotype = UPIO_MEM,
	75	.regshift = 2,
	76	.uartclk = OMAP16XX_BASE_BAUD * 16,
	77	},
	78	{
	79	.membase = (char*)IO_ADDRESS(OMAP_UART2_BASE),
	80	.mapbase = (unsigned long)OMAP_UART2_BASE,
	81	.irq = INT_UART2,
	82	.flags = UPF_BOOT_AUTOCONF,
	83	.iotype = UPIO_MEM,
	84	.regshift = 2,
	85	.uartclk = OMAP16XX_BASE_BAUD * 16,
	86	},
	87	{
	88	.membase = (char*)IO_ADDRESS(OMAP_UART3_BASE),
	89	.mapbase = (unsigned long)OMAP_UART3_BASE,
	90	.irq = INT_UART3,
	91	.flags = UPF_BOOT_AUTOCONF,
	92	.iotype = UPIO_MEM,
	93	.regshift = 2,
	94	.uartclk = OMAP16XX_BASE_BAUD * 16,
	95	},
	96	{ },
	97	};
	98
	99	static struct platform_device serial_device = {
100	.name = "serial8250",
6df29deb	101	.id = PLAT8250_DEV_PLATFORM,
f577ffd7 TL	102	.dev = {
	103	.platform_data = serial_platform_data,
	104	},
	105	};
	106
	107	/*
	108	* Note that on Innovator-1510 UART2 pins conflict with USB2.
	109	* By default UART2 does not work on Innovator-1510 if you have
	110	* USB OHCI enabled. To use UART2, you must disable USB2 first.
	111	*/
3179a019	112	void __init omap_serial_init(void)
f577ffd7 TL	113	{
f577ffd7 TL	114	int i;
3179a019	115	const struct omap_uart_config *info;
f577ffd7 TL	116
	117	if (cpu_is_omap730()) {
	118	serial_platform_data[0].regshift = 0;
	119	serial_platform_data[1].regshift = 0;
	120	serial_platform_data[0].irq = INT_730_UART_MODEM_1;
	121	serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
	122	}
	123
	124	if (cpu_is_omap1510()) {
	125	serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
	126	serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
	127	serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
	128	}
	129
3179a019 TL	130	info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
	131	if (info == NULL)
	132	return;
	133
f577ffd7 TL	134	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
	135	unsigned char reg;
	136
3179a019	137	if (!((1 << i) & info->enabled_uarts)) {
f577ffd7 TL	138	serial_platform_data[i].membase = NULL;
	139	serial_platform_data[i].mapbase = 0;
	140	continue;
	141	}
	142
	143	switch (i) {
	144	case 0:
	145	uart1_ck = clk_get(NULL, "uart1_ck");
	146	if (IS_ERR(uart1_ck))
	147	printk("Could not get uart1_ck\n");
	148	else {
30ff720b	149	clk_enable(uart1_ck);
f577ffd7 TL	150	if (cpu_is_omap1510())
	151	clk_set_rate(uart1_ck, 12000000);
	152	}
	153	if (cpu_is_omap1510()) {
	154	omap_cfg_reg(UART1_TX);
	155	omap_cfg_reg(UART1_RTS);
	156	if (machine_is_omap_innovator()) {
	157	reg = fpga_read(OMAP1510_FPGA_POWER);
	158	reg \|= OMAP1510_FPGA_PCR_COM1_EN;
	159	fpga_write(reg, OMAP1510_FPGA_POWER);
	160	udelay(10);
	161	}
	162	}
	163	break;
	164	case 1:
	165	uart2_ck = clk_get(NULL, "uart2_ck");
	166	if (IS_ERR(uart2_ck))
	167	printk("Could not get uart2_ck\n");
	168	else {
30ff720b	169	clk_enable(uart2_ck);
f577ffd7 TL	170	if (cpu_is_omap1510())
	171	clk_set_rate(uart2_ck, 12000000);
	172	else
	173	clk_set_rate(uart2_ck, 48000000);
	174	}
	175	if (cpu_is_omap1510()) {
	176	omap_cfg_reg(UART2_TX);
	177	omap_cfg_reg(UART2_RTS);
	178	if (machine_is_omap_innovator()) {
	179	reg = fpga_read(OMAP1510_FPGA_POWER);
	180	reg \|= OMAP1510_FPGA_PCR_COM2_EN;
	181	fpga_write(reg, OMAP1510_FPGA_POWER);
	182	udelay(10);
	183	}
	184	}
	185	break;
	186	case 2:
	187	uart3_ck = clk_get(NULL, "uart3_ck");
	188	if (IS_ERR(uart3_ck))
	189	printk("Could not get uart3_ck\n");
	190	else {
30ff720b	191	clk_enable(uart3_ck);
f577ffd7 TL	192	if (cpu_is_omap1510())
	193	clk_set_rate(uart3_ck, 12000000);
	194	}
	195	if (cpu_is_omap1510()) {
	196	omap_cfg_reg(UART3_TX);
	197	omap_cfg_reg(UART3_RX);
	198	}
	199	break;
	200	}
	201	omap_serial_reset(&serial_platform_data[i]);
	202	}
	203	}
	204
7c38cf02 TL	205	#ifdef CONFIG_OMAP_SERIAL_WAKE
7c38cf02 TL	206
0cd61b68	207	static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
7c38cf02 TL	208	{
	209	/* Need to do something with serial port right after wake-up? */
	210	return IRQ_HANDLED;
	211	}
	212
	213	/*
	214	* Reroutes serial RX lines to GPIO lines for the duration of
	215	* sleep to allow waking up the device from serial port even
	216	* in deep sleep.
	217	*/
	218	void omap_serial_wake_trigger(int enable)
	219	{
	220	if (!cpu_is_omap16xx())
	221	return;
	222
	223	if (uart1_ck != NULL) {
	224	if (enable)
	225	omap_cfg_reg(V14_16XX_GPIO37);
	226	else
	227	omap_cfg_reg(V14_16XX_UART1_RX);
	228	}
	229	if (uart2_ck != NULL) {
	230	if (enable)
	231	omap_cfg_reg(R9_16XX_GPIO18);
	232	else
	233	omap_cfg_reg(R9_16XX_UART2_RX);
	234	}
	235	if (uart3_ck != NULL) {
	236	if (enable)
	237	omap_cfg_reg(L14_16XX_GPIO49);
	238	else
	239	omap_cfg_reg(L14_16XX_UART3_RX);
	240	}
	241	}
	242
	243	static void __init omap_serial_set_port_wakeup(int gpio_nr)
	244	{
	245	int ret;
	246
	247	ret = omap_request_gpio(gpio_nr);
	248	if (ret < 0) {
	249	printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
	250	gpio_nr);
	251	return;
	252	}
	253	omap_set_gpio_direction(gpio_nr, 1);
7c38cf02	254	ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt,
52e405ea	255	IRQF_TRIGGER_RISING, "serial wakeup", NULL);
7c38cf02 TL	256	if (ret) {
	257	omap_free_gpio(gpio_nr);
	258	printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
	259	gpio_nr);
	260	return;
	261	}
	262	enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr));
	263	}
	264
	265	static int __init omap_serial_wakeup_init(void)
	266	{
	267	if (!cpu_is_omap16xx())
	268	return 0;
	269
	270	if (uart1_ck != NULL)
	271	omap_serial_set_port_wakeup(37);
	272	if (uart2_ck != NULL)
	273	omap_serial_set_port_wakeup(18);
	274	if (uart3_ck != NULL)
	275	omap_serial_set_port_wakeup(49);
	276
	277	return 0;
	278	}
	279	late_initcall(omap_serial_wakeup_init);
	280
	281	#endif /* CONFIG_OMAP_SERIAL_WAKE */
	282
f577ffd7 TL	283	static int __init omap_init(void)
	284	{
	285	return platform_device_register(&serial_device);
	286	}
	287	arch_initcall(omap_init);