[deliverable/linux.git] / arch / arm / mach-omap1 / time.c

/*
 * linux/arch/arm/mach-omap1/time.c
 *
 * OMAP Timers
 *
 * Copyright (C) 2004 Nokia Corporation
 * Partial timer rewrite and additional dynamic tick timer support by
 * Tony Lindgen <tony@atomide.com> and
 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
 *
 * MPU timer code based on the older MPU timer code for OMAP
 * Copyright (C) 2000 RidgeRun, Inc.
 * Author: Greg Lonnon <glonnon@ridgerun.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>

#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/leds.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>

#include <plat/common.h>

#define OMAP_MPU_TIMER_BASE		OMAP_MPU_TIMER1_BASE
#define OMAP_MPU_TIMER_OFFSET		0x100

typedef struct {
	u32 cntl;			/* CNTL_TIMER, R/W */
	u32 load_tim;			/* LOAD_TIM,   W */
	u32 read_tim;			/* READ_TIM,   R */
} omap_mpu_timer_regs_t;

#define omap_mpu_timer_base(n)							\
((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +	\
				 (n)*OMAP_MPU_TIMER_OFFSET))

static inline unsigned long omap_mpu_timer_read(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	return timer->read_tim;
}

static inline void omap_mpu_set_autoreset(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl = timer->cntl | MPU_TIMER_AR;
}

static inline void omap_mpu_remove_autoreset(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl = timer->cntl & ~MPU_TIMER_AR;
}

static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
					int autoreset)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);

	if (autoreset) timerflags |= MPU_TIMER_AR;

	timer->cntl = MPU_TIMER_CLOCK_ENABLE;
	udelay(1);
	timer->load_tim = load_val;
        udelay(1);
	timer->cntl = timerflags;
}

static inline void omap_mpu_timer_stop(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl &= ~MPU_TIMER_ST;
}

/*
 * ---------------------------------------------------------------------------
 * MPU timer 1 ... count down to zero, interrupt, reload
 * ---------------------------------------------------------------------------
 */
static int omap_mpu_set_next_event(unsigned long cycles,
				   struct clock_event_device *evt)
{
	omap_mpu_timer_start(0, cycles, 0);
	return 0;
}

static void omap_mpu_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		omap_mpu_set_autoreset(0);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		omap_mpu_timer_stop(0);
		omap_mpu_remove_autoreset(0);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_mpu_timer1 = {
	.name		= "mpu_timer1",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_next_event	= omap_mpu_set_next_event,
	.set_mode	= omap_mpu_set_mode,
};

static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mpu_timer1;

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction omap_mpu_timer1_irq = {
	.name		= "mpu_timer1",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap_mpu_timer1_interrupt,
};

static __init void omap_init_mpu_timer(unsigned long rate)
{
	setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
	omap_mpu_timer_start(0, (rate / HZ) - 1, 1);

	clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
					    clockevent_mpu_timer1.shift);
	clockevent_mpu_timer1.max_delta_ns =
		clockevent_delta2ns(-1, &clockevent_mpu_timer1);
	clockevent_mpu_timer1.min_delta_ns =
		clockevent_delta2ns(1, &clockevent_mpu_timer1);

	clockevent_mpu_timer1.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_mpu_timer1);
}


/*
 * ---------------------------------------------------------------------------
 * MPU timer 2 ... free running 32-bit clock source and scheduler clock
 * ---------------------------------------------------------------------------
 */

static unsigned long omap_mpu_timer2_overflows;

static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
{
	omap_mpu_timer2_overflows++;
	return IRQ_HANDLED;
}

static struct irqaction omap_mpu_timer2_irq = {
	.name		= "mpu_timer2",
	.flags		= IRQF_DISABLED,
	.handler	= omap_mpu_timer2_interrupt,
};

static cycle_t mpu_read(struct clocksource *cs)
{
	return ~omap_mpu_timer_read(1);
}

static struct clocksource clocksource_mpu = {
	.name		= "mpu_timer2",
	.rating		= 300,
	.read		= mpu_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init omap_init_clocksource(unsigned long rate)
{
	static char err[] __initdata = KERN_ERR
			"%s: can't register clocksource!\n";

	setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
	omap_mpu_timer_start(1, ~0, 1);

	if (clocksource_register_hz(&clocksource_mpu, rate))
		printk(err, clocksource_mpu.name);
}

/*
 * ---------------------------------------------------------------------------
 * Timer initialization
 * ---------------------------------------------------------------------------
 */
static void __init omap_timer_init(void)
{
	struct clk	*ck_ref = clk_get(NULL, "ck_ref");
	unsigned long	rate;

	BUG_ON(IS_ERR(ck_ref));

	rate = clk_get_rate(ck_ref);
	clk_put(ck_ref);

	/* PTV = 0 */
	rate /= 2;

	omap_init_mpu_timer(rate);
	omap_init_clocksource(rate);
}

struct sys_timer omap_timer = {
	.init		= omap_timer_init,
};
Commit	Line	Data
1da177e4	1	/*
3b59b6be	2	* linux/arch/arm/mach-omap1/time.c
1da177e4 LT	3	*
	4	* OMAP Timers
	5	*
	6	* Copyright (C) 2004 Nokia Corporation
b3402cf5	7	* Partial timer rewrite and additional dynamic tick timer support by
1da177e4 LT	8	* Tony Lindgen <tony@atomide.com> and
	9	* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
	10	*
	11	* MPU timer code based on the older MPU timer code for OMAP
	12	* Copyright (C) 2000 RidgeRun, Inc.
	13	* Author: Greg Lonnon <glonnon@ridgerun.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License as published by the
	17	* Free Software Foundation; either version 2 of the License, or (at your
	18	* option) any later version.
	19	*
	20	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	21	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	22	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	23	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	24	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	25	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	26	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	29	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	30	*
	31	* You should have received a copy of the GNU General Public License along
	32	* with this program; if not, write to the Free Software Foundation, Inc.,
	33	* 675 Mass Ave, Cambridge, MA 02139, USA.
	34	*/
	35
1da177e4 LT	36	#include <linux/kernel.h>
	37	#include <linux/init.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/sched.h>
	41	#include <linux/spinlock.h>
075192ae KH	42	#include <linux/clk.h>
	43	#include <linux/err.h>
	44	#include <linux/clocksource.h>
	45	#include <linux/clockchips.h>
fced80c7	46	#include <linux/io.h>
1da177e4 LT	47
1da177e4 LT	48	#include <asm/system.h>
a09e64fb	49	#include <mach/hardware.h>
1da177e4 LT	50	#include <asm/leds.h>
	51	#include <asm/irq.h>
	52	#include <asm/mach/irq.h>
	53	#include <asm/mach/time.h>
	54
706afdda	55	#include <plat/common.h>
1da177e4	56
1da177e4 LT	57	#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
	58	#define OMAP_MPU_TIMER_OFFSET 0x100
	59
1da177e4 LT	60	typedef struct {
	61	u32 cntl; /* CNTL_TIMER, R/W */
	62	u32 load_tim; /* LOAD_TIM, W */
	63	u32 read_tim; /* READ_TIM, R */
	64	} omap_mpu_timer_regs_t;
	65
94113260 TL	66	#define omap_mpu_timer_base(n) \
94113260 TL	67	((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
1da177e4 LT	68	(n)*OMAP_MPU_TIMER_OFFSET))
	69
	70	static inline unsigned long omap_mpu_timer_read(int nr)
	71	{
	72	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	73	return timer->read_tim;
	74	}
	75
075192ae	76	static inline void omap_mpu_set_autoreset(int nr)
1da177e4 LT	77	{
	78	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	79
075192ae	80	timer->cntl = timer->cntl \| MPU_TIMER_AR;
1da177e4 LT	81	}
1da177e4 LT	82
075192ae	83	static inline void omap_mpu_remove_autoreset(int nr)
1da177e4	84	{
075192ae	85	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
1da177e4	86
075192ae	87	timer->cntl = timer->cntl & ~MPU_TIMER_AR;
1da177e4 LT	88	}
1da177e4 LT	89
075192ae KH	90	static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
	91	int autoreset)
	92	{
	93	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	94	unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE \| MPU_TIMER_ST);
	95
	96	if (autoreset) timerflags \|= MPU_TIMER_AR;
	97
	98	timer->cntl = MPU_TIMER_CLOCK_ENABLE;
	99	udelay(1);
	100	timer->load_tim = load_val;
	101	udelay(1);
	102	timer->cntl = timerflags;
	103	}
1da177e4	104
06cad098 KH	105	static inline void omap_mpu_timer_stop(int nr)
	106	{
	107	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	108
	109	timer->cntl &= ~MPU_TIMER_ST;
	110	}
	111
1da177e4	112	/*
075192ae KH	113	* ---------------------------------------------------------------------------
	114	* MPU timer 1 ... count down to zero, interrupt, reload
	115	* ---------------------------------------------------------------------------
1da177e4	116	*/
075192ae	117	static int omap_mpu_set_next_event(unsigned long cycles,
06cad098	118	struct clock_event_device *evt)
1da177e4	119	{
075192ae KH	120	omap_mpu_timer_start(0, cycles, 0);
	121	return 0;
	122	}
1da177e4	123
075192ae KH	124	static void omap_mpu_set_mode(enum clock_event_mode mode,
	125	struct clock_event_device *evt)
	126	{
	127	switch (mode) {
	128	case CLOCK_EVT_MODE_PERIODIC:
	129	omap_mpu_set_autoreset(0);
	130	break;
	131	case CLOCK_EVT_MODE_ONESHOT:
06cad098	132	omap_mpu_timer_stop(0);
075192ae KH	133	omap_mpu_remove_autoreset(0);
	134	break;
	135	case CLOCK_EVT_MODE_UNUSED:
	136	case CLOCK_EVT_MODE_SHUTDOWN:
18de5bc4	137	case CLOCK_EVT_MODE_RESUME:
075192ae KH	138	break;
075192ae KH	139	}
1da177e4 LT	140	}
1da177e4 LT	141
075192ae KH	142	static struct clock_event_device clockevent_mpu_timer1 = {
075192ae KH	143	.name = "mpu_timer1",
c6b349ed	144	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
075192ae KH	145	.shift = 32,
	146	.set_next_event = omap_mpu_set_next_event,
	147	.set_mode = omap_mpu_set_mode,
	148	};
	149
	150	static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
1da177e4	151	{
075192ae	152	struct clock_event_device *evt = &clockevent_mpu_timer1;
1da177e4	153
075192ae	154	evt->event_handler(evt);
1da177e4 LT	155
	156	return IRQ_HANDLED;
	157	}
	158
075192ae KH	159	static struct irqaction omap_mpu_timer1_irq = {
075192ae KH	160	.name = "mpu_timer1",
b30fabad	161	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
075192ae	162	.handler = omap_mpu_timer1_interrupt,
1da177e4 LT	163	};
1da177e4 LT	164
075192ae KH	165	static __init void omap_init_mpu_timer(unsigned long rate)
075192ae KH	166	{
075192ae KH	167	setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
	168	omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
	169
	170	clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
	171	clockevent_mpu_timer1.shift);
	172	clockevent_mpu_timer1.max_delta_ns =
	173	clockevent_delta2ns(-1, &clockevent_mpu_timer1);
	174	clockevent_mpu_timer1.min_delta_ns =
	175	clockevent_delta2ns(1, &clockevent_mpu_timer1);
	176
320ab2b0	177	clockevent_mpu_timer1.cpumask = cpumask_of(0);
075192ae KH	178	clockevents_register_device(&clockevent_mpu_timer1);
	179	}
	180
	181
	182	/*
	183	* ---------------------------------------------------------------------------
	184	* MPU timer 2 ... free running 32-bit clock source and scheduler clock
	185	* ---------------------------------------------------------------------------
	186	*/
	187
	188	static unsigned long omap_mpu_timer2_overflows;
	189
	190	static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
1da177e4	191	{
075192ae	192	omap_mpu_timer2_overflows++;
1da177e4 LT	193	return IRQ_HANDLED;
	194	}
	195
075192ae KH	196	static struct irqaction omap_mpu_timer2_irq = {
075192ae KH	197	.name = "mpu_timer2",
52e405ea	198	.flags = IRQF_DISABLED,
075192ae	199	.handler = omap_mpu_timer2_interrupt,
1da177e4 LT	200	};
1da177e4 LT	201
8e19608e	202	static cycle_t mpu_read(struct clocksource *cs)
1da177e4	203	{
075192ae KH	204	return ~omap_mpu_timer_read(1);
	205	}
	206
	207	static struct clocksource clocksource_mpu = {
	208	.name = "mpu_timer2",
	209	.rating = 300,
	210	.read = mpu_read,
	211	.mask = CLOCKSOURCE_MASK(32),
075192ae KH	212	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	213	};
	214
	215	static void __init omap_init_clocksource(unsigned long rate)
	216	{
	217	static char err[] __initdata = KERN_ERR
	218	"%s: can't register clocksource!\n";
	219
075192ae KH	220	setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
	221	omap_mpu_timer_start(1, ~0, 1);
	222
8437c25e	223	if (clocksource_register_hz(&clocksource_mpu, rate))
075192ae	224	printk(err, clocksource_mpu.name);
1da177e4 LT	225	}
1da177e4 LT	226
1da177e4 LT	227	/*
	228	* ---------------------------------------------------------------------------
	229	* Timer initialization
	230	* ---------------------------------------------------------------------------
	231	*/
3b59b6be	232	static void __init omap_timer_init(void)
1da177e4	233	{
075192ae KH	234	struct clk *ck_ref = clk_get(NULL, "ck_ref");
	235	unsigned long rate;
	236
	237	BUG_ON(IS_ERR(ck_ref));
	238
	239	rate = clk_get_rate(ck_ref);
	240	clk_put(ck_ref);
	241
	242	/* PTV = 0 */
	243	rate /= 2;
	244
	245	omap_init_mpu_timer(rate);
	246	omap_init_clocksource(rate);
1da177e4 LT	247	}
	248
	249	struct sys_timer omap_timer = {
	250	.init = omap_timer_init,
1da177e4	251	};