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6fdc29e2 SMK |
1 | /* |
2 | * linux/arch/arm/mach-omap2/board-3430sdp.c | |
3 | * | |
4 | * Copyright (C) 2007 Texas Instruments | |
5 | * | |
6 | * Modified from mach-omap2/board-generic.c | |
7 | * | |
8 | * Initial code: Syed Mohammed Khasim | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/input.h> | |
6135434a | 20 | #include <linux/input/matrix_keypad.h> |
6fdc29e2 | 21 | #include <linux/spi/spi.h> |
b07682b6 | 22 | #include <linux/i2c/twl.h> |
6fdc29e2 SMK |
23 | #include <linux/regulator/machine.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/gpio.h> | |
3a63833e | 26 | #include <linux/mmc/host.h> |
2203747c | 27 | #include <linux/platform_data/spi-omap2-mcspi.h> |
6fdc29e2 | 28 | |
6fdc29e2 SMK |
29 | #include <asm/mach-types.h> |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach/map.h> | |
32 | ||
ce491cf8 | 33 | #include <plat/usb.h> |
4e65331c | 34 | #include "common.h" |
ce491cf8 TL |
35 | #include <plat/dma.h> |
36 | #include <plat/gpmc.h> | |
a0b38cc4 | 37 | #include <video/omapdss.h> |
dac8eb5f | 38 | #include <video/omap-panel-tfp410.h> |
6fdc29e2 | 39 | |
60628152 | 40 | #include "gpmc-smc91x.h" |
6fdc29e2 | 41 | |
04aeae77 | 42 | #include "board-flash.h" |
ca5742bd | 43 | #include "mux.h" |
17a722ca | 44 | #include "sdram-qimonda-hyb18m512160af-6.h" |
d02a900b | 45 | #include "hsmmc.h" |
bb4de3df | 46 | #include "pm.h" |
4814ced5 | 47 | #include "control.h" |
96974a24 | 48 | #include "common-board-devices.h" |
6fdc29e2 SMK |
49 | |
50 | #define CONFIG_DISABLE_HFCLK 1 | |
51 | ||
6fdc29e2 SMK |
52 | #define SDP3430_TS_GPIO_IRQ_SDPV1 3 |
53 | #define SDP3430_TS_GPIO_IRQ_SDPV2 2 | |
54 | ||
55 | #define ENABLE_VAUX3_DEDICATED 0x03 | |
56 | #define ENABLE_VAUX3_DEV_GRP 0x20 | |
57 | ||
58 | #define TWL4030_MSECURE_GPIO 22 | |
59 | ||
bead4375 | 60 | static uint32_t board_keymap[] = { |
6fdc29e2 SMK |
61 | KEY(0, 0, KEY_LEFT), |
62 | KEY(0, 1, KEY_RIGHT), | |
63 | KEY(0, 2, KEY_A), | |
64 | KEY(0, 3, KEY_B), | |
65 | KEY(0, 4, KEY_C), | |
66 | KEY(1, 0, KEY_DOWN), | |
67 | KEY(1, 1, KEY_UP), | |
68 | KEY(1, 2, KEY_E), | |
69 | KEY(1, 3, KEY_F), | |
70 | KEY(1, 4, KEY_G), | |
71 | KEY(2, 0, KEY_ENTER), | |
72 | KEY(2, 1, KEY_I), | |
73 | KEY(2, 2, KEY_J), | |
74 | KEY(2, 3, KEY_K), | |
75 | KEY(2, 4, KEY_3), | |
76 | KEY(3, 0, KEY_M), | |
77 | KEY(3, 1, KEY_N), | |
78 | KEY(3, 2, KEY_O), | |
79 | KEY(3, 3, KEY_P), | |
80 | KEY(3, 4, KEY_Q), | |
81 | KEY(4, 0, KEY_R), | |
82 | KEY(4, 1, KEY_4), | |
83 | KEY(4, 2, KEY_T), | |
84 | KEY(4, 3, KEY_U), | |
85 | KEY(4, 4, KEY_D), | |
86 | KEY(5, 0, KEY_V), | |
87 | KEY(5, 1, KEY_W), | |
88 | KEY(5, 2, KEY_L), | |
89 | KEY(5, 3, KEY_S), | |
90 | KEY(5, 4, KEY_H), | |
91 | 0 | |
92 | }; | |
93 | ||
4f543332 TL |
94 | static struct matrix_keymap_data board_map_data = { |
95 | .keymap = board_keymap, | |
96 | .keymap_size = ARRAY_SIZE(board_keymap), | |
97 | }; | |
98 | ||
6fdc29e2 | 99 | static struct twl4030_keypad_data sdp3430_kp_data = { |
4f543332 | 100 | .keymap_data = &board_map_data, |
6fdc29e2 SMK |
101 | .rows = 5, |
102 | .cols = 6, | |
6fdc29e2 SMK |
103 | .rep = 1, |
104 | }; | |
105 | ||
d9056ce2 TV |
106 | #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 |
107 | #define SDP3430_LCD_PANEL_ENABLE_GPIO 5 | |
108 | ||
bc593f5d IG |
109 | static struct gpio sdp3430_dss_gpios[] __initdata = { |
110 | {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" }, | |
111 | {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, | |
112 | }; | |
113 | ||
d9056ce2 TV |
114 | static void __init sdp3430_display_init(void) |
115 | { | |
116 | int r; | |
117 | ||
bc593f5d IG |
118 | r = gpio_request_array(sdp3430_dss_gpios, |
119 | ARRAY_SIZE(sdp3430_dss_gpios)); | |
120 | if (r) | |
121 | printk(KERN_ERR "failed to get LCD control GPIOs\n"); | |
d9056ce2 | 122 | |
d9056ce2 TV |
123 | } |
124 | ||
125 | static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) | |
126 | { | |
bc593f5d IG |
127 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); |
128 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); | |
d9056ce2 | 129 | |
d9056ce2 TV |
130 | return 0; |
131 | } | |
132 | ||
133 | static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) | |
134 | { | |
bc593f5d IG |
135 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); |
136 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); | |
d9056ce2 TV |
137 | } |
138 | ||
d9056ce2 TV |
139 | static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev) | |
145 | { | |
146 | } | |
147 | ||
148 | ||
149 | static struct omap_dss_device sdp3430_lcd_device = { | |
150 | .name = "lcd", | |
151 | .driver_name = "sharp_ls_panel", | |
152 | .type = OMAP_DISPLAY_TYPE_DPI, | |
153 | .phy.dpi.data_lines = 16, | |
154 | .platform_enable = sdp3430_panel_enable_lcd, | |
155 | .platform_disable = sdp3430_panel_disable_lcd, | |
6fdc29e2 SMK |
156 | }; |
157 | ||
2e6f2ee7 | 158 | static struct tfp410_platform_data dvi_panel = { |
e813a55e | 159 | .power_down_gpio = -1, |
89747c91 BW |
160 | }; |
161 | ||
d9056ce2 TV |
162 | static struct omap_dss_device sdp3430_dvi_device = { |
163 | .name = "dvi", | |
d9056ce2 | 164 | .type = OMAP_DISPLAY_TYPE_DPI, |
2e6f2ee7 | 165 | .driver_name = "tfp410", |
89747c91 | 166 | .data = &dvi_panel, |
d9056ce2 | 167 | .phy.dpi.data_lines = 24, |
6fdc29e2 SMK |
168 | }; |
169 | ||
d9056ce2 TV |
170 | static struct omap_dss_device sdp3430_tv_device = { |
171 | .name = "tv", | |
172 | .driver_name = "venc", | |
173 | .type = OMAP_DISPLAY_TYPE_VENC, | |
174 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
175 | .platform_enable = sdp3430_panel_enable_tv, | |
176 | .platform_disable = sdp3430_panel_disable_tv, | |
6fdc29e2 SMK |
177 | }; |
178 | ||
d9056ce2 TV |
179 | |
180 | static struct omap_dss_device *sdp3430_dss_devices[] = { | |
6fdc29e2 | 181 | &sdp3430_lcd_device, |
d9056ce2 TV |
182 | &sdp3430_dvi_device, |
183 | &sdp3430_tv_device, | |
6fdc29e2 SMK |
184 | }; |
185 | ||
d9056ce2 TV |
186 | static struct omap_dss_board_info sdp3430_dss_data = { |
187 | .num_devices = ARRAY_SIZE(sdp3430_dss_devices), | |
188 | .devices = sdp3430_dss_devices, | |
189 | .default_device = &sdp3430_lcd_device, | |
190 | }; | |
191 | ||
68ff0423 | 192 | static struct omap2_hsmmc_info mmc[] = { |
6fdc29e2 SMK |
193 | { |
194 | .mmc = 1, | |
195 | /* 8 bits (default) requires S6.3 == ON, | |
196 | * so the SIM card isn't used; else 4 bits. | |
197 | */ | |
3a63833e | 198 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 | 199 | .gpio_wp = 4, |
3b972bf0 | 200 | .deferred = true, |
6fdc29e2 SMK |
201 | }, |
202 | { | |
203 | .mmc = 2, | |
3a63833e | 204 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 | 205 | .gpio_wp = 7, |
3b972bf0 | 206 | .deferred = true, |
6fdc29e2 SMK |
207 | }, |
208 | {} /* Terminator */ | |
209 | }; | |
210 | ||
6fdc29e2 SMK |
211 | static int sdp3430_twl_gpio_setup(struct device *dev, |
212 | unsigned gpio, unsigned ngpio) | |
213 | { | |
214 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | |
215 | * gpio + 1 is "mmc1_cd" (input/IRQ) | |
216 | */ | |
217 | mmc[0].gpio_cd = gpio + 0; | |
218 | mmc[1].gpio_cd = gpio + 1; | |
3b972bf0 | 219 | omap_hsmmc_late_init(mmc); |
6fdc29e2 | 220 | |
6fdc29e2 | 221 | /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ |
bc593f5d | 222 | gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl"); |
6fdc29e2 SMK |
223 | |
224 | /* gpio + 15 is "sub_lcd_nRST" (output) */ | |
bc593f5d | 225 | gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST"); |
6fdc29e2 SMK |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | |
6fdc29e2 SMK |
231 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) |
232 | | BIT(16) | BIT(17), | |
233 | .setup = sdp3430_twl_gpio_setup, | |
234 | }; | |
235 | ||
73a92aa4 RN |
236 | /* regulator consumer mappings */ |
237 | ||
4b087ff8 RN |
238 | /* ads7846 on SPI */ |
239 | static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { | |
240 | REGULATOR_SUPPLY("vcc", "spi1.0"), | |
241 | }; | |
242 | ||
73a92aa4 | 243 | static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { |
0005ae73 | 244 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), |
73a92aa4 RN |
245 | }; |
246 | ||
247 | static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { | |
0005ae73 | 248 | REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), |
73a92aa4 RN |
249 | }; |
250 | ||
251 | static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { | |
0005ae73 | 252 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), |
73a92aa4 RN |
253 | }; |
254 | ||
6fdc29e2 SMK |
255 | /* |
256 | * Apply all the fixed voltages since most versions of U-Boot | |
257 | * don't bother with that initialization. | |
258 | */ | |
259 | ||
260 | /* VAUX1 for mainboard (irda and sub-lcd) */ | |
261 | static struct regulator_init_data sdp3430_vaux1 = { | |
262 | .constraints = { | |
263 | .min_uV = 2800000, | |
264 | .max_uV = 2800000, | |
265 | .apply_uV = true, | |
266 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
267 | | REGULATOR_MODE_STANDBY, | |
268 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
269 | | REGULATOR_CHANGE_STATUS, | |
270 | }, | |
271 | }; | |
272 | ||
273 | /* VAUX2 for camera module */ | |
274 | static struct regulator_init_data sdp3430_vaux2 = { | |
275 | .constraints = { | |
276 | .min_uV = 2800000, | |
277 | .max_uV = 2800000, | |
278 | .apply_uV = true, | |
279 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
280 | | REGULATOR_MODE_STANDBY, | |
281 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
282 | | REGULATOR_CHANGE_STATUS, | |
283 | }, | |
284 | }; | |
285 | ||
286 | /* VAUX3 for LCD board */ | |
287 | static struct regulator_init_data sdp3430_vaux3 = { | |
288 | .constraints = { | |
289 | .min_uV = 2800000, | |
290 | .max_uV = 2800000, | |
291 | .apply_uV = true, | |
292 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
293 | | REGULATOR_MODE_STANDBY, | |
294 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
295 | | REGULATOR_CHANGE_STATUS, | |
296 | }, | |
4b087ff8 RN |
297 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), |
298 | .consumer_supplies = sdp3430_vaux3_supplies, | |
6fdc29e2 SMK |
299 | }; |
300 | ||
301 | /* VAUX4 for OMAP VDD_CSI2 (camera) */ | |
302 | static struct regulator_init_data sdp3430_vaux4 = { | |
303 | .constraints = { | |
304 | .min_uV = 1800000, | |
305 | .max_uV = 1800000, | |
306 | .apply_uV = true, | |
307 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
308 | | REGULATOR_MODE_STANDBY, | |
309 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
310 | | REGULATOR_CHANGE_STATUS, | |
311 | }, | |
312 | }; | |
313 | ||
314 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | |
315 | static struct regulator_init_data sdp3430_vmmc1 = { | |
316 | .constraints = { | |
317 | .min_uV = 1850000, | |
318 | .max_uV = 3150000, | |
319 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
320 | | REGULATOR_MODE_STANDBY, | |
321 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
322 | | REGULATOR_CHANGE_MODE | |
323 | | REGULATOR_CHANGE_STATUS, | |
324 | }, | |
73a92aa4 RN |
325 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), |
326 | .consumer_supplies = sdp3430_vmmc1_supplies, | |
6fdc29e2 SMK |
327 | }; |
328 | ||
329 | /* VMMC2 for MMC2 card */ | |
330 | static struct regulator_init_data sdp3430_vmmc2 = { | |
331 | .constraints = { | |
332 | .min_uV = 1850000, | |
333 | .max_uV = 1850000, | |
334 | .apply_uV = true, | |
335 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
336 | | REGULATOR_MODE_STANDBY, | |
337 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
338 | | REGULATOR_CHANGE_STATUS, | |
339 | }, | |
73a92aa4 RN |
340 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), |
341 | .consumer_supplies = sdp3430_vmmc2_supplies, | |
6fdc29e2 SMK |
342 | }; |
343 | ||
344 | /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ | |
345 | static struct regulator_init_data sdp3430_vsim = { | |
346 | .constraints = { | |
347 | .min_uV = 1800000, | |
348 | .max_uV = 3000000, | |
349 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
350 | | REGULATOR_MODE_STANDBY, | |
351 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
352 | | REGULATOR_CHANGE_MODE | |
353 | | REGULATOR_CHANGE_STATUS, | |
354 | }, | |
73a92aa4 RN |
355 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), |
356 | .consumer_supplies = sdp3430_vsim_supplies, | |
6fdc29e2 SMK |
357 | }; |
358 | ||
6fdc29e2 | 359 | static struct twl4030_platform_data sdp3430_twldata = { |
6fdc29e2 | 360 | /* platform_data for children goes here */ |
6fdc29e2 | 361 | .gpio = &sdp3430_gpio_data, |
6fdc29e2 | 362 | .keypad = &sdp3430_kp_data, |
6fdc29e2 SMK |
363 | |
364 | .vaux1 = &sdp3430_vaux1, | |
365 | .vaux2 = &sdp3430_vaux2, | |
366 | .vaux3 = &sdp3430_vaux3, | |
367 | .vaux4 = &sdp3430_vaux4, | |
368 | .vmmc1 = &sdp3430_vmmc1, | |
369 | .vmmc2 = &sdp3430_vmmc2, | |
370 | .vsim = &sdp3430_vsim, | |
6fdc29e2 SMK |
371 | }; |
372 | ||
6fdc29e2 SMK |
373 | static int __init omap3430_i2c_init(void) |
374 | { | |
375 | /* i2c1 for PMIC only */ | |
827ed9ae | 376 | omap3_pmic_get_config(&sdp3430_twldata, |
b252b0ef PU |
377 | TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI | |
378 | TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, | |
379 | TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); | |
380 | sdp3430_twldata.vdac->constraints.apply_uV = true; | |
381 | sdp3430_twldata.vpll2->constraints.apply_uV = true; | |
382 | sdp3430_twldata.vpll2->constraints.name = "VDVI"; | |
383 | ||
fbd8071c | 384 | omap3_pmic_init("twl4030", &sdp3430_twldata); |
827ed9ae | 385 | |
6fdc29e2 SMK |
386 | /* i2c2 on camera connector (for sensor control) and optional isp1301 */ |
387 | omap_register_i2c_bus(2, 400, NULL, 0); | |
388 | /* i2c3 on display connector (for DVI, tfp410) */ | |
389 | omap_register_i2c_bus(3, 400, NULL, 0); | |
390 | return 0; | |
391 | } | |
392 | ||
1a48e157 TL |
393 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
394 | ||
395 | static struct omap_smc91x_platform_data board_smc91x_data = { | |
396 | .cs = 3, | |
397 | .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | | |
398 | IORESOURCE_IRQ_LOWLEVEL, | |
399 | }; | |
400 | ||
401 | static void __init board_smc91x_init(void) | |
402 | { | |
403 | if (omap_rev() > OMAP3430_REV_ES1_0) | |
404 | board_smc91x_data.gpio_irq = 6; | |
405 | else | |
406 | board_smc91x_data.gpio_irq = 29; | |
407 | ||
408 | gpmc_smc91x_init(&board_smc91x_data); | |
409 | } | |
410 | ||
411 | #else | |
412 | ||
413 | static inline void board_smc91x_init(void) | |
414 | { | |
415 | } | |
416 | ||
417 | #endif | |
418 | ||
5110b298 RT |
419 | static void enable_board_wakeup_source(void) |
420 | { | |
4896e394 TL |
421 | /* T2 interrupt line (keypad) */ |
422 | omap_mux_init_signal("sys_nirq", | |
423 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | |
5110b298 RT |
424 | } |
425 | ||
181b250c | 426 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { |
58a5491c | 427 | |
181b250c KM |
428 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
429 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
430 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
58a5491c FB |
431 | |
432 | .phy_reset = true, | |
433 | .reset_gpio_port[0] = 57, | |
434 | .reset_gpio_port[1] = 61, | |
435 | .reset_gpio_port[2] = -EINVAL | |
436 | }; | |
437 | ||
ca5742bd TL |
438 | #ifdef CONFIG_OMAP_MUX |
439 | static struct omap_board_mux board_mux[] __initdata = { | |
440 | { .reg_offset = OMAP_MUX_TERMINATOR }, | |
441 | }; | |
626dda8a S |
442 | #else |
443 | #define board_mux NULL | |
ca5742bd TL |
444 | #endif |
445 | ||
13d6b73c SG |
446 | /* |
447 | * SDP3430 V2 Board CS organization | |
448 | * Different from SDP3430 V1. Now 4 switches used to specify CS | |
449 | * | |
450 | * See also the Switch S8 settings in the comments. | |
451 | */ | |
452 | static char chip_sel_3430[][GPMC_CS_NUM] = { | |
453 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | |
454 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | |
455 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | |
456 | }; | |
457 | ||
88c8460a VS |
458 | static struct mtd_partition sdp_nor_partitions[] = { |
459 | /* bootloader (U-Boot, etc) in first sector */ | |
460 | { | |
461 | .name = "Bootloader-NOR", | |
462 | .offset = 0, | |
463 | .size = SZ_256K, | |
464 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
465 | }, | |
466 | /* bootloader params in the next sector */ | |
467 | { | |
468 | .name = "Params-NOR", | |
469 | .offset = MTDPART_OFS_APPEND, | |
470 | .size = SZ_256K, | |
471 | .mask_flags = 0, | |
472 | }, | |
473 | /* kernel */ | |
474 | { | |
475 | .name = "Kernel-NOR", | |
476 | .offset = MTDPART_OFS_APPEND, | |
477 | .size = SZ_2M, | |
478 | .mask_flags = 0 | |
479 | }, | |
480 | /* file system */ | |
481 | { | |
482 | .name = "Filesystem-NOR", | |
483 | .offset = MTDPART_OFS_APPEND, | |
484 | .size = MTDPART_SIZ_FULL, | |
485 | .mask_flags = 0 | |
486 | } | |
487 | }; | |
488 | ||
489 | static struct mtd_partition sdp_onenand_partitions[] = { | |
490 | { | |
491 | .name = "X-Loader-OneNAND", | |
492 | .offset = 0, | |
493 | .size = 4 * (64 * 2048), | |
494 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
495 | }, | |
496 | { | |
497 | .name = "U-Boot-OneNAND", | |
498 | .offset = MTDPART_OFS_APPEND, | |
499 | .size = 2 * (64 * 2048), | |
500 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
501 | }, | |
502 | { | |
503 | .name = "U-Boot Environment-OneNAND", | |
504 | .offset = MTDPART_OFS_APPEND, | |
505 | .size = 1 * (64 * 2048), | |
506 | }, | |
507 | { | |
508 | .name = "Kernel-OneNAND", | |
509 | .offset = MTDPART_OFS_APPEND, | |
510 | .size = 16 * (64 * 2048), | |
511 | }, | |
512 | { | |
513 | .name = "File System-OneNAND", | |
514 | .offset = MTDPART_OFS_APPEND, | |
515 | .size = MTDPART_SIZ_FULL, | |
516 | }, | |
517 | }; | |
518 | ||
519 | static struct mtd_partition sdp_nand_partitions[] = { | |
520 | /* All the partition sizes are listed in terms of NAND block size */ | |
521 | { | |
522 | .name = "X-Loader-NAND", | |
523 | .offset = 0, | |
524 | .size = 4 * (64 * 2048), | |
525 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
526 | }, | |
527 | { | |
528 | .name = "U-Boot-NAND", | |
529 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
530 | .size = 10 * (64 * 2048), | |
531 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
532 | }, | |
533 | { | |
534 | .name = "Boot Env-NAND", | |
535 | ||
536 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | |
537 | .size = 6 * (64 * 2048), | |
538 | }, | |
539 | { | |
540 | .name = "Kernel-NAND", | |
541 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | |
542 | .size = 40 * (64 * 2048), | |
543 | }, | |
544 | { | |
545 | .name = "File System - NAND", | |
546 | .size = MTDPART_SIZ_FULL, | |
547 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | |
548 | }, | |
549 | }; | |
550 | ||
551 | static struct flash_partitions sdp_flash_partitions[] = { | |
552 | { | |
553 | .parts = sdp_nor_partitions, | |
554 | .nr_parts = ARRAY_SIZE(sdp_nor_partitions), | |
555 | }, | |
556 | { | |
557 | .parts = sdp_onenand_partitions, | |
558 | .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), | |
559 | }, | |
560 | { | |
561 | .parts = sdp_nand_partitions, | |
562 | .nr_parts = ARRAY_SIZE(sdp_nand_partitions), | |
563 | }, | |
564 | }; | |
565 | ||
6fdc29e2 SMK |
566 | static void __init omap_3430sdp_init(void) |
567 | { | |
96974a24 MR |
568 | int gpio_pendown; |
569 | ||
ca5742bd | 570 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
3b972bf0 | 571 | omap_hsmmc_init(mmc); |
6fdc29e2 | 572 | omap3430_i2c_init(); |
d5e13227 | 573 | omap_display_init(&sdp3430_dss_data); |
6fdc29e2 | 574 | if (omap_rev() > OMAP3430_REV_ES1_0) |
96974a24 | 575 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2; |
6fdc29e2 | 576 | else |
96974a24 MR |
577 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; |
578 | omap_ads7846_init(1, gpio_pendown, 310, NULL); | |
7496ba30 | 579 | omap_serial_init(); |
a4ca9dbe | 580 | omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); |
9e18630b | 581 | usb_musb_init(NULL); |
1a48e157 | 582 | board_smc91x_init(); |
d5ce2b65 | 583 | board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); |
d9056ce2 | 584 | sdp3430_display_init(); |
5110b298 | 585 | enable_board_wakeup_source(); |
9e64bb1e | 586 | usbhs_init(&usbhs_bdata); |
6fdc29e2 SMK |
587 | } |
588 | ||
6fdc29e2 SMK |
589 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
590 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | |
5e52b435 | 591 | .atag_offset = 0x100, |
71ee7dad | 592 | .reserve = omap_reserve, |
3dc3bad6 | 593 | .map_io = omap3_map_io, |
8f5b5a41 | 594 | .init_early = omap3430_init_early, |
741e3a89 | 595 | .init_irq = omap3_init_irq, |
6b2f55d7 | 596 | .handle_irq = omap3_intc_handle_irq, |
6fdc29e2 | 597 | .init_machine = omap_3430sdp_init, |
bbd707ac | 598 | .init_late = omap3430_init_late, |
e74984e4 | 599 | .timer = &omap3_timer, |
baa95883 | 600 | .restart = omap_prcm_restart, |
6fdc29e2 | 601 | MACHINE_END |