Merge branch 'vmwgfx-fixes-3.13' of git://people.freedesktop.org/~thomash/linux into...
[deliverable/linux.git] / arch / arm / mach-omap2 / board-3430sdp.c
CommitLineData
6fdc29e2
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1/*
2 * linux/arch/arm/mach-omap2/board-3430sdp.c
3 *
4 * Copyright (C) 2007 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/input.h>
6135434a 20#include <linux/input/matrix_keypad.h>
6fdc29e2 21#include <linux/spi/spi.h>
b07682b6 22#include <linux/i2c/twl.h>
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23#include <linux/regulator/machine.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
3a63833e 26#include <linux/mmc/host.h>
2203747c 27#include <linux/platform_data/spi-omap2-mcspi.h>
77f86144 28#include <linux/platform_data/omap-twl4030.h>
51482be9 29#include <linux/usb/phy.h>
6fdc29e2 30
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31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34
4e65331c 35#include "common.h"
45c3eb7d 36#include <linux/omap-dma.h>
a0b38cc4 37#include <video/omapdss.h>
a0d8dde9 38#include <video/omap-panel-data.h>
6fdc29e2 39
99f0b8d6 40#include "gpmc.h"
60628152 41#include "gpmc-smc91x.h"
6fdc29e2 42
e4c060db 43#include "soc.h"
04aeae77 44#include "board-flash.h"
ca5742bd 45#include "mux.h"
17a722ca 46#include "sdram-qimonda-hyb18m512160af-6.h"
d02a900b 47#include "hsmmc.h"
bb4de3df 48#include "pm.h"
4814ced5 49#include "control.h"
96974a24 50#include "common-board-devices.h"
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51
52#define CONFIG_DISABLE_HFCLK 1
53
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54#define SDP3430_TS_GPIO_IRQ_SDPV1 3
55#define SDP3430_TS_GPIO_IRQ_SDPV2 2
56
57#define ENABLE_VAUX3_DEDICATED 0x03
58#define ENABLE_VAUX3_DEV_GRP 0x20
59
60#define TWL4030_MSECURE_GPIO 22
61
bead4375 62static uint32_t board_keymap[] = {
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63 KEY(0, 0, KEY_LEFT),
64 KEY(0, 1, KEY_RIGHT),
65 KEY(0, 2, KEY_A),
66 KEY(0, 3, KEY_B),
67 KEY(0, 4, KEY_C),
68 KEY(1, 0, KEY_DOWN),
69 KEY(1, 1, KEY_UP),
70 KEY(1, 2, KEY_E),
71 KEY(1, 3, KEY_F),
72 KEY(1, 4, KEY_G),
73 KEY(2, 0, KEY_ENTER),
74 KEY(2, 1, KEY_I),
75 KEY(2, 2, KEY_J),
76 KEY(2, 3, KEY_K),
77 KEY(2, 4, KEY_3),
78 KEY(3, 0, KEY_M),
79 KEY(3, 1, KEY_N),
80 KEY(3, 2, KEY_O),
81 KEY(3, 3, KEY_P),
82 KEY(3, 4, KEY_Q),
83 KEY(4, 0, KEY_R),
84 KEY(4, 1, KEY_4),
85 KEY(4, 2, KEY_T),
86 KEY(4, 3, KEY_U),
87 KEY(4, 4, KEY_D),
88 KEY(5, 0, KEY_V),
89 KEY(5, 1, KEY_W),
90 KEY(5, 2, KEY_L),
91 KEY(5, 3, KEY_S),
92 KEY(5, 4, KEY_H),
93 0
94};
95
4f543332
TL
96static struct matrix_keymap_data board_map_data = {
97 .keymap = board_keymap,
98 .keymap_size = ARRAY_SIZE(board_keymap),
99};
100
6fdc29e2 101static struct twl4030_keypad_data sdp3430_kp_data = {
4f543332 102 .keymap_data = &board_map_data,
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103 .rows = 5,
104 .cols = 6,
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105 .rep = 1,
106};
107
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108#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
109#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
110
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TV
111static void __init sdp3430_display_init(void)
112{
113 int r;
114
a05f92b7
AT
115 /*
116 * the backlight GPIO doesn't directly go to the panel, it enables
117 * an internal circuit on 3430sdp to create the signal V_BKL_28V,
118 * this is connected to LED+ pin of the sharp panel. This GPIO
119 * is left enabled in the board file, and not passed to the panel
120 * as platform_data.
121 */
122 r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO,
123 GPIOF_OUT_INIT_HIGH, "LCD Backlight");
bc593f5d 124 if (r)
a05f92b7 125 pr_err("failed to get LCD Backlight GPIO\n");
d9056ce2 126
d9056ce2
TV
127}
128
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TV
129static struct panel_sharp_ls037v7dw01_platform_data sdp3430_lcd_pdata = {
130 .name = "lcd",
131 .source = "dpi.0",
132
133 .data_lines = 16,
134
135 .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO,
136 .ini_gpio = -1,
137 .mo_gpio = -1,
138 .lr_gpio = -1,
139 .ud_gpio = -1,
140};
141
142static struct platform_device sdp3430_lcd_device = {
143 .name = "panel-sharp-ls037v7dw01",
144 .id = 0,
145 .dev.platform_data = &sdp3430_lcd_pdata,
a05f92b7 146};
d9056ce2 147
7a2950cc
TV
148static struct connector_dvi_platform_data sdp3430_dvi_connector_pdata = {
149 .name = "dvi",
150 .source = "tfp410.0",
151 .i2c_bus_num = -1,
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SMK
152};
153
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TV
154static struct platform_device sdp3430_dvi_connector_device = {
155 .name = "connector-dvi",
156 .id = 0,
157 .dev.platform_data = &sdp3430_dvi_connector_pdata,
89747c91
BW
158};
159
7a2950cc
TV
160static struct encoder_tfp410_platform_data sdp3430_tfp410_pdata = {
161 .name = "tfp410.0",
162 .source = "dpi.0",
163 .data_lines = 24,
164 .power_down_gpio = -1,
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165};
166
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TV
167static struct platform_device sdp3430_tfp410_device = {
168 .name = "tfp410",
169 .id = 0,
170 .dev.platform_data = &sdp3430_tfp410_pdata,
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171};
172
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TV
173static struct connector_atv_platform_data sdp3430_tv_pdata = {
174 .name = "tv",
175 .source = "venc.0",
176 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
177 .invert_polarity = false,
178};
d9056ce2 179
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TV
180static struct platform_device sdp3430_tv_connector_device = {
181 .name = "connector-analog-tv",
182 .id = 0,
183 .dev.platform_data = &sdp3430_tv_pdata,
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184};
185
d9056ce2 186static struct omap_dss_board_info sdp3430_dss_data = {
7a2950cc 187 .default_display_name = "lcd",
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TV
188};
189
68ff0423 190static struct omap2_hsmmc_info mmc[] = {
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191 {
192 .mmc = 1,
193 /* 8 bits (default) requires S6.3 == ON,
194 * so the SIM card isn't used; else 4 bits.
195 */
3a63833e 196 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
6fdc29e2 197 .gpio_wp = 4,
3b972bf0 198 .deferred = true,
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199 },
200 {
201 .mmc = 2,
3a63833e 202 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
6fdc29e2 203 .gpio_wp = 7,
3b972bf0 204 .deferred = true,
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205 },
206 {} /* Terminator */
207};
208
77f86144
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209static struct omap_tw4030_pdata omap_twl4030_audio_data = {
210 .voice_connected = true,
211 .custom_routing = true,
212
213 .has_hs = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
214 .has_hf = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
215
216 .has_mainmic = true,
217 .has_submic = true,
218 .has_hsmic = true,
219 .has_linein = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
220};
221
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222static int sdp3430_twl_gpio_setup(struct device *dev,
223 unsigned gpio, unsigned ngpio)
224{
225 /* gpio + 0 is "mmc0_cd" (input/IRQ),
226 * gpio + 1 is "mmc1_cd" (input/IRQ)
227 */
228 mmc[0].gpio_cd = gpio + 0;
229 mmc[1].gpio_cd = gpio + 1;
3b972bf0 230 omap_hsmmc_late_init(mmc);
6fdc29e2 231
6fdc29e2 232 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
bc593f5d 233 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
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234
235 /* gpio + 15 is "sub_lcd_nRST" (output) */
bc593f5d 236 gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
6fdc29e2 237
77f86144
PU
238 omap_twl4030_audio_data.jack_detect = gpio + 2;
239 omap_twl4030_audio_init("SDP3430", &omap_twl4030_audio_data);
240
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241 return 0;
242}
243
244static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
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245 .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
246 | BIT(16) | BIT(17),
247 .setup = sdp3430_twl_gpio_setup,
248};
249
73a92aa4
RN
250/* regulator consumer mappings */
251
4b087ff8
RN
252/* ads7846 on SPI */
253static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
254 REGULATOR_SUPPLY("vcc", "spi1.0"),
255};
256
73a92aa4 257static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
0005ae73 258 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
73a92aa4
RN
259};
260
261static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
0005ae73 262 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
73a92aa4
RN
263};
264
265static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
0005ae73 266 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
73a92aa4
RN
267};
268
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SMK
269/*
270 * Apply all the fixed voltages since most versions of U-Boot
271 * don't bother with that initialization.
272 */
273
274/* VAUX1 for mainboard (irda and sub-lcd) */
275static struct regulator_init_data sdp3430_vaux1 = {
276 .constraints = {
277 .min_uV = 2800000,
278 .max_uV = 2800000,
279 .apply_uV = true,
280 .valid_modes_mask = REGULATOR_MODE_NORMAL
281 | REGULATOR_MODE_STANDBY,
282 .valid_ops_mask = REGULATOR_CHANGE_MODE
283 | REGULATOR_CHANGE_STATUS,
284 },
285};
286
287/* VAUX2 for camera module */
288static struct regulator_init_data sdp3430_vaux2 = {
289 .constraints = {
290 .min_uV = 2800000,
291 .max_uV = 2800000,
292 .apply_uV = true,
293 .valid_modes_mask = REGULATOR_MODE_NORMAL
294 | REGULATOR_MODE_STANDBY,
295 .valid_ops_mask = REGULATOR_CHANGE_MODE
296 | REGULATOR_CHANGE_STATUS,
297 },
298};
299
300/* VAUX3 for LCD board */
301static struct regulator_init_data sdp3430_vaux3 = {
302 .constraints = {
303 .min_uV = 2800000,
304 .max_uV = 2800000,
305 .apply_uV = true,
306 .valid_modes_mask = REGULATOR_MODE_NORMAL
307 | REGULATOR_MODE_STANDBY,
308 .valid_ops_mask = REGULATOR_CHANGE_MODE
309 | REGULATOR_CHANGE_STATUS,
310 },
4b087ff8
RN
311 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
312 .consumer_supplies = sdp3430_vaux3_supplies,
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SMK
313};
314
315/* VAUX4 for OMAP VDD_CSI2 (camera) */
316static struct regulator_init_data sdp3430_vaux4 = {
317 .constraints = {
318 .min_uV = 1800000,
319 .max_uV = 1800000,
320 .apply_uV = true,
321 .valid_modes_mask = REGULATOR_MODE_NORMAL
322 | REGULATOR_MODE_STANDBY,
323 .valid_ops_mask = REGULATOR_CHANGE_MODE
324 | REGULATOR_CHANGE_STATUS,
325 },
326};
327
328/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
329static struct regulator_init_data sdp3430_vmmc1 = {
330 .constraints = {
331 .min_uV = 1850000,
332 .max_uV = 3150000,
333 .valid_modes_mask = REGULATOR_MODE_NORMAL
334 | REGULATOR_MODE_STANDBY,
335 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
336 | REGULATOR_CHANGE_MODE
337 | REGULATOR_CHANGE_STATUS,
338 },
73a92aa4
RN
339 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
340 .consumer_supplies = sdp3430_vmmc1_supplies,
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SMK
341};
342
343/* VMMC2 for MMC2 card */
344static struct regulator_init_data sdp3430_vmmc2 = {
345 .constraints = {
346 .min_uV = 1850000,
347 .max_uV = 1850000,
348 .apply_uV = true,
349 .valid_modes_mask = REGULATOR_MODE_NORMAL
350 | REGULATOR_MODE_STANDBY,
351 .valid_ops_mask = REGULATOR_CHANGE_MODE
352 | REGULATOR_CHANGE_STATUS,
353 },
73a92aa4
RN
354 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
355 .consumer_supplies = sdp3430_vmmc2_supplies,
6fdc29e2
SMK
356};
357
358/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
359static struct regulator_init_data sdp3430_vsim = {
360 .constraints = {
361 .min_uV = 1800000,
362 .max_uV = 3000000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL
364 | REGULATOR_MODE_STANDBY,
365 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
366 | REGULATOR_CHANGE_MODE
367 | REGULATOR_CHANGE_STATUS,
368 },
73a92aa4
RN
369 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
370 .consumer_supplies = sdp3430_vsim_supplies,
6fdc29e2
SMK
371};
372
6fdc29e2 373static struct twl4030_platform_data sdp3430_twldata = {
6fdc29e2 374 /* platform_data for children goes here */
6fdc29e2 375 .gpio = &sdp3430_gpio_data,
6fdc29e2 376 .keypad = &sdp3430_kp_data,
6fdc29e2
SMK
377
378 .vaux1 = &sdp3430_vaux1,
379 .vaux2 = &sdp3430_vaux2,
380 .vaux3 = &sdp3430_vaux3,
381 .vaux4 = &sdp3430_vaux4,
382 .vmmc1 = &sdp3430_vmmc1,
383 .vmmc2 = &sdp3430_vmmc2,
384 .vsim = &sdp3430_vsim,
6fdc29e2
SMK
385};
386
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SMK
387static int __init omap3430_i2c_init(void)
388{
389 /* i2c1 for PMIC only */
827ed9ae 390 omap3_pmic_get_config(&sdp3430_twldata,
b252b0ef
PU
391 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
392 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
393 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
394 sdp3430_twldata.vdac->constraints.apply_uV = true;
395 sdp3430_twldata.vpll2->constraints.apply_uV = true;
396 sdp3430_twldata.vpll2->constraints.name = "VDVI";
397
7b00077a
PU
398 sdp3430_twldata.audio->codec->hs_extmute = 1;
399 sdp3430_twldata.audio->codec->hs_extmute_gpio = -EINVAL;
400
fbd8071c 401 omap3_pmic_init("twl4030", &sdp3430_twldata);
827ed9ae 402
6fdc29e2
SMK
403 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
404 omap_register_i2c_bus(2, 400, NULL, 0);
405 /* i2c3 on display connector (for DVI, tfp410) */
406 omap_register_i2c_bus(3, 400, NULL, 0);
407 return 0;
408}
409
1a48e157
TL
410#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
411
412static struct omap_smc91x_platform_data board_smc91x_data = {
413 .cs = 3,
414 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
415 IORESOURCE_IRQ_LOWLEVEL,
416};
417
418static void __init board_smc91x_init(void)
419{
420 if (omap_rev() > OMAP3430_REV_ES1_0)
421 board_smc91x_data.gpio_irq = 6;
422 else
423 board_smc91x_data.gpio_irq = 29;
424
425 gpmc_smc91x_init(&board_smc91x_data);
426}
427
428#else
429
430static inline void board_smc91x_init(void)
431{
432}
433
434#endif
435
5110b298
RT
436static void enable_board_wakeup_source(void)
437{
4896e394
TL
438 /* T2 interrupt line (keypad) */
439 omap_mux_init_signal("sys_nirq",
440 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
5110b298
RT
441}
442
0047c909
RQ
443static struct usbhs_phy_data phy_data[] __initdata = {
444 {
445 .port = 1,
446 .reset_gpio = 57,
447 .vcc_gpio = -EINVAL,
448 },
449 {
450 .port = 2,
451 .reset_gpio = 61,
452 .vcc_gpio = -EINVAL,
453 },
454};
455
42973159 456static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
58a5491c 457
181b250c
KM
458 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
459 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
58a5491c
FB
460};
461
ca5742bd
TL
462#ifdef CONFIG_OMAP_MUX
463static struct omap_board_mux board_mux[] __initdata = {
464 { .reg_offset = OMAP_MUX_TERMINATOR },
465};
626dda8a
S
466#else
467#define board_mux NULL
ca5742bd
TL
468#endif
469
13d6b73c
SG
470/*
471 * SDP3430 V2 Board CS organization
472 * Different from SDP3430 V1. Now 4 switches used to specify CS
473 *
474 * See also the Switch S8 settings in the comments.
475 */
476static char chip_sel_3430[][GPMC_CS_NUM] = {
477 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
478 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
479 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
480};
481
88c8460a
VS
482static struct mtd_partition sdp_nor_partitions[] = {
483 /* bootloader (U-Boot, etc) in first sector */
484 {
485 .name = "Bootloader-NOR",
486 .offset = 0,
487 .size = SZ_256K,
488 .mask_flags = MTD_WRITEABLE, /* force read-only */
489 },
490 /* bootloader params in the next sector */
491 {
492 .name = "Params-NOR",
493 .offset = MTDPART_OFS_APPEND,
494 .size = SZ_256K,
495 .mask_flags = 0,
496 },
497 /* kernel */
498 {
499 .name = "Kernel-NOR",
500 .offset = MTDPART_OFS_APPEND,
501 .size = SZ_2M,
502 .mask_flags = 0
503 },
504 /* file system */
505 {
506 .name = "Filesystem-NOR",
507 .offset = MTDPART_OFS_APPEND,
508 .size = MTDPART_SIZ_FULL,
509 .mask_flags = 0
510 }
511};
512
513static struct mtd_partition sdp_onenand_partitions[] = {
514 {
515 .name = "X-Loader-OneNAND",
516 .offset = 0,
517 .size = 4 * (64 * 2048),
518 .mask_flags = MTD_WRITEABLE /* force read-only */
519 },
520 {
521 .name = "U-Boot-OneNAND",
522 .offset = MTDPART_OFS_APPEND,
523 .size = 2 * (64 * 2048),
524 .mask_flags = MTD_WRITEABLE /* force read-only */
525 },
526 {
527 .name = "U-Boot Environment-OneNAND",
528 .offset = MTDPART_OFS_APPEND,
529 .size = 1 * (64 * 2048),
530 },
531 {
532 .name = "Kernel-OneNAND",
533 .offset = MTDPART_OFS_APPEND,
534 .size = 16 * (64 * 2048),
535 },
536 {
537 .name = "File System-OneNAND",
538 .offset = MTDPART_OFS_APPEND,
539 .size = MTDPART_SIZ_FULL,
540 },
541};
542
543static struct mtd_partition sdp_nand_partitions[] = {
544 /* All the partition sizes are listed in terms of NAND block size */
545 {
546 .name = "X-Loader-NAND",
547 .offset = 0,
548 .size = 4 * (64 * 2048),
549 .mask_flags = MTD_WRITEABLE, /* force read-only */
550 },
551 {
552 .name = "U-Boot-NAND",
553 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
554 .size = 10 * (64 * 2048),
555 .mask_flags = MTD_WRITEABLE, /* force read-only */
556 },
557 {
558 .name = "Boot Env-NAND",
559
560 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
561 .size = 6 * (64 * 2048),
562 },
563 {
564 .name = "Kernel-NAND",
565 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
566 .size = 40 * (64 * 2048),
567 },
568 {
569 .name = "File System - NAND",
570 .size = MTDPART_SIZ_FULL,
571 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
572 },
573};
574
575static struct flash_partitions sdp_flash_partitions[] = {
576 {
577 .parts = sdp_nor_partitions,
578 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
579 },
580 {
581 .parts = sdp_onenand_partitions,
582 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
583 },
584 {
585 .parts = sdp_nand_partitions,
586 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
587 },
588};
589
6fdc29e2
SMK
590static void __init omap_3430sdp_init(void)
591{
96974a24
MR
592 int gpio_pendown;
593
ca5742bd 594 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
3b972bf0 595 omap_hsmmc_init(mmc);
6fdc29e2 596 omap3430_i2c_init();
d5e13227 597 omap_display_init(&sdp3430_dss_data);
7a2950cc
TV
598 platform_device_register(&sdp3430_lcd_device);
599 platform_device_register(&sdp3430_tfp410_device);
600 platform_device_register(&sdp3430_dvi_connector_device);
601 platform_device_register(&sdp3430_tv_connector_device);
602
6fdc29e2 603 if (omap_rev() > OMAP3430_REV_ES1_0)
96974a24 604 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
6fdc29e2 605 else
96974a24
MR
606 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
607 omap_ads7846_init(1, gpio_pendown, 310, NULL);
7496ba30 608 omap_serial_init();
a4ca9dbe 609 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
51482be9 610 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
9e18630b 611 usb_musb_init(NULL);
1a48e157 612 board_smc91x_init();
d5ce2b65 613 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
d9056ce2 614 sdp3430_display_init();
5110b298 615 enable_board_wakeup_source();
0047c909
RQ
616
617 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
9e64bb1e 618 usbhs_init(&usbhs_bdata);
6fdc29e2
SMK
619}
620
6fdc29e2
SMK
621MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
622 /* Maintainer: Syed Khasim - Texas Instruments Inc */
5e52b435 623 .atag_offset = 0x100,
71ee7dad 624 .reserve = omap_reserve,
3dc3bad6 625 .map_io = omap3_map_io,
8f5b5a41 626 .init_early = omap3430_init_early,
741e3a89 627 .init_irq = omap3_init_irq,
6b2f55d7 628 .handle_irq = omap3_intc_handle_irq,
6fdc29e2 629 .init_machine = omap_3430sdp_init,
bbd707ac 630 .init_late = omap3430_init_late,
6bb27d73 631 .init_time = omap3_sync32k_timer_init,
187e3e06 632 .restart = omap3xxx_restart,
6fdc29e2 633MACHINE_END
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