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Linux 2.6.39-rc7
[deliverable/linux.git] / arch / arm / mach-omap2 / board-3430sdp.c
CommitLineData
6fdc29e2
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-3430sdp.c
3 *
4 * Copyright (C) 2007 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/input.h>
6135434a 20#include <linux/input/matrix_keypad.h>
6fdc29e2
SMK		 21#include <linux/spi/spi.h>
22#include <linux/spi/ads7846.h>
b07682b6 23#include <linux/i2c/twl.h>
6fdc29e2
SMK		 24#include <linux/regulator/machine.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
3a63833e 27#include <linux/mmc/host.h>
6fdc29e2
SMK		 28
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33
ce491cf8 34#include <plat/mcspi.h>
ce491cf8
TL		 35#include <plat/board.h>
36#include <plat/usb.h>
37#include <plat/common.h>
38#include <plat/dma.h>
39#include <plat/gpmc.h>
d9056ce2 40#include <plat/display.h>
89747c91 41#include <plat/panel-generic-dpi.h>
6fdc29e2 42
ce491cf8 43#include <plat/gpmc-smc91x.h>
6fdc29e2 44
04aeae77 45#include "board-flash.h"
ca5742bd 46#include "mux.h"
17a722ca 47#include "sdram-qimonda-hyb18m512160af-6.h"
d02a900b 48#include "hsmmc.h"
bb4de3df 49#include "pm.h"
4814ced5 50#include "control.h"
6fdc29e2
SMK		 51
52#define CONFIG_DISABLE_HFCLK 1
53
6fdc29e2
SMK		 54#define SDP3430_TS_GPIO_IRQ_SDPV1 3
55#define SDP3430_TS_GPIO_IRQ_SDPV2 2
56
57#define ENABLE_VAUX3_DEDICATED 0x03
58#define ENABLE_VAUX3_DEV_GRP 0x20
59
60#define TWL4030_MSECURE_GPIO 22
61
bb4de3df
KH		 62/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
63static struct cpuidle_params omap3_cpuidle_params_table[] = {
64 /* C1 */
709731bb 65 {1, 2, 2, 5},
bb4de3df 66 /* C2 */
709731bb 67 {1, 10, 10, 30},
bb4de3df 68 /* C3 */
709731bb 69 {1, 50, 50, 300},
bb4de3df 70 /* C4 */
709731bb 71 {1, 1500, 1800, 4000},
bb4de3df 72 /* C5 */
709731bb 73 {1, 2500, 7500, 12000},
bb4de3df 74 /* C6 */
709731bb 75 {1, 3000, 8500, 15000},
bb4de3df 76 /* C7 */
709731bb 77 {1, 10000, 30000, 300000},
bb4de3df
KH		 78};
79
bead4375 80static uint32_t board_keymap[] = {
6fdc29e2
SMK		 81 KEY(0, 0, KEY_LEFT),
82 KEY(0, 1, KEY_RIGHT),
83 KEY(0, 2, KEY_A),
84 KEY(0, 3, KEY_B),
85 KEY(0, 4, KEY_C),
86 KEY(1, 0, KEY_DOWN),
87 KEY(1, 1, KEY_UP),
88 KEY(1, 2, KEY_E),
89 KEY(1, 3, KEY_F),
90 KEY(1, 4, KEY_G),
91 KEY(2, 0, KEY_ENTER),
92 KEY(2, 1, KEY_I),
93 KEY(2, 2, KEY_J),
94 KEY(2, 3, KEY_K),
95 KEY(2, 4, KEY_3),
96 KEY(3, 0, KEY_M),
97 KEY(3, 1, KEY_N),
98 KEY(3, 2, KEY_O),
99 KEY(3, 3, KEY_P),
100 KEY(3, 4, KEY_Q),
101 KEY(4, 0, KEY_R),
102 KEY(4, 1, KEY_4),
103 KEY(4, 2, KEY_T),
104 KEY(4, 3, KEY_U),
105 KEY(4, 4, KEY_D),
106 KEY(5, 0, KEY_V),
107 KEY(5, 1, KEY_W),
108 KEY(5, 2, KEY_L),
109 KEY(5, 3, KEY_S),
110 KEY(5, 4, KEY_H),
111 0
112};
113
4f543332
TL		 114static struct matrix_keymap_data board_map_data = {
115 .keymap = board_keymap,
116 .keymap_size = ARRAY_SIZE(board_keymap),
117};
118
6fdc29e2 119static struct twl4030_keypad_data sdp3430_kp_data = {
4f543332 120 .keymap_data = &board_map_data,
6fdc29e2
SMK		 121 .rows = 5,
122 .cols = 6,
6fdc29e2
SMK		 123 .rep = 1,
124};
125
126static int ts_gpio; /* Needed for ads7846_get_pendown_state */
127
128/**
129 * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
130 *
131 * @return - void. If request gpio fails then Flag KERN_ERR.
132 */
133static void ads7846_dev_init(void)
134{
135 if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) {
136 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
137 return;
138 }
139
140 gpio_direction_input(ts_gpio);
48feb337 141 gpio_set_debounce(ts_gpio, 310);
6fdc29e2
SMK		 142}
143
144static int ads7846_get_pendown_state(void)
145{
146 return !gpio_get_value(ts_gpio);
147}
148
149static struct ads7846_platform_data tsc2046_config __initdata = {
150 .get_pendown_state = ads7846_get_pendown_state,
151 .keep_vref_on = 1,
7a44ad2f 152 .wakeup = true,
6fdc29e2
SMK		 153};
154
155
156static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
157 .turbo_mode = 0,
158 .single_channel = 1, /* 0: slave, 1: master */
159};
160
161static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
162 [0] = {
163 /*
164 * TSC2046 operates at a max freqency of 2MHz, so
165 * operate slightly below at 1.5MHz
166 */
167 .modalias = "ads7846",
168 .bus_num = 1,
169 .chip_select = 0,
170 .max_speed_hz = 1500000,
171 .controller_data = &tsc2046_mcspi_config,
172 .irq = 0,
173 .platform_data = &tsc2046_config,
174 },
175};
176
d9056ce2
TV		 177
178#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
179#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
180
181static unsigned backlight_gpio;
182static unsigned enable_gpio;
183static int lcd_enabled;
184static int dvi_enabled;
185
186static void __init sdp3430_display_init(void)
187{
188 int r;
189
190 enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
191 backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
192
193 r = gpio_request(enable_gpio, "LCD reset");
194 if (r) {
195 printk(KERN_ERR "failed to get LCD reset GPIO\n");
196 goto err0;
197 }
198
199 r = gpio_request(backlight_gpio, "LCD Backlight");
200 if (r) {
201 printk(KERN_ERR "failed to get LCD backlight GPIO\n");
202 goto err1;
203 }
204
205 gpio_direction_output(enable_gpio, 0);
206 gpio_direction_output(backlight_gpio, 0);
207
208 return;
209err1:
210 gpio_free(enable_gpio);
211err0:
212 return;
213}
214
215static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
216{
217 if (dvi_enabled) {
218 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
219 return -EINVAL;
220 }
221
222 gpio_direction_output(enable_gpio, 1);
223 gpio_direction_output(backlight_gpio, 1);
224
225 lcd_enabled = 1;
226
227 return 0;
228}
229
230static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
231{
232 lcd_enabled = 0;
233
234 gpio_direction_output(enable_gpio, 0);
235 gpio_direction_output(backlight_gpio, 0);
236}
237
238static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
239{
240 if (lcd_enabled) {
241 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
242 return -EINVAL;
243 }
244
245 dvi_enabled = 1;
246
247 return 0;
248}
249
250static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
251{
252 dvi_enabled = 0;
253}
254
255static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
256{
257 return 0;
258}
259
260static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
261{
262}
263
264
265static struct omap_dss_device sdp3430_lcd_device = {
266 .name = "lcd",
267 .driver_name = "sharp_ls_panel",
268 .type = OMAP_DISPLAY_TYPE_DPI,
269 .phy.dpi.data_lines = 16,
270 .platform_enable = sdp3430_panel_enable_lcd,
271 .platform_disable = sdp3430_panel_disable_lcd,
6fdc29e2
SMK		 272};
273
89747c91
BW		 274static struct panel_generic_dpi_data dvi_panel = {
275 .name = "generic",
276 .platform_enable = sdp3430_panel_enable_dvi,
277 .platform_disable = sdp3430_panel_disable_dvi,
278};
279
d9056ce2
TV		 280static struct omap_dss_device sdp3430_dvi_device = {
281 .name = "dvi",
d9056ce2 282 .type = OMAP_DISPLAY_TYPE_DPI,
89747c91
BW		 283 .driver_name = "generic_dpi_panel",
284 .data = &dvi_panel,
d9056ce2 285 .phy.dpi.data_lines = 24,
6fdc29e2
SMK		 286};
287
d9056ce2
TV		 288static struct omap_dss_device sdp3430_tv_device = {
289 .name = "tv",
290 .driver_name = "venc",
291 .type = OMAP_DISPLAY_TYPE_VENC,
292 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
293 .platform_enable = sdp3430_panel_enable_tv,
294 .platform_disable = sdp3430_panel_disable_tv,
6fdc29e2
SMK		 295};
296
d9056ce2
TV		 297
298static struct omap_dss_device *sdp3430_dss_devices[] = {
6fdc29e2 299 &sdp3430_lcd_device,
d9056ce2
TV		 300 &sdp3430_dvi_device,
301 &sdp3430_tv_device,
6fdc29e2
SMK		 302};
303
d9056ce2
TV		 304static struct omap_dss_board_info sdp3430_dss_data = {
305 .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
306 .devices = sdp3430_dss_devices,
307 .default_device = &sdp3430_lcd_device,
308};
309
6fdc29e2 310static struct omap_board_config_kernel sdp3430_config[] __initdata = {
6fdc29e2
SMK		 311};
312
3dc3bad6 313static void __init omap_3430sdp_init_early(void)
b3c6df3a 314{
4805734b
PW		 315 omap2_init_common_infrastructure();
316 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
b3c6df3a
PW		 317}
318
6fdc29e2
SMK		 319static int sdp3430_batt_table[] = {
320/* 0 C*/
32130800, 29500, 28300, 27100,
32226000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
32317200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
32411600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
3258020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
3265640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
3274040, 3910, 3790, 3670, 3550
328};
329
330static struct twl4030_bci_platform_data sdp3430_bci_data = {
331 .battery_tmp_tbl = sdp3430_batt_table,
332 .tblsize = ARRAY_SIZE(sdp3430_batt_table),
333};
334
68ff0423 335static struct omap2_hsmmc_info mmc[] = {
6fdc29e2
SMK		 336 {
337 .mmc = 1,
338 /* 8 bits (default) requires S6.3 == ON,
339 * so the SIM card isn't used; else 4 bits.
340 */
3a63833e 341 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
6fdc29e2
SMK		 342 .gpio_wp = 4,
343 },
344 {
345 .mmc = 2,
3a63833e 346 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
6fdc29e2
SMK		 347 .gpio_wp = 7,
348 },
349 {} /* Terminator */
350};
351
6fdc29e2
SMK		 352static int sdp3430_twl_gpio_setup(struct device *dev,
353 unsigned gpio, unsigned ngpio)
354{
355 /* gpio + 0 is "mmc0_cd" (input/IRQ),
356 * gpio + 1 is "mmc1_cd" (input/IRQ)
357 */
358 mmc[0].gpio_cd = gpio + 0;
359 mmc[1].gpio_cd = gpio + 1;
68ff0423 360 omap2_hsmmc_init(mmc);
6fdc29e2 361
6fdc29e2
SMK		 362 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
363 gpio_request(gpio + 7, "sub_lcd_en_bkl");
364 gpio_direction_output(gpio + 7, 0);
365
366 /* gpio + 15 is "sub_lcd_nRST" (output) */
367 gpio_request(gpio + 15, "sub_lcd_nRST");
368 gpio_direction_output(gpio + 15, 0);
369
370 return 0;
371}
372
373static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
374 .gpio_base = OMAP_MAX_GPIO_LINES,
375 .irq_base = TWL4030_GPIO_IRQ_BASE,
376 .irq_end = TWL4030_GPIO_IRQ_END,
377 .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
378 | BIT(16) | BIT(17),
379 .setup = sdp3430_twl_gpio_setup,
380};
381
382static struct twl4030_usb_data sdp3430_usb_data = {
383 .usb_mode = T2_USB_MODE_ULPI,
384};
385
386static struct twl4030_madc_platform_data sdp3430_madc_data = {
387 .irq_line = 1,
388};
389
73a92aa4
RN		 390/* regulator consumer mappings */
391
4b087ff8
RN		 392/* ads7846 on SPI */
393static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
394 REGULATOR_SUPPLY("vcc", "spi1.0"),
395};
396
73a92aa4 397static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
30ea50c9 398 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
73a92aa4
RN		 399};
400
401/* VPLL2 for digital video outputs */
402static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
403 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
c8aac01b 404 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
73a92aa4
RN		 405};
406
407static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
0005ae73 408 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
73a92aa4
RN		 409};
410
411static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
0005ae73 412 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
73a92aa4
RN		 413};
414
415static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
0005ae73 416 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
73a92aa4
RN		 417};
418
6fdc29e2
SMK		 419/*
420 * Apply all the fixed voltages since most versions of U-Boot
421 * don't bother with that initialization.
422 */
423
424/* VAUX1 for mainboard (irda and sub-lcd) */
425static struct regulator_init_data sdp3430_vaux1 = {
426 .constraints = {
427 .min_uV = 2800000,
428 .max_uV = 2800000,
429 .apply_uV = true,
430 .valid_modes_mask = REGULATOR_MODE_NORMAL
431 | REGULATOR_MODE_STANDBY,
432 .valid_ops_mask = REGULATOR_CHANGE_MODE
433 | REGULATOR_CHANGE_STATUS,
434 },
435};
436
437/* VAUX2 for camera module */
438static struct regulator_init_data sdp3430_vaux2 = {
439 .constraints = {
440 .min_uV = 2800000,
441 .max_uV = 2800000,
442 .apply_uV = true,
443 .valid_modes_mask = REGULATOR_MODE_NORMAL
444 | REGULATOR_MODE_STANDBY,
445 .valid_ops_mask = REGULATOR_CHANGE_MODE
446 | REGULATOR_CHANGE_STATUS,
447 },
448};
449
450/* VAUX3 for LCD board */
451static struct regulator_init_data sdp3430_vaux3 = {
452 .constraints = {
453 .min_uV = 2800000,
454 .max_uV = 2800000,
455 .apply_uV = true,
456 .valid_modes_mask = REGULATOR_MODE_NORMAL
457 | REGULATOR_MODE_STANDBY,
458 .valid_ops_mask = REGULATOR_CHANGE_MODE
459 | REGULATOR_CHANGE_STATUS,
460 },
4b087ff8
RN		 461 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
462 .consumer_supplies = sdp3430_vaux3_supplies,
6fdc29e2
SMK		 463};
464
465/* VAUX4 for OMAP VDD_CSI2 (camera) */
466static struct regulator_init_data sdp3430_vaux4 = {
467 .constraints = {
468 .min_uV = 1800000,
469 .max_uV = 1800000,
470 .apply_uV = true,
471 .valid_modes_mask = REGULATOR_MODE_NORMAL
472 | REGULATOR_MODE_STANDBY,
473 .valid_ops_mask = REGULATOR_CHANGE_MODE
474 | REGULATOR_CHANGE_STATUS,
475 },
476};
477
478/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
479static struct regulator_init_data sdp3430_vmmc1 = {
480 .constraints = {
481 .min_uV = 1850000,
482 .max_uV = 3150000,
483 .valid_modes_mask = REGULATOR_MODE_NORMAL
484 | REGULATOR_MODE_STANDBY,
485 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
486 | REGULATOR_CHANGE_MODE
487 | REGULATOR_CHANGE_STATUS,
488 },
73a92aa4
RN		 489 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
490 .consumer_supplies = sdp3430_vmmc1_supplies,
6fdc29e2
SMK		 491};
492
493/* VMMC2 for MMC2 card */
494static struct regulator_init_data sdp3430_vmmc2 = {
495 .constraints = {
496 .min_uV = 1850000,
497 .max_uV = 1850000,
498 .apply_uV = true,
499 .valid_modes_mask = REGULATOR_MODE_NORMAL
500 | REGULATOR_MODE_STANDBY,
501 .valid_ops_mask = REGULATOR_CHANGE_MODE
502 | REGULATOR_CHANGE_STATUS,
503 },
73a92aa4
RN		 504 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
505 .consumer_supplies = sdp3430_vmmc2_supplies,
6fdc29e2
SMK		 506};
507
508/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
509static struct regulator_init_data sdp3430_vsim = {
510 .constraints = {
511 .min_uV = 1800000,
512 .max_uV = 3000000,
513 .valid_modes_mask = REGULATOR_MODE_NORMAL
514 | REGULATOR_MODE_STANDBY,
515 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
516 | REGULATOR_CHANGE_MODE
517 | REGULATOR_CHANGE_STATUS,
518 },
73a92aa4
RN		 519 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
520 .consumer_supplies = sdp3430_vsim_supplies,
6fdc29e2
SMK		 521};
522
523/* VDAC for DSS driving S-Video */
524static struct regulator_init_data sdp3430_vdac = {
525 .constraints = {
526 .min_uV = 1800000,
527 .max_uV = 1800000,
528 .apply_uV = true,
529 .valid_modes_mask = REGULATOR_MODE_NORMAL
530 | REGULATOR_MODE_STANDBY,
531 .valid_ops_mask = REGULATOR_CHANGE_MODE
532 | REGULATOR_CHANGE_STATUS,
533 },
73a92aa4
RN		 534 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
535 .consumer_supplies = sdp3430_vdda_dac_supplies,
d9056ce2
TV		 536};
537
6fdc29e2
SMK		 538static struct regulator_init_data sdp3430_vpll2 = {
539 .constraints = {
540 .name = "VDVI",
541 .min_uV = 1800000,
542 .max_uV = 1800000,
d9056ce2 543 .apply_uV = true,
6fdc29e2
SMK		 544 .valid_modes_mask = REGULATOR_MODE_NORMAL
545 | REGULATOR_MODE_STANDBY,
546 .valid_ops_mask = REGULATOR_CHANGE_MODE
547 | REGULATOR_CHANGE_STATUS,
548 },
d9056ce2
TV		 549 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
550 .consumer_supplies = sdp3430_vpll2_supplies,
6fdc29e2
SMK		 551};
552
6a58baf8 553static struct twl4030_codec_audio_data sdp3430_audio;
e86fa0b4
PU		 554
555static struct twl4030_codec_data sdp3430_codec = {
6df74efb 556 .audio_mclk = 26000000,
e86fa0b4
PU		 557 .audio = &sdp3430_audio,
558};
559
6fdc29e2
SMK		 560static struct twl4030_platform_data sdp3430_twldata = {
561 .irq_base = TWL4030_IRQ_BASE,
562 .irq_end = TWL4030_IRQ_END,
563
564 /* platform_data for children goes here */
565 .bci = &sdp3430_bci_data,
566 .gpio = &sdp3430_gpio_data,
567 .madc = &sdp3430_madc_data,
568 .keypad = &sdp3430_kp_data,
569 .usb = &sdp3430_usb_data,
e86fa0b4 570 .codec = &sdp3430_codec,
6fdc29e2
SMK		 571
572 .vaux1 = &sdp3430_vaux1,
573 .vaux2 = &sdp3430_vaux2,
574 .vaux3 = &sdp3430_vaux3,
575 .vaux4 = &sdp3430_vaux4,
576 .vmmc1 = &sdp3430_vmmc1,
577 .vmmc2 = &sdp3430_vmmc2,
578 .vsim = &sdp3430_vsim,
579 .vdac = &sdp3430_vdac,
580 .vpll2 = &sdp3430_vpll2,
581};
582
583static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = {
584 {
585 I2C_BOARD_INFO("twl4030", 0x48),
586 .flags = I2C_CLIENT_WAKE,
587 .irq = INT_34XX_SYS_NIRQ,
588 .platform_data = &sdp3430_twldata,
589 },
590};
591
592static int __init omap3430_i2c_init(void)
593{
594 /* i2c1 for PMIC only */
595 omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo,
596 ARRAY_SIZE(sdp3430_i2c_boardinfo));
597 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
598 omap_register_i2c_bus(2, 400, NULL, 0);
599 /* i2c3 on display connector (for DVI, tfp410) */
600 omap_register_i2c_bus(3, 400, NULL, 0);
601 return 0;
602}
603
1a48e157
TL		 604#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
605
606static struct omap_smc91x_platform_data board_smc91x_data = {
607 .cs = 3,
608 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
609 IORESOURCE_IRQ_LOWLEVEL,
610};
611
612static void __init board_smc91x_init(void)
613{
614 if (omap_rev() > OMAP3430_REV_ES1_0)
615 board_smc91x_data.gpio_irq = 6;
616 else
617 board_smc91x_data.gpio_irq = 29;
618
619 gpmc_smc91x_init(&board_smc91x_data);
620}
621
622#else
623
624static inline void board_smc91x_init(void)
625{
626}
627
628#endif
629
5110b298
RT		 630static void enable_board_wakeup_source(void)
631{
4896e394
TL		 632 /* T2 interrupt line (keypad) */
633 omap_mux_init_signal("sys_nirq",
634 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
5110b298
RT		 635}
636
181b250c 637static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
58a5491c 638
181b250c
KM		 639 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
640 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
641 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 642
643 .phy_reset = true,
644 .reset_gpio_port[0] = 57,
645 .reset_gpio_port[1] = 61,
646 .reset_gpio_port[2] = -EINVAL
647};
648
ca5742bd
TL		 649#ifdef CONFIG_OMAP_MUX
650static struct omap_board_mux board_mux[] __initdata = {
651 { .reg_offset = OMAP_MUX_TERMINATOR },
652};
626dda8a
S		 653
654static struct omap_device_pad serial1_pads[] __initdata = {
655 /*
656 * Note that off output enable is an active low
657 * signal. So setting this means pin is a
658 * input enabled in off mode
659 */
660 OMAP_MUX_STATIC("uart1_cts.uart1_cts",
661 OMAP_PIN_INPUT |
662 OMAP_PIN_OFF_INPUT_PULLDOWN |
663 OMAP_OFFOUT_EN |
664 OMAP_MUX_MODE0),
665 OMAP_MUX_STATIC("uart1_rts.uart1_rts",
666 OMAP_PIN_OUTPUT |
667 OMAP_OFF_EN |
668 OMAP_MUX_MODE0),
669 OMAP_MUX_STATIC("uart1_rx.uart1_rx",
670 OMAP_PIN_INPUT |
671 OMAP_PIN_OFF_INPUT_PULLDOWN |
672 OMAP_OFFOUT_EN |
673 OMAP_MUX_MODE0),
674 OMAP_MUX_STATIC("uart1_tx.uart1_tx",
675 OMAP_PIN_OUTPUT |
676 OMAP_OFF_EN |
677 OMAP_MUX_MODE0),
678};
679
680static struct omap_device_pad serial2_pads[] __initdata = {
681 OMAP_MUX_STATIC("uart2_cts.uart2_cts",
682 OMAP_PIN_INPUT_PULLUP |
683 OMAP_PIN_OFF_INPUT_PULLDOWN |
684 OMAP_OFFOUT_EN |
685 OMAP_MUX_MODE0),
686 OMAP_MUX_STATIC("uart2_rts.uart2_rts",
687 OMAP_PIN_OUTPUT |
688 OMAP_OFF_EN |
689 OMAP_MUX_MODE0),
690 OMAP_MUX_STATIC("uart2_rx.uart2_rx",
691 OMAP_PIN_INPUT |
692 OMAP_PIN_OFF_INPUT_PULLDOWN |
693 OMAP_OFFOUT_EN |
694 OMAP_MUX_MODE0),
695 OMAP_MUX_STATIC("uart2_tx.uart2_tx",
696 OMAP_PIN_OUTPUT |
697 OMAP_OFF_EN |
698 OMAP_MUX_MODE0),
699};
700
701static struct omap_device_pad serial3_pads[] __initdata = {
702 OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
703 OMAP_PIN_INPUT_PULLDOWN |
704 OMAP_PIN_OFF_INPUT_PULLDOWN |
705 OMAP_OFFOUT_EN |
706 OMAP_MUX_MODE0),
707 OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
708 OMAP_PIN_OUTPUT |
709 OMAP_OFF_EN |
710 OMAP_MUX_MODE0),
711 OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
712 OMAP_PIN_INPUT |
713 OMAP_PIN_OFF_INPUT_PULLDOWN |
714 OMAP_OFFOUT_EN |
715 OMAP_MUX_MODE0),
716 OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
717 OMAP_PIN_OUTPUT |
718 OMAP_OFF_EN |
719 OMAP_MUX_MODE0),
720};
721
722static struct omap_board_data serial1_data = {
723 .id = 0,
724 .pads = serial1_pads,
725 .pads_cnt = ARRAY_SIZE(serial1_pads),
726};
727
728static struct omap_board_data serial2_data = {
729 .id = 1,
730 .pads = serial2_pads,
731 .pads_cnt = ARRAY_SIZE(serial2_pads),
732};
733
734static struct omap_board_data serial3_data = {
735 .id = 2,
736 .pads = serial3_pads,
737 .pads_cnt = ARRAY_SIZE(serial3_pads),
738};
739
740static inline void board_serial_init(void)
741{
742 omap_serial_init_port(&serial1_data);
743 omap_serial_init_port(&serial2_data);
744 omap_serial_init_port(&serial3_data);
745}
746#else
747#define board_mux NULL
748
749static inline void board_serial_init(void)
750{
751 omap_serial_init();
752}
ca5742bd
TL		 753#endif
754
13d6b73c
SG		 755/*
756 * SDP3430 V2 Board CS organization
757 * Different from SDP3430 V1. Now 4 switches used to specify CS
758 *
759 * See also the Switch S8 settings in the comments.
760 */
761static char chip_sel_3430[][GPMC_CS_NUM] = {
762 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
763 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
764 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
765};
766
88c8460a
VS		 767static struct mtd_partition sdp_nor_partitions[] = {
768 /* bootloader (U-Boot, etc) in first sector */
769 {
770 .name = "Bootloader-NOR",
771 .offset = 0,
772 .size = SZ_256K,
773 .mask_flags = MTD_WRITEABLE, /* force read-only */
774 },
775 /* bootloader params in the next sector */
776 {
777 .name = "Params-NOR",
778 .offset = MTDPART_OFS_APPEND,
779 .size = SZ_256K,
780 .mask_flags = 0,
781 },
782 /* kernel */
783 {
784 .name = "Kernel-NOR",
785 .offset = MTDPART_OFS_APPEND,
786 .size = SZ_2M,
787 .mask_flags = 0
788 },
789 /* file system */
790 {
791 .name = "Filesystem-NOR",
792 .offset = MTDPART_OFS_APPEND,
793 .size = MTDPART_SIZ_FULL,
794 .mask_flags = 0
795 }
796};
797
798static struct mtd_partition sdp_onenand_partitions[] = {
799 {
800 .name = "X-Loader-OneNAND",
801 .offset = 0,
802 .size = 4 * (64 * 2048),
803 .mask_flags = MTD_WRITEABLE /* force read-only */
804 },
805 {
806 .name = "U-Boot-OneNAND",
807 .offset = MTDPART_OFS_APPEND,
808 .size = 2 * (64 * 2048),
809 .mask_flags = MTD_WRITEABLE /* force read-only */
810 },
811 {
812 .name = "U-Boot Environment-OneNAND",
813 .offset = MTDPART_OFS_APPEND,
814 .size = 1 * (64 * 2048),
815 },
816 {
817 .name = "Kernel-OneNAND",
818 .offset = MTDPART_OFS_APPEND,
819 .size = 16 * (64 * 2048),
820 },
821 {
822 .name = "File System-OneNAND",
823 .offset = MTDPART_OFS_APPEND,
824 .size = MTDPART_SIZ_FULL,
825 },
826};
827
828static struct mtd_partition sdp_nand_partitions[] = {
829 /* All the partition sizes are listed in terms of NAND block size */
830 {
831 .name = "X-Loader-NAND",
832 .offset = 0,
833 .size = 4 * (64 * 2048),
834 .mask_flags = MTD_WRITEABLE, /* force read-only */
835 },
836 {
837 .name = "U-Boot-NAND",
838 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
839 .size = 10 * (64 * 2048),
840 .mask_flags = MTD_WRITEABLE, /* force read-only */
841 },
842 {
843 .name = "Boot Env-NAND",
844
845 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
846 .size = 6 * (64 * 2048),
847 },
848 {
849 .name = "Kernel-NAND",
850 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
851 .size = 40 * (64 * 2048),
852 },
853 {
854 .name = "File System - NAND",
855 .size = MTDPART_SIZ_FULL,
856 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
857 },
858};
859
860static struct flash_partitions sdp_flash_partitions[] = {
861 {
862 .parts = sdp_nor_partitions,
863 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
864 },
865 {
866 .parts = sdp_onenand_partitions,
867 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
868 },
869 {
870 .parts = sdp_nand_partitions,
871 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
872 },
873};
874
884b8369
MM		 875static struct omap_musb_board_data musb_board_data = {
876 .interface_type = MUSB_INTERFACE_ULPI,
877 .mode = MUSB_OTG,
878 .power = 100,
879};
880
6fdc29e2
SMK		 881static void __init omap_3430sdp_init(void)
882{
ca5742bd 883 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
e41cccfe
TL		 884 omap_board_config = sdp3430_config;
885 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
886 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
6fdc29e2 887 omap3430_i2c_init();
d5e13227 888 omap_display_init(&sdp3430_dss_data);
6fdc29e2
SMK		 889 if (omap_rev() > OMAP3430_REV_ES1_0)
890 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
891 else
892 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1;
893 sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
894 spi_register_board_info(sdp3430_spi_board_info,
895 ARRAY_SIZE(sdp3430_spi_board_info));
896 ads7846_dev_init();
626dda8a 897 board_serial_init();
884b8369 898 usb_musb_init(&musb_board_data);
1a48e157 899 board_smc91x_init();
d5ce2b65 900 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
d9056ce2 901 sdp3430_display_init();
5110b298 902 enable_board_wakeup_source();
9e64bb1e 903 usbhs_init(&usbhs_bdata);
6fdc29e2
SMK		 904}
905
6fdc29e2
SMK		 906MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
907 /* Maintainer: Syed Khasim - Texas Instruments Inc */
6fdc29e2 908 .boot_params = 0x80000100,
71ee7dad 909 .reserve = omap_reserve,
3dc3bad6
RKAL		 910 .map_io = omap3_map_io,
911 .init_early = omap_3430sdp_init_early,
912 .init_irq = omap_init_irq,
6fdc29e2
SMK		 913 .init_machine = omap_3430sdp_init,
914 .timer = &omap_timer,
915MACHINE_END
Linux kernel - Deliverables
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