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Merge tag 'stable/for-linus-3.8-rc0-bugfix-tag' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31 26
dc42c8bd
ZC		 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
53c5ec31
SMK		 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
ebeb53e1 33#include <linux/i2c/twl.h>
e8e2ff46 34#include <linux/usb/otg.h>
e8c4a7ac 35#include <linux/usb/musb.h>
78c289f8 36#include <linux/usb/nop-usb-xceiv.h>
562138a4 37#include <linux/smsc911x.h>
53c5ec31 38
741927f7
ER		 39#include <linux/wl12xx.h>
40#include <linux/regulator/fixed.h>
1a7ec135 41#include <linux/regulator/machine.h>
3a63833e 42#include <linux/mmc/host.h>
dc28094b 43#include <linux/export.h>
1a7ec135 44
53c5ec31
SMK		 45#include <asm/mach-types.h>
46#include <asm/mach/arch.h>
47#include <asm/mach/map.h>
48
2203747c 49#include <linux/platform_data/mtd-nand-omap2.h>
4e65331c 50#include "common.h"
2203747c 51#include <linux/platform_data/spi-omap2-mcspi.h>
a0b38cc4 52#include <video/omapdss.h>
dac8eb5f 53#include <video/omap-panel-tfp410.h>
53c5ec31 54
e4c060db 55#include "soc.h"
ca5742bd 56#include "mux.h"
53c5ec31 57#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 58#include "hsmmc.h"
96974a24 59#include "common-board-devices.h"
2e618261
AM		 60#include "board-flash.h"
61
62#define NAND_CS 0
53c5ec31 63
c31cc1b7 64#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 65#define OMAP3_EVM_EHCI_VBUS 22
66#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 67
68#define OMAP3EVM_ETHR_START 0x2c000000
69#define OMAP3EVM_ETHR_SIZE 1024
db408023 70#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 71#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 72#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 73/*
74 * Eth Reset signal
75 * 64 = Generation 1 (<=RevD)
76 * 7 = Generation 2 (>=RevE)
77 */
78#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
79#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 80
e54adb1e
IG		 81/*
82 * OMAP35x EVM revision
83 * Run time detection of EVM revision is done by reading Ethernet
84 * PHY ID -
85 * GEN_1 = 0x01150000
86 * GEN_2 = 0x92200000
87 */
88enum {
89 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
90 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
91};
92
db408023
AKG		 93static u8 omap3_evm_version;
94
695f0117 95static u8 get_omap3_evm_rev(void)
db408023
AKG		 96{
97 return omap3_evm_version;
98}
db408023
AKG		 99
100static void __init omap3_evm_get_revision(void)
101{
102 void __iomem *ioaddr;
103 unsigned int smsc_id;
104
105 /* Ethernet PHY ID is stored at ID_REV register */
106 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
107 if (!ioaddr)
108 return;
109 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
110 iounmap(ioaddr);
111
112 switch (smsc_id) {
113 /*SMSC9115 chipset*/
114 case 0x01150000:
115 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
116 break;
117 /*SMSC 9220 chipset*/
118 case 0x92200000:
119 default:
120 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
121 }
122}
123
562138a4 124#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
ac839b3c 125#include "gpmc-smsc911x.h"
53c5ec31 126
21b42731
MR		 127static struct omap_smsc911x_platform_data smsc911x_cfg = {
128 .cs = OMAP3EVM_SMSC911X_CS,
129 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
130 .gpio_reset = -EINVAL,
131 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 132};
133
562138a4 134static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 135{
9bc64b89
VH		 136 /* Configure ethernet controller reset gpio */
137 if (cpu_is_omap3430()) {
21b42731
MR		 138 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
139 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
140 else
141 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 142 }
143
21b42731 144 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 145}
146
562138a4
S		 147#else
148static inline void __init omap3evm_init_smsc911x(void) { return; }
149#endif
150
703e3061
VH		 151/*
152 * OMAP3EVM LCD Panel control signals
153 */
154#define OMAP3EVM_LCD_PANEL_LR 2
155#define OMAP3EVM_LCD_PANEL_UD 3
156#define OMAP3EVM_LCD_PANEL_INI 152
157#define OMAP3EVM_LCD_PANEL_ENVDD 153
158#define OMAP3EVM_LCD_PANEL_QVGA 154
159#define OMAP3EVM_LCD_PANEL_RESB 155
160#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
161#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
162
bc593f5d
IG		 163static struct gpio omap3_evm_dss_gpios[] __initdata = {
164 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
165 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
166 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
167 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
168 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
169 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
170};
171
703e3061
VH		 172static int lcd_enabled;
173static int dvi_enabled;
174
175static void __init omap3_evm_display_init(void)
176{
177 int r;
178
bc593f5d
IG		 179 r = gpio_request_array(omap3_evm_dss_gpios,
180 ARRAY_SIZE(omap3_evm_dss_gpios));
181 if (r)
182 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 183}
184
185static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
186{
187 if (dvi_enabled) {
188 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
189 return -EINVAL;
190 }
191 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
192
193 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 194 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 195 else
f186e9b2 196 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 197
198 lcd_enabled = 1;
199 return 0;
200}
201
202static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
203{
204 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
205
206 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 207 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 208 else
f186e9b2 209 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 210
211 lcd_enabled = 0;
212}
213
214static struct omap_dss_device omap3_evm_lcd_device = {
215 .name = "lcd",
216 .driver_name = "sharp_ls_panel",
217 .type = OMAP_DISPLAY_TYPE_DPI,
218 .phy.dpi.data_lines = 18,
219 .platform_enable = omap3_evm_enable_lcd,
220 .platform_disable = omap3_evm_disable_lcd,
221};
222
223static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
224{
225 return 0;
226}
227
228static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
229{
230}
231
232static struct omap_dss_device omap3_evm_tv_device = {
233 .name = "tv",
234 .driver_name = "venc",
235 .type = OMAP_DISPLAY_TYPE_VENC,
236 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
237 .platform_enable = omap3_evm_enable_tv,
238 .platform_disable = omap3_evm_disable_tv,
239};
240
2e6f2ee7 241static struct tfp410_platform_data dvi_panel = {
e813a55e 242 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
89747c91
BW		 243};
244
703e3061
VH		 245static struct omap_dss_device omap3_evm_dvi_device = {
246 .name = "dvi",
703e3061 247 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 248 .driver_name = "tfp410",
89747c91 249 .data = &dvi_panel,
703e3061 250 .phy.dpi.data_lines = 24,
703e3061
VH		 251};
252
253static struct omap_dss_device *omap3_evm_dss_devices[] = {
254 &omap3_evm_lcd_device,
255 &omap3_evm_tv_device,
256 &omap3_evm_dvi_device,
257};
258
259static struct omap_dss_board_info omap3_evm_dss_data = {
260 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
261 .devices = omap3_evm_dss_devices,
262 .default_device = &omap3_evm_lcd_device,
263};
264
786b01a8
OD		 265static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
266 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 267};
268
786b01a8
OD		 269static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
270 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 271};
272
273/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
274static struct regulator_init_data omap3evm_vmmc1 = {
275 .constraints = {
276 .min_uV = 1850000,
277 .max_uV = 3150000,
278 .valid_modes_mask = REGULATOR_MODE_NORMAL
279 | REGULATOR_MODE_STANDBY,
280 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
281 | REGULATOR_CHANGE_MODE
282 | REGULATOR_CHANGE_STATUS,
283 },
786b01a8
OD		 284 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
285 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 286};
287
288/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
289static struct regulator_init_data omap3evm_vsim = {
290 .constraints = {
291 .min_uV = 1800000,
292 .max_uV = 3000000,
293 .valid_modes_mask = REGULATOR_MODE_NORMAL
294 | REGULATOR_MODE_STANDBY,
295 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
296 | REGULATOR_CHANGE_MODE
297 | REGULATOR_CHANGE_STATUS,
298 },
786b01a8
OD		 299 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
300 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 301};
302
68ff0423 303static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 304 {
305 .mmc = 1,
3a63833e 306 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 307 .gpio_cd = -EINVAL,
308 .gpio_wp = 63,
3b972bf0 309 .deferred = true,
53c5ec31 310 },
741927f7
ER		 311#ifdef CONFIG_WL12XX_PLATFORM_DATA
312 {
313 .name = "wl1271",
aca6ad07 314 .mmc = 2,
741927f7
ER		 315 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
316 .gpio_wp = -EINVAL,
317 .gpio_cd = -EINVAL,
318 .nonremovable = true,
319 },
320#endif
53c5ec31
SMK		 321 {} /* Terminator */
322};
323
324static struct gpio_led gpio_leds[] = {
325 {
326 .name = "omap3evm::ledb",
327 /* normally not visible (board underside) */
328 .default_trigger = "default-on",
329 .gpio = -EINVAL, /* gets replaced */
330 .active_low = true,
331 },
332};
333
334static struct gpio_led_platform_data gpio_led_info = {
335 .leds = gpio_leds,
336 .num_leds = ARRAY_SIZE(gpio_leds),
337};
338
339static struct platform_device leds_gpio = {
340 .name = "leds-gpio",
341 .id = -1,
342 .dev = {
343 .platform_data = &gpio_led_info,
344 },
345};
346
347
348static int omap3evm_twl_gpio_setup(struct device *dev,
349 unsigned gpio, unsigned ngpio)
350{
bc593f5d 351 int r, lcd_bl_en;
42fc8cab 352
53c5ec31 353 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 354 mmc[0].gpio_cd = gpio + 0;
3b972bf0 355 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 356
357 /*
358 * Most GPIOs are for USB OTG. Some are mostly sent to
359 * the P2 connector; notably LEDA for the LCD backlight.
360 */
361
703e3061 362 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 363 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
364 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
365 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 366 if (r)
367 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 368
369 /* gpio + 7 == DVI Enable */
bc593f5d 370 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 371
53c5ec31 372 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 373 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 374
375 platform_device_register(&leds_gpio);
376
cb8ca589
ZC		 377 /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
378 * for starting USB tranceiver
379 */
b103a2e2 380#ifdef CONFIG_TWL4030_CORE
cb8ca589
ZC		 381 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
382 u8 val;
383
384 twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
385 val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
386 twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
387 }
b103a2e2 388#endif
cb8ca589 389
53c5ec31
SMK		 390 return 0;
391}
392
393static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
53c5ec31
SMK		 394 .use_leds = true,
395 .setup = omap3evm_twl_gpio_setup,
396};
397
bead4375 398static uint32_t board_keymap[] = {
53c5ec31 399 KEY(0, 0, KEY_LEFT),
0621d756
SP		 400 KEY(0, 1, KEY_DOWN),
401 KEY(0, 2, KEY_ENTER),
402 KEY(0, 3, KEY_M),
403
404 KEY(1, 0, KEY_RIGHT),
53c5ec31 405 KEY(1, 1, KEY_UP),
0621d756
SP		 406 KEY(1, 2, KEY_I),
407 KEY(1, 3, KEY_N),
408
409 KEY(2, 0, KEY_A),
410 KEY(2, 1, KEY_E),
53c5ec31 411 KEY(2, 2, KEY_J),
0621d756
SP		 412 KEY(2, 3, KEY_O),
413
414 KEY(3, 0, KEY_B),
415 KEY(3, 1, KEY_F),
416 KEY(3, 2, KEY_K),
53c5ec31
SMK		 417 KEY(3, 3, KEY_P)
418};
419
4f543332
TL		 420static struct matrix_keymap_data board_map_data = {
421 .keymap = board_keymap,
422 .keymap_size = ARRAY_SIZE(board_keymap),
423};
424
53c5ec31 425static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 426 .keymap_data = &board_map_data,
53c5ec31
SMK		 427 .rows = 4,
428 .cols = 4,
53c5ec31
SMK		 429 .rep = 1,
430};
431
410491d4 432/* ads7846 on SPI */
786b01a8
OD		 433static struct regulator_consumer_supply omap3evm_vio_supply[] = {
434 REGULATOR_SUPPLY("vcc", "spi1.0"),
435};
410491d4
VH		 436
437/* VIO for ads7846 */
438static struct regulator_init_data omap3evm_vio = {
439 .constraints = {
440 .min_uV = 1800000,
441 .max_uV = 1800000,
442 .apply_uV = true,
443 .valid_modes_mask = REGULATOR_MODE_NORMAL
444 | REGULATOR_MODE_STANDBY,
445 .valid_ops_mask = REGULATOR_CHANGE_MODE
446 | REGULATOR_CHANGE_STATUS,
447 },
786b01a8
OD		 448 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
449 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 450};
451
741927f7
ER		 452#ifdef CONFIG_WL12XX_PLATFORM_DATA
453
454#define OMAP3EVM_WLAN_PMENA_GPIO (150)
455#define OMAP3EVM_WLAN_IRQ_GPIO (149)
456
786b01a8 457static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 458 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 459};
741927f7
ER		 460
461/* VMMC2 for driving the WL12xx module */
462static struct regulator_init_data omap3evm_vmmc2 = {
463 .constraints = {
464 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
465 },
d19f579a 466 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 467 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 468};
469
470static struct fixed_voltage_config omap3evm_vwlan = {
471 .supply_name = "vwl1271",
472 .microvolts = 1800000, /* 1.80V */
473 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
474 .startup_delay = 70000, /* 70ms */
475 .enable_high = 1,
476 .enabled_at_boot = 0,
477 .init_data = &omap3evm_vmmc2,
478};
479
aca6ad07 480static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 481 .name = "reg-fixed-voltage",
482 .id = 1,
483 .dev = {
484 .platform_data = &omap3evm_vwlan,
485 },
486};
487
488struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 489 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 490};
491#endif
492
497af1f3
ZC		 493/* VAUX2 for USB */
494static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
495 REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
496 REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
497 REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
498 REGULATOR_SUPPLY("vaux2", NULL),
499};
500
501static struct regulator_init_data omap3evm_vaux2 = {
502 .constraints = {
503 .min_uV = 2800000,
504 .max_uV = 2800000,
505 .apply_uV = true,
506 .valid_modes_mask = REGULATOR_MODE_NORMAL
507 | REGULATOR_MODE_STANDBY,
508 .valid_ops_mask = REGULATOR_CHANGE_MODE
509 | REGULATOR_CHANGE_STATUS,
510 },
511 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies),
512 .consumer_supplies = omap3evm_vaux2_supplies,
513};
514
53c5ec31 515static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 516 /* platform_data for children goes here */
517 .keypad = &omap3evm_kp_data,
53c5ec31 518 .gpio = &omap3evm_gpio_data,
410491d4 519 .vio = &omap3evm_vio,
fbd8071c
MR		 520 .vmmc1 = &omap3evm_vmmc1,
521 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 522};
523
524static int __init omap3_evm_i2c_init(void)
525{
827ed9ae 526 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 527 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
528 TWL_COMMON_PDATA_AUDIO,
529 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
530
531 omap3evm_twldata.vdac->constraints.apply_uV = true;
532 omap3evm_twldata.vpll2->constraints.apply_uV = true;
533
fbd8071c 534 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 535 omap_register_i2c_bus(2, 400, NULL, 0);
536 omap_register_i2c_bus(3, 400, NULL, 0);
537 return 0;
538}
539
181b250c 540static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 541
181b250c
KM		 542 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
543 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
544 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 545
546 .phy_reset = true,
e8e51d29 547 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 548 .reset_gpio_port[0] = -EINVAL,
e8e51d29 549 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 550 .reset_gpio_port[2] = -EINVAL
551};
552
ca5742bd 553#ifdef CONFIG_OMAP_MUX
904c545c 554static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 555 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 556 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 557 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 558 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 559 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
560 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 561 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
562 OMAP_PIN_OFF_NONE),
563 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
564 OMAP_PIN_OFF_NONE),
741927f7
ER		 565#ifdef CONFIG_WL12XX_PLATFORM_DATA
566 /* WLAN IRQ - GPIO 149 */
aca6ad07 567 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 568
569 /* WLAN POWER ENABLE - GPIO 150 */
570 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
571
572 /* MMC2 SDIO pin muxes for WL12xx */
573 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
574 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
575 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
576 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
577 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
578 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
579#endif
ca5742bd
TL		 580 { .reg_offset = OMAP_MUX_TERMINATOR },
581};
904c545c
VH		 582
583static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 584 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 585 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 586 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 587 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 588 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
589 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 590 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
591 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
592 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
593 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
594 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
595 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
596 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
597 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
598 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
599 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
600 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
601 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
602 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 603#ifdef CONFIG_WL12XX_PLATFORM_DATA
604 /* WLAN IRQ - GPIO 149 */
605 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
606
607 /* WLAN POWER ENABLE - GPIO 150 */
608 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
609
610 /* MMC2 SDIO pin muxes for WL12xx */
611 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
612 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
613 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
614 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
615 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
616 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
617#endif
904c545c 618
ca5742bd
TL		 619 { .reg_offset = OMAP_MUX_TERMINATOR },
620};
904c545c
VH		 621#else
622#define omap35x_board_mux NULL
623#define omap36x_board_mux NULL
ca5742bd
TL		 624#endif
625
884b8369
MM		 626static struct omap_musb_board_data musb_board_data = {
627 .interface_type = MUSB_INTERFACE_ULPI,
628 .mode = MUSB_OTG,
629 .power = 100,
630};
631
bc593f5d
IG		 632static struct gpio omap3_evm_ehci_gpios[] __initdata = {
633 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
634 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
635};
636
70d669de
RK		 637static void __init omap3_evm_wl12xx_init(void)
638{
639#ifdef CONFIG_WL12XX_PLATFORM_DATA
640 int ret;
641
642 /* WL12xx WLAN Init */
46a0a540 643 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 644 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
645 if (ret)
646 pr_err("error setting wl12xx data: %d\n", ret);
647 ret = platform_device_register(&omap3evm_wlan_regulator);
648 if (ret)
649 pr_err("error registering wl12xx device: %d\n", ret);
650#endif
651}
652
5b3689f4
RD		 653static struct regulator_consumer_supply dummy_supplies[] = {
654 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
655 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
656};
657
dc42c8bd
ZC		 658static struct mtd_partition omap3evm_nand_partitions[] = {
659 /* All the partition sizes are listed in terms of NAND block size */
660 {
661 .name = "X-Loader",
662 .offset = 0,
663 .size = 4*(SZ_128K),
664 .mask_flags = MTD_WRITEABLE
665 },
666 {
667 .name = "U-Boot",
668 .offset = MTDPART_OFS_APPEND,
669 .size = 14*(SZ_128K),
670 .mask_flags = MTD_WRITEABLE
671 },
672 {
673 .name = "U-Boot Env",
674 .offset = MTDPART_OFS_APPEND,
675 .size = 2*(SZ_128K)
676 },
677 {
678 .name = "Kernel",
679 .offset = MTDPART_OFS_APPEND,
680 .size = 40*(SZ_128K)
681 },
682 {
683 .name = "File system",
684 .size = MTDPART_SIZ_FULL,
685 .offset = MTDPART_OFS_APPEND,
686 },
687};
688
53c5ec31
SMK		 689static void __init omap3_evm_init(void)
690{
eeb3711b
PW		 691 struct omap_board_mux *obm;
692
db408023 693 omap3_evm_get_revision();
5b3689f4 694 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c 695
eeb3711b
PW		 696 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
697 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
db408023 698
d1589f09 699 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 700 omap_hsmmc_init(mmc);
d1589f09 701
497af1f3
ZC		 702 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
703 omap3evm_twldata.vaux2 = &omap3evm_vaux2;
704
53c5ec31
SMK		 705 omap3_evm_i2c_init();
706
d5e13227 707 omap_display_init(&omap3_evm_dss_data);
53c5ec31 708
53c5ec31 709 omap_serial_init();
a4ca9dbe 710 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 711
e8e2ff46
GAK		 712 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
713 usb_nop_xceiv_register();
1a4f4637 714
e8e51d29
AKG		 715 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
716 /* enable EHCI VBUS using GPIO22 */
bc593f5d 717 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 718 /* Select EHCI port on main board */
bc593f5d
IG		 719 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
720 OMAP_PIN_INPUT_PULLUP);
721 gpio_request_array(omap3_evm_ehci_gpios,
722 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 723
724 /* setup EHCI phy reset config */
4896e394 725 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 726 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 727
58815fa3
AKG		 728 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
729 musb_board_data.power = 500;
730 musb_board_data.extvbus = 1;
e8e51d29
AKG		 731 } else {
732 /* setup EHCI phy reset on MDC */
4896e394 733 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 734 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 735 }
884b8369 736 usb_musb_init(&musb_board_data);
9e64bb1e 737 usbhs_init(&usbhs_bdata);
2e618261
AM		 738 board_nand_init(omap3evm_nand_partitions,
739 ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
740 NAND_BUSWIDTH_16, NULL);
dc42c8bd 741
96974a24 742 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 743 omap3evm_init_smsc911x();
703e3061 744 omap3_evm_display_init();
70d669de 745 omap3_evm_wl12xx_init();
ac51c90f 746 omap_twl4030_audio_init("omap3evm");
53c5ec31
SMK		 747}
748
53c5ec31
SMK		 749MACHINE_START(OMAP3EVM, "OMAP3 EVM")
750 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 751 .atag_offset = 0x100,
71ee7dad 752 .reserve = omap_reserve,
3dc3bad6 753 .map_io = omap3_map_io,
8f5b5a41 754 .init_early = omap35xx_init_early,
741e3a89 755 .init_irq = omap3_init_irq,
6b2f55d7 756 .handle_irq = omap3_intc_handle_irq,
53c5ec31 757 .init_machine = omap3_evm_init,
bbd707ac 758 .init_late = omap35xx_init_late,
e74984e4 759 .timer = &omap3_timer,
187e3e06 760 .restart = omap3xxx_restart,
53c5ec31 761MACHINE_END
Linux kernel - Deliverables
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