Linux 3.3-rc1
[deliverable/linux.git] / arch / arm / mach-omap2 / board-rx51-peripherals.c
CommitLineData
ffe7f95b 1/*
9312fffb 2 * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
ffe7f95b
LL
3 *
4 * Copyright (C) 2008-2009 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/input.h>
6135434a 15#include <linux/input/matrix_keypad.h>
ffe7f95b 16#include <linux/spi/spi.h>
c1f9a095 17#include <linux/wl12xx.h>
3dad5356 18#include <linux/spi/tsc2005.h>
ffe7f95b 19#include <linux/i2c.h>
ebeb53e1 20#include <linux/i2c/twl.h>
ffe7f95b
LL
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/regulator/machine.h>
24#include <linux/gpio.h>
f014ee32 25#include <linux/gpio_keys.h>
5e763d29 26#include <linux/mmc/host.h>
10299e2e 27#include <linux/power/isp1704_charger.h>
ffe7f95b 28
ce491cf8 29#include <plat/mcspi.h>
ce491cf8 30#include <plat/board.h>
4e65331c 31#include "common.h"
ce491cf8
TL
32#include <plat/dma.h>
33#include <plat/gpmc.h>
ce491cf8
TL
34#include <plat/onenand.h>
35#include <plat/gpmc-smc91x.h>
ffe7f95b 36
04aeae77
MK
37#include <mach/board-rx51.h>
38
87581fd4 39#include <sound/tlv320aic3x.h>
64d06691 40#include <sound/tpa6130a2-plat.h>
589541c0
JN
41#include <media/radio-si4713.h>
42#include <media/si4713.h>
eeada9e8 43#include <linux/leds-lp5523.h>
87581fd4 44
70b5d737
MN
45#include <../drivers/staging/iio/light/tsl2563.h>
46
4896e394 47#include "mux.h"
d02a900b 48#include "hsmmc.h"
fbd8071c 49#include "common-board-devices.h"
ffe7f95b 50
f52eeee8
AH
51#define SYSTEM_REV_B_USES_VAUX3 0x1699
52#define SYSTEM_REV_S_USES_VAUX3 0x8
53
a24e61a9
KV
54#define RX51_WL1251_POWER_GPIO 87
55#define RX51_WL1251_IRQ_GPIO 42
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JN
56#define RX51_FMTX_RESET_GPIO 163
57#define RX51_FMTX_IRQ 53
eeada9e8 58#define RX51_LP5523_CHIP_EN_GPIO 41
a24e61a9 59
10299e2e
KJ
60#define RX51_USB_TRANSCEIVER_RST_GPIO 67
61
3dad5356
AK
62#define RX51_TSC2005_RESET_GPIO 104
63#define RX51_TSC2005_IRQ_GPIO 100
64
a24e61a9
KV
65/* list all spi devices here */
66enum {
67 RX51_SPI_WL1251,
03e11104 68 RX51_SPI_MIPID, /* LCD panel */
6996e7ff 69 RX51_SPI_TSC2005, /* Touch Controller */
a24e61a9
KV
70};
71
72static struct wl12xx_platform_data wl1251_pdata;
3dad5356 73static struct tsc2005_platform_data tsc2005_pdata;
a24e61a9 74
70b5d737
MN
75#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
76static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
77 .cover_comp_gain = 16,
78};
79#endif
80
eeada9e8
AP
81#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
82static struct lp5523_led_config rx51_lp5523_led_config[] = {
83 {
84 .chan_nr = 0,
85 .led_current = 50,
86 }, {
87 .chan_nr = 1,
88 .led_current = 50,
89 }, {
90 .chan_nr = 2,
91 .led_current = 50,
92 }, {
93 .chan_nr = 3,
94 .led_current = 50,
95 }, {
96 .chan_nr = 4,
97 .led_current = 50,
98 }, {
99 .chan_nr = 5,
100 .led_current = 50,
101 }, {
102 .chan_nr = 6,
103 .led_current = 50,
104 }, {
105 .chan_nr = 7,
106 .led_current = 50,
107 }, {
108 .chan_nr = 8,
109 .led_current = 50,
110 }
111};
112
113static int rx51_lp5523_setup(void)
114{
115 return gpio_request_one(RX51_LP5523_CHIP_EN_GPIO, GPIOF_DIR_OUT,
116 "lp5523_enable");
117}
118
119static void rx51_lp5523_release(void)
120{
121 gpio_free(RX51_LP5523_CHIP_EN_GPIO);
122}
123
124static void rx51_lp5523_enable(bool state)
125{
126 gpio_set_value(RX51_LP5523_CHIP_EN_GPIO, !!state);
127}
128
129static struct lp5523_platform_data rx51_lp5523_platform_data = {
130 .led_config = rx51_lp5523_led_config,
131 .num_channels = ARRAY_SIZE(rx51_lp5523_led_config),
132 .clock_mode = LP5523_CLOCK_AUTO,
133 .setup_resources = rx51_lp5523_setup,
134 .release_resources = rx51_lp5523_release,
135 .enable = rx51_lp5523_enable,
136};
137#endif
138
a24e61a9
KV
139static struct omap2_mcspi_device_config wl1251_mcspi_config = {
140 .turbo_mode = 0,
141 .single_channel = 1,
142};
143
03e11104
RQ
144static struct omap2_mcspi_device_config mipid_mcspi_config = {
145 .turbo_mode = 0,
146 .single_channel = 1,
147};
148
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RQ
149static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
150 .turbo_mode = 0,
151 .single_channel = 1,
152};
153
a24e61a9
KV
154static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
155 [RX51_SPI_WL1251] = {
156 .modalias = "wl1251",
157 .bus_num = 4,
158 .chip_select = 0,
159 .max_speed_hz = 48000000,
860fc976 160 .mode = SPI_MODE_3,
a24e61a9
KV
161 .controller_data = &wl1251_mcspi_config,
162 .platform_data = &wl1251_pdata,
163 },
03e11104
RQ
164 [RX51_SPI_MIPID] = {
165 .modalias = "acx565akm",
166 .bus_num = 1,
167 .chip_select = 2,
168 .max_speed_hz = 6000000,
169 .controller_data = &mipid_mcspi_config,
170 },
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RQ
171 [RX51_SPI_TSC2005] = {
172 .modalias = "tsc2005",
173 .bus_num = 1,
174 .chip_select = 0,
3dad5356 175 .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
6996e7ff
RQ
176 .max_speed_hz = 6000000,
177 .controller_data = &tsc2005_mcspi_config,
3dad5356 178 .platform_data = &tsc2005_pdata,
6996e7ff 179 },
a24e61a9
KV
180};
181
10299e2e
KJ
182static void rx51_charger_set_power(bool on)
183{
184 gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
185}
186
187static struct isp1704_charger_data rx51_charger_data = {
188 .set_power = rx51_charger_set_power,
189};
190
fd0964c5 191static struct platform_device rx51_charger_device = {
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KJ
192 .name = "isp1704_charger",
193 .dev = {
194 .platform_data = &rx51_charger_data,
195 },
fd0964c5
HK
196};
197
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KJ
198static void __init rx51_charger_init(void)
199{
200 WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
e5fe29c7 201 GPIOF_OUT_INIT_HIGH, "isp1704_reset"));
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202
203 platform_device_register(&rx51_charger_device);
204}
205
f014ee32
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206#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
207
208#define RX51_GPIO_CAMERA_LENS_COVER 110
209#define RX51_GPIO_CAMERA_FOCUS 68
210#define RX51_GPIO_CAMERA_CAPTURE 69
211#define RX51_GPIO_KEYPAD_SLIDE 71
212#define RX51_GPIO_LOCK_BUTTON 113
213#define RX51_GPIO_PROXIMITY 89
214
215#define RX51_GPIO_DEBOUNCE_TIMEOUT 10
216
217static struct gpio_keys_button rx51_gpio_keys[] = {
218 {
219 .desc = "Camera Lens Cover",
220 .type = EV_SW,
221 .code = SW_CAMERA_LENS_COVER,
222 .gpio = RX51_GPIO_CAMERA_LENS_COVER,
223 .active_low = 1,
224 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
225 }, {
226 .desc = "Camera Focus",
227 .type = EV_KEY,
228 .code = KEY_CAMERA_FOCUS,
229 .gpio = RX51_GPIO_CAMERA_FOCUS,
230 .active_low = 1,
231 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
232 }, {
233 .desc = "Camera Capture",
234 .type = EV_KEY,
235 .code = KEY_CAMERA,
236 .gpio = RX51_GPIO_CAMERA_CAPTURE,
237 .active_low = 1,
238 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
239 }, {
240 .desc = "Lock Button",
241 .type = EV_KEY,
242 .code = KEY_SCREENLOCK,
243 .gpio = RX51_GPIO_LOCK_BUTTON,
244 .active_low = 1,
245 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
246 }, {
247 .desc = "Keypad Slide",
248 .type = EV_SW,
249 .code = SW_KEYPAD_SLIDE,
250 .gpio = RX51_GPIO_KEYPAD_SLIDE,
251 .active_low = 1,
252 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
253 }, {
254 .desc = "Proximity Sensor",
255 .type = EV_SW,
256 .code = SW_FRONT_PROXIMITY,
257 .gpio = RX51_GPIO_PROXIMITY,
258 .active_low = 0,
259 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
260 }
261};
262
263static struct gpio_keys_platform_data rx51_gpio_keys_data = {
264 .buttons = rx51_gpio_keys,
265 .nbuttons = ARRAY_SIZE(rx51_gpio_keys),
266};
267
268static struct platform_device rx51_gpio_keys_device = {
269 .name = "gpio-keys",
270 .id = -1,
271 .dev = {
272 .platform_data = &rx51_gpio_keys_data,
273 },
274};
275
276static void __init rx51_add_gpio_keys(void)
277{
278 platform_device_register(&rx51_gpio_keys_device);
279}
280#else
281static void __init rx51_add_gpio_keys(void)
282{
283}
284#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
285
bead4375 286static uint32_t board_keymap[] = {
3fea6026
DT
287 /*
288 * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
289 * connected to the ground" matrix state.
290 */
ffe7f95b 291 KEY(0, 0, KEY_Q),
acf442dc
AK
292 KEY(0, 1, KEY_O),
293 KEY(0, 2, KEY_P),
294 KEY(0, 3, KEY_COMMA),
295 KEY(0, 4, KEY_BACKSPACE),
296 KEY(0, 6, KEY_A),
297 KEY(0, 7, KEY_S),
3fea6026 298
acf442dc 299 KEY(1, 0, KEY_W),
ffe7f95b 300 KEY(1, 1, KEY_D),
acf442dc
AK
301 KEY(1, 2, KEY_F),
302 KEY(1, 3, KEY_G),
303 KEY(1, 4, KEY_H),
304 KEY(1, 5, KEY_J),
305 KEY(1, 6, KEY_K),
306 KEY(1, 7, KEY_L),
3fea6026 307
acf442dc
AK
308 KEY(2, 0, KEY_E),
309 KEY(2, 1, KEY_DOT),
ffe7f95b 310 KEY(2, 2, KEY_UP),
acf442dc
AK
311 KEY(2, 3, KEY_ENTER),
312 KEY(2, 5, KEY_Z),
313 KEY(2, 6, KEY_X),
314 KEY(2, 7, KEY_C),
3fea6026
DT
315 KEY(2, 8, KEY_F9),
316
acf442dc
AK
317 KEY(3, 0, KEY_R),
318 KEY(3, 1, KEY_V),
319 KEY(3, 2, KEY_B),
ffe7f95b 320 KEY(3, 3, KEY_N),
acf442dc
AK
321 KEY(3, 4, KEY_M),
322 KEY(3, 5, KEY_SPACE),
323 KEY(3, 6, KEY_SPACE),
324 KEY(3, 7, KEY_LEFT),
3fea6026 325
acf442dc
AK
326 KEY(4, 0, KEY_T),
327 KEY(4, 1, KEY_DOWN),
328 KEY(4, 2, KEY_RIGHT),
ffe7f95b 329 KEY(4, 4, KEY_LEFTCTRL),
acf442dc
AK
330 KEY(4, 5, KEY_RIGHTALT),
331 KEY(4, 6, KEY_LEFTSHIFT),
2e65a207 332 KEY(4, 8, KEY_F10),
3fea6026 333
acf442dc 334 KEY(5, 0, KEY_Y),
2e65a207 335 KEY(5, 8, KEY_F11),
3fea6026 336
acf442dc 337 KEY(6, 0, KEY_U),
3fea6026 338
acf442dc
AK
339 KEY(7, 0, KEY_I),
340 KEY(7, 1, KEY_F7),
341 KEY(7, 2, KEY_F8),
ffe7f95b
LL
342};
343
4f543332
TL
344static struct matrix_keymap_data board_map_data = {
345 .keymap = board_keymap,
346 .keymap_size = ARRAY_SIZE(board_keymap),
347};
348
ffe7f95b 349static struct twl4030_keypad_data rx51_kp_data = {
4f543332 350 .keymap_data = &board_map_data,
ffe7f95b
LL
351 .rows = 8,
352 .cols = 8,
ffe7f95b
LL
353 .rep = 1,
354};
355
ce6f0016
AH
356/* Enable input logic and pull all lines up when eMMC is on. */
357static struct omap_board_mux rx51_mmc2_on_mux[] = {
358 OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
359 OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
360 OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
361 OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
362 OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
363 OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
364 OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
365 OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
366 OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
367 { .reg_offset = OMAP_MUX_TERMINATOR },
368};
369
370/* Disable input logic and pull all lines down when eMMC is off. */
371static struct omap_board_mux rx51_mmc2_off_mux[] = {
372 OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0),
373 OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0),
374 OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0),
375 OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0),
376 OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0),
377 OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0),
378 OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0),
379 OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0),
380 OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0),
381 { .reg_offset = OMAP_MUX_TERMINATOR },
382};
383
112485e9
BC
384static struct omap_mux_partition *partition;
385
ce6f0016
AH
386/*
387 * Current flows to eMMC when eMMC is off and the data lines are pulled up,
388 * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
389 */
390static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
391{
392 if (power_on)
112485e9 393 omap_mux_write_array(partition, rx51_mmc2_on_mux);
ce6f0016 394 else
112485e9 395 omap_mux_write_array(partition, rx51_mmc2_off_mux);
ce6f0016
AH
396}
397
68ff0423 398static struct omap2_hsmmc_info mmc[] __initdata = {
ffe7f95b
LL
399 {
400 .name = "external",
401 .mmc = 1,
3a63833e 402 .caps = MMC_CAP_4_BIT_DATA,
ffe7f95b
LL
403 .cover_only = true,
404 .gpio_cd = 160,
405 .gpio_wp = -EINVAL,
5e763d29 406 .power_saving = true,
ffe7f95b
LL
407 },
408 {
409 .name = "internal",
410 .mmc = 2,
3a63833e
SG
411 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
412 /* See also rx51_mmc2_remux */
ffe7f95b
LL
413 .gpio_cd = -EINVAL,
414 .gpio_wp = -EINVAL,
5e763d29
AH
415 .nonremovable = true,
416 .power_saving = true,
ce6f0016 417 .remux = rx51_mmc2_remux,
ffe7f95b
LL
418 },
419 {} /* Terminator */
420};
421
786b01a8
OD
422static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
423 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
424};
ffe7f95b 425
664a41b8
LT
426static struct regulator_consumer_supply rx51_vaux2_supply[] = {
427 REGULATOR_SUPPLY("vdds_csib", "omap3isp"),
428};
75ccf268 429
786b01a8
OD
430static struct regulator_consumer_supply rx51_vaux3_supply[] = {
431 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
432};
ffe7f95b 433
786b01a8
OD
434static struct regulator_consumer_supply rx51_vsim_supply[] = {
435 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
436};
ffe7f95b 437
4cfcaef1
JN
438static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
439 /* tlv320aic3x analog supplies */
5c7d9bbe
JN
440 REGULATOR_SUPPLY("AVDD", "2-0018"),
441 REGULATOR_SUPPLY("DRVDD", "2-0018"),
caeeb4aa
JN
442 REGULATOR_SUPPLY("AVDD", "2-0019"),
443 REGULATOR_SUPPLY("DRVDD", "2-0019"),
64d06691
JN
444 /* tpa6130a2 */
445 REGULATOR_SUPPLY("Vdd", "2-0060"),
4cfcaef1 446 /* Keep vmmc as last item. It is not iterated for newer boards */
0005ae73 447 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
4cfcaef1
JN
448};
449
450static struct regulator_consumer_supply rx51_vio_supplies[] = {
451 /* tlv320aic3x digital supplies */
5c7d9bbe
JN
452 REGULATOR_SUPPLY("IOVDD", "2-0018"),
453 REGULATOR_SUPPLY("DVDD", "2-0018"),
caeeb4aa
JN
454 REGULATOR_SUPPLY("IOVDD", "2-0019"),
455 REGULATOR_SUPPLY("DVDD", "2-0019"),
589541c0
JN
456 /* Si4713 IO supply */
457 REGULATOR_SUPPLY("vio", "2-0063"),
4cfcaef1
JN
458};
459
0581b52e 460static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
b5b9945b 461 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
589541c0
JN
462 /* Si4713 supply */
463 REGULATOR_SUPPLY("vdd", "2-0063"),
0581b52e
RQ
464};
465
ffe7f95b
LL
466static struct regulator_init_data rx51_vaux1 = {
467 .constraints = {
468 .name = "V28",
469 .min_uV = 2800000,
470 .max_uV = 2800000,
000d534e 471 .always_on = true, /* due battery cover sensor */
ffe7f95b
LL
472 .valid_modes_mask = REGULATOR_MODE_NORMAL
473 | REGULATOR_MODE_STANDBY,
474 .valid_ops_mask = REGULATOR_CHANGE_MODE
475 | REGULATOR_CHANGE_STATUS,
476 },
0581b52e
RQ
477 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers),
478 .consumer_supplies = rx51_vaux1_consumers,
ffe7f95b
LL
479};
480
481static struct regulator_init_data rx51_vaux2 = {
482 .constraints = {
483 .name = "VCSI",
484 .min_uV = 1800000,
485 .max_uV = 1800000,
486 .valid_modes_mask = REGULATOR_MODE_NORMAL
487 | REGULATOR_MODE_STANDBY,
488 .valid_ops_mask = REGULATOR_CHANGE_MODE
489 | REGULATOR_CHANGE_STATUS,
490 },
664a41b8
LT
491 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux2_supply),
492 .consumer_supplies = rx51_vaux2_supply,
ffe7f95b
LL
493};
494
495/* VAUX3 - adds more power to VIO_18 rail */
f52eeee8 496static struct regulator_init_data rx51_vaux3_cam = {
ffe7f95b
LL
497 .constraints = {
498 .name = "VCAM_DIG_18",
499 .min_uV = 1800000,
500 .max_uV = 1800000,
501 .apply_uV = true,
502 .valid_modes_mask = REGULATOR_MODE_NORMAL
503 | REGULATOR_MODE_STANDBY,
504 .valid_ops_mask = REGULATOR_CHANGE_MODE
505 | REGULATOR_CHANGE_STATUS,
506 },
507};
508
f52eeee8
AH
509static struct regulator_init_data rx51_vaux3_mmc = {
510 .constraints = {
511 .name = "VMMC2_30",
512 .min_uV = 2800000,
513 .max_uV = 3000000,
514 .apply_uV = true,
515 .valid_modes_mask = REGULATOR_MODE_NORMAL
516 | REGULATOR_MODE_STANDBY,
517 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
518 | REGULATOR_CHANGE_MODE
519 | REGULATOR_CHANGE_STATUS,
520 },
786b01a8
OD
521 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
522 .consumer_supplies = rx51_vaux3_supply,
f52eeee8
AH
523};
524
ffe7f95b
LL
525static struct regulator_init_data rx51_vaux4 = {
526 .constraints = {
527 .name = "VCAM_ANA_28",
528 .min_uV = 2800000,
529 .max_uV = 2800000,
530 .apply_uV = true,
531 .valid_modes_mask = REGULATOR_MODE_NORMAL
532 | REGULATOR_MODE_STANDBY,
533 .valid_ops_mask = REGULATOR_CHANGE_MODE
534 | REGULATOR_CHANGE_STATUS,
535 },
536};
537
538static struct regulator_init_data rx51_vmmc1 = {
539 .constraints = {
540 .min_uV = 1850000,
541 .max_uV = 3150000,
542 .valid_modes_mask = REGULATOR_MODE_NORMAL
543 | REGULATOR_MODE_STANDBY,
544 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
545 | REGULATOR_CHANGE_MODE
546 | REGULATOR_CHANGE_STATUS,
547 },
786b01a8
OD
548 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
549 .consumer_supplies = rx51_vmmc1_supply,
ffe7f95b
LL
550};
551
552static struct regulator_init_data rx51_vmmc2 = {
553 .constraints = {
f2add1de
JN
554 .name = "V28_A",
555 .min_uV = 2800000,
556 .max_uV = 3000000,
2827411e 557 .always_on = true, /* due VIO leak to AIC34 VDDs */
ffe7f95b
LL
558 .apply_uV = true,
559 .valid_modes_mask = REGULATOR_MODE_NORMAL
560 | REGULATOR_MODE_STANDBY,
561 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
562 | REGULATOR_CHANGE_MODE
563 | REGULATOR_CHANGE_STATUS,
564 },
4cfcaef1
JN
565 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies),
566 .consumer_supplies = rx51_vmmc2_supplies,
ffe7f95b
LL
567};
568
094fc559
KJ
569static struct regulator_init_data rx51_vpll1 = {
570 .constraints = {
571 .name = "VPLL",
572 .min_uV = 1800000,
573 .max_uV = 1800000,
574 .apply_uV = true,
575 .always_on = true,
576 .valid_modes_mask = REGULATOR_MODE_NORMAL
577 | REGULATOR_MODE_STANDBY,
578 .valid_ops_mask = REGULATOR_CHANGE_MODE,
579 },
580};
581
582static struct regulator_init_data rx51_vpll2 = {
583 .constraints = {
584 .name = "VSDI_CSI",
585 .min_uV = 1800000,
586 .max_uV = 1800000,
587 .apply_uV = true,
588 .always_on = true,
589 .valid_modes_mask = REGULATOR_MODE_NORMAL
590 | REGULATOR_MODE_STANDBY,
591 .valid_ops_mask = REGULATOR_CHANGE_MODE,
592 },
593};
594
ffe7f95b
LL
595static struct regulator_init_data rx51_vsim = {
596 .constraints = {
597 .name = "VMMC2_IO_18",
598 .min_uV = 1800000,
599 .max_uV = 1800000,
600 .apply_uV = true,
601 .valid_modes_mask = REGULATOR_MODE_NORMAL
602 | REGULATOR_MODE_STANDBY,
603 .valid_ops_mask = REGULATOR_CHANGE_MODE
604 | REGULATOR_CHANGE_STATUS,
605 },
786b01a8
OD
606 .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
607 .consumer_supplies = rx51_vsim_supply,
ffe7f95b
LL
608};
609
4cfcaef1
JN
610static struct regulator_init_data rx51_vio = {
611 .constraints = {
612 .min_uV = 1800000,
613 .max_uV = 1800000,
614 .valid_modes_mask = REGULATOR_MODE_NORMAL
615 | REGULATOR_MODE_STANDBY,
616 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
617 | REGULATOR_CHANGE_MODE
618 | REGULATOR_CHANGE_STATUS,
619 },
620 .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies),
621 .consumer_supplies = rx51_vio_supplies,
622};
623
094fc559
KJ
624static struct regulator_init_data rx51_vintana1 = {
625 .constraints = {
626 .name = "VINTANA1",
627 .min_uV = 1500000,
628 .max_uV = 1500000,
629 .always_on = true,
630 .valid_modes_mask = REGULATOR_MODE_NORMAL
631 | REGULATOR_MODE_STANDBY,
632 .valid_ops_mask = REGULATOR_CHANGE_MODE,
633 },
634};
635
636static struct regulator_init_data rx51_vintana2 = {
637 .constraints = {
638 .name = "VINTANA2",
639 .min_uV = 2750000,
640 .max_uV = 2750000,
641 .apply_uV = true,
642 .always_on = true,
643 .valid_modes_mask = REGULATOR_MODE_NORMAL
644 | REGULATOR_MODE_STANDBY,
645 .valid_ops_mask = REGULATOR_CHANGE_MODE,
646 },
647};
648
649static struct regulator_init_data rx51_vintdig = {
650 .constraints = {
651 .name = "VINTDIG",
652 .min_uV = 1500000,
653 .max_uV = 1500000,
654 .always_on = true,
655 .valid_modes_mask = REGULATOR_MODE_NORMAL
656 | REGULATOR_MODE_STANDBY,
657 .valid_ops_mask = REGULATOR_CHANGE_MODE,
658 },
659};
660
589541c0
JN
661static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
662 .gpio_reset = RX51_FMTX_RESET_GPIO,
663};
664
665static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
666 I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
667 .platform_data = &rx51_si4713_i2c_data,
668};
669
670static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
671 .i2c_bus = 2,
672 .subdev_board_info = &rx51_si4713_board_info,
673};
674
07ad6ab3 675static struct platform_device rx51_si4713_dev = {
589541c0
JN
676 .name = "radio-si4713",
677 .id = -1,
678 .dev = {
679 .platform_data = &rx51_si4713_data,
680 },
681};
682
683static __init void rx51_init_si4713(void)
684{
685 int err;
686
687 err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
688 if (err) {
689 printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
690 return;
691 }
692 rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
693 platform_device_register(&rx51_si4713_dev);
694}
695
ffe7f95b
LL
696static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
697{
698 /* FIXME this gpio setup is just a placeholder for now */
bc593f5d 699 gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
c0ad4fac 700 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "speaker_en");
ffe7f95b 701
ffe7f95b
LL
702 return 0;
703}
704
705static struct twl4030_gpio_platform_data rx51_gpio_data = {
706 .gpio_base = OMAP_MAX_GPIO_LINES,
707 .irq_base = TWL4030_GPIO_IRQ_BASE,
708 .irq_end = TWL4030_GPIO_IRQ_END,
709 .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3)
710 | BIT(4) | BIT(5)
711 | BIT(8) | BIT(9) | BIT(10) | BIT(11)
712 | BIT(12) | BIT(13) | BIT(14) | BIT(15)
713 | BIT(16) | BIT(17) ,
714 .setup = rx51_twlgpio_setup,
715};
716
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AK
717static struct twl4030_ins sleep_on_seq[] __initdata = {
718/*
3c684e84 719 * Turn off everything
9312fffb 720 */
3c684e84 721 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
9312fffb
AK
722};
723
724static struct twl4030_script sleep_on_script __initdata = {
725 .script = sleep_on_seq,
726 .size = ARRAY_SIZE(sleep_on_seq),
727 .flags = TWL4030_SLEEP_SCRIPT,
728};
729
730static struct twl4030_ins wakeup_seq[] __initdata = {
731/*
3c684e84 732 * Reenable everything
9312fffb 733 */
3c684e84 734 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
9312fffb
AK
735};
736
737static struct twl4030_script wakeup_script __initdata = {
738 .script = wakeup_seq,
739 .size = ARRAY_SIZE(wakeup_seq),
740 .flags = TWL4030_WAKEUP12_SCRIPT,
741};
742
743static struct twl4030_ins wakeup_p3_seq[] __initdata = {
744/*
3c684e84 745 * Reenable everything
9312fffb 746 */
3c684e84 747 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
9312fffb
AK
748};
749
750static struct twl4030_script wakeup_p3_script __initdata = {
751 .script = wakeup_p3_seq,
752 .size = ARRAY_SIZE(wakeup_p3_seq),
753 .flags = TWL4030_WAKEUP3_SCRIPT,
754};
755
756static struct twl4030_ins wrst_seq[] __initdata = {
757/*
758 * Reset twl4030.
759 * Reset VDD1 regulator.
760 * Reset VDD2 regulator.
761 * Reset VPLL1 regulator.
762 * Enable sysclk output.
763 * Reenable twl4030.
764 */
765 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
766 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
767 0x13},
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AK
768 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
769 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
770 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
771 {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
3c684e84 772 {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
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AK
773 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
774};
775
776static struct twl4030_script wrst_script __initdata = {
777 .script = wrst_seq,
778 .size = ARRAY_SIZE(wrst_seq),
779 .flags = TWL4030_WRST_SCRIPT,
780};
781
782static struct twl4030_script *twl4030_scripts[] __initdata = {
783 /* wakeup12 script should be loaded before sleep script, otherwise a
784 board might hit retention before loading of wakeup script is
785 completed. This can cause boot failures depending on timing issues.
786 */
787 &wakeup_script,
788 &sleep_on_script,
789 &wakeup_p3_script,
790 &wrst_script,
791};
792
793static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
3c684e84
AK
794 { .resource = RES_VDD1, .devgroup = -1,
795 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
796 .remap_sleep = RES_STATE_OFF
797 },
798 { .resource = RES_VDD2, .devgroup = -1,
799 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
800 .remap_sleep = RES_STATE_OFF
801 },
802 { .resource = RES_VPLL1, .devgroup = -1,
803 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
804 .remap_sleep = RES_STATE_OFF
805 },
806 { .resource = RES_VPLL2, .devgroup = -1,
807 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
808 },
809 { .resource = RES_VAUX1, .devgroup = -1,
810 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
811 },
812 { .resource = RES_VAUX2, .devgroup = -1,
813 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
814 },
815 { .resource = RES_VAUX3, .devgroup = -1,
816 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
817 },
818 { .resource = RES_VAUX4, .devgroup = -1,
819 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
820 },
821 { .resource = RES_VMMC1, .devgroup = -1,
822 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
823 },
824 { .resource = RES_VMMC2, .devgroup = -1,
825 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
826 },
827 { .resource = RES_VDAC, .devgroup = -1,
828 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
829 },
830 { .resource = RES_VSIM, .devgroup = -1,
831 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
832 },
833 { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
834 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
835 },
836 { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
837 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
838 },
839 { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
840 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
841 },
842 { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
843 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
844 },
845 { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
846 .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
847 },
848 { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
849 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
850 },
851 { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
852 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
853 },
854 { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
855 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
856 },
857 { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
858 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
859 },
860 { .resource = RES_32KCLKOUT, .devgroup = -1,
861 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
862 },
863 { .resource = RES_RESET, .devgroup = -1,
864 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
865 },
d7ac829f 866 { .resource = RES_MAIN_REF, .devgroup = -1,
3c684e84
AK
867 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
868 },
9312fffb
AK
869 { 0, 0},
870};
871
872static struct twl4030_power_data rx51_t2scripts_data __initdata = {
873 .scripts = twl4030_scripts,
874 .num = ARRAY_SIZE(twl4030_scripts),
875 .resource_config = twl4030_rconfig,
876};
877
4ae6df5e 878struct twl4030_vibra_data rx51_vibra_data __initdata = {
b7a834cc
IK
879 .coexist = 0,
880};
881
4ae6df5e 882struct twl4030_audio_data rx51_audio_data __initdata = {
b7a834cc
IK
883 .audio_mclk = 26000000,
884 .vibra = &rx51_vibra_data,
885};
9312fffb 886
9312fffb 887static struct twl4030_platform_data rx51_twldata __initdata = {
ffe7f95b
LL
888 /* platform_data for children goes here */
889 .gpio = &rx51_gpio_data,
890 .keypad = &rx51_kp_data,
9312fffb 891 .power = &rx51_t2scripts_data,
4ae6df5e 892 .audio = &rx51_audio_data,
ffe7f95b
LL
893
894 .vaux1 = &rx51_vaux1,
895 .vaux2 = &rx51_vaux2,
ffe7f95b
LL
896 .vaux4 = &rx51_vaux4,
897 .vmmc1 = &rx51_vmmc1,
094fc559
KJ
898 .vpll1 = &rx51_vpll1,
899 .vpll2 = &rx51_vpll2,
ffe7f95b 900 .vsim = &rx51_vsim,
094fc559
KJ
901 .vintana1 = &rx51_vintana1,
902 .vintana2 = &rx51_vintana2,
903 .vintdig = &rx51_vintdig,
4cfcaef1 904 .vio = &rx51_vio,
ffe7f95b
LL
905};
906
f0c61d3d 907static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
64d06691
JN
908 .power_gpio = 98,
909};
910
f0fba2ad
LG
911/* Audio setup data */
912static struct aic3x_setup_data rx51_aic34_setup = {
913 .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
914 .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
915};
916
e4862f2f 917static struct aic3x_pdata rx51_aic3x_data = {
f0fba2ad
LG
918 .setup = &rx51_aic34_setup,
919 .gpio_reset = 60,
920};
921
caeeb4aa
JN
922static struct aic3x_pdata rx51_aic3x_data2 = {
923 .gpio_reset = 60,
924};
925
dabe929b
JN
926static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
927 {
928 I2C_BOARD_INFO("tlv320aic3x", 0x18),
87581fd4 929 .platform_data = &rx51_aic3x_data,
dabe929b 930 },
caeeb4aa
JN
931 {
932 I2C_BOARD_INFO("tlv320aic3x", 0x19),
933 .platform_data = &rx51_aic3x_data2,
934 },
70b5d737
MN
935#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
936 {
937 I2C_BOARD_INFO("tsl2563", 0x29),
938 .platform_data = &rx51_tsl2563_platform_data,
939 },
eeada9e8
AP
940#endif
941#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
942 {
943 I2C_BOARD_INFO("lp5523", 0x32),
944 .platform_data = &rx51_lp5523_platform_data,
945 },
70b5d737 946#endif
d77711aa
PR
947 {
948 I2C_BOARD_INFO("bq27200", 0x55),
949 },
64d06691
JN
950 {
951 I2C_BOARD_INFO("tpa6130a2", 0x60),
952 .platform_data = &rx51_tpa6130a2_data,
953 }
dabe929b
JN
954};
955
ffe7f95b
LL
956static int __init rx51_i2c_init(void)
957{
f52eeee8 958 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
4cfcaef1 959 system_rev >= SYSTEM_REV_B_USES_VAUX3) {
f52eeee8 960 rx51_twldata.vaux3 = &rx51_vaux3_mmc;
4cfcaef1
JN
961 /* Only older boards use VMMC2 for internal MMC */
962 rx51_vmmc2.num_consumer_supplies--;
963 } else {
f52eeee8 964 rx51_twldata.vaux3 = &rx51_vaux3_cam;
f52eeee8 965 }
4cfcaef1 966 rx51_twldata.vmmc2 = &rx51_vmmc2;
827ed9ae 967 omap3_pmic_get_config(&rx51_twldata,
b252b0ef
PU
968 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
969 TWL_COMMON_REGULATOR_VDAC);
970
971 rx51_twldata.vdac->constraints.apply_uV = true;
972 rx51_twldata.vdac->constraints.name = "VDAC";
973
fbd8071c 974 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
dabe929b
JN
975 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
976 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
ffe7f95b
LL
977 omap_register_i2c_bus(3, 400, NULL, 0);
978 return 0;
979}
980
aa62e90f
JY
981#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
982 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
983
984static struct mtd_partition onenand_partitions[] = {
985 {
986 .name = "bootloader",
987 .offset = 0,
988 .size = 0x20000,
989 .mask_flags = MTD_WRITEABLE, /* Force read-only */
990 },
991 {
992 .name = "config",
993 .offset = MTDPART_OFS_APPEND,
994 .size = 0x60000,
995 },
996 {
997 .name = "log",
998 .offset = MTDPART_OFS_APPEND,
999 .size = 0x40000,
1000 },
1001 {
1002 .name = "kernel",
1003 .offset = MTDPART_OFS_APPEND,
1004 .size = 0x200000,
1005 },
1006 {
1007 .name = "initfs",
1008 .offset = MTDPART_OFS_APPEND,
1009 .size = 0x200000,
1010 },
1011 {
1012 .name = "rootfs",
1013 .offset = MTDPART_OFS_APPEND,
1014 .size = MTDPART_SIZ_FULL,
1015 },
1016};
1017
5403187f
AK
1018static struct omap_onenand_platform_data board_onenand_data[] = {
1019 {
1020 .cs = 0,
1021 .gpio_irq = 65,
1022 .parts = onenand_partitions,
1023 .nr_parts = ARRAY_SIZE(onenand_partitions),
1024 .flags = ONENAND_SYNC_READWRITE,
1025 }
aa62e90f 1026};
aa62e90f 1027#endif
ffe7f95b 1028
1a48e157
TL
1029#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1030
1031static struct omap_smc91x_platform_data board_smc91x_data = {
1032 .cs = 1,
1033 .gpio_irq = 54,
1034 .gpio_pwrdwn = 86,
1035 .gpio_reset = 164,
1036 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
1037};
1038
1039static void __init board_smc91x_init(void)
1040{
4896e394
TL
1041 omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
1042 omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
1043 omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
1a48e157
TL
1044
1045 gpmc_smc91x_init(&board_smc91x_data);
1046}
1047
1048#else
1049
1050static inline void board_smc91x_init(void)
1051{
1052}
1053
1054#endif
1055
a24e61a9
KV
1056static void rx51_wl1251_set_power(bool enable)
1057{
1058 gpio_set_value(RX51_WL1251_POWER_GPIO, enable);
1059}
1060
bc593f5d
IG
1061static struct gpio rx51_wl1251_gpios[] __initdata = {
1062 { RX51_WL1251_POWER_GPIO, GPIOF_OUT_INIT_LOW, "wl1251 power" },
1063 { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" },
1064};
1065
a24e61a9
KV
1066static void __init rx51_init_wl1251(void)
1067{
1068 int irq, ret;
1069
bc593f5d
IG
1070 ret = gpio_request_array(rx51_wl1251_gpios,
1071 ARRAY_SIZE(rx51_wl1251_gpios));
a24e61a9
KV
1072 if (ret < 0)
1073 goto error;
1074
a24e61a9
KV
1075 irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
1076 if (irq < 0)
1077 goto err_irq;
1078
1079 wl1251_pdata.set_power = rx51_wl1251_set_power;
1080 rx51_peripherals_spi_board_info[RX51_SPI_WL1251].irq = irq;
1081
1082 return;
1083
1084err_irq:
1085 gpio_free(RX51_WL1251_IRQ_GPIO);
a24e61a9 1086 gpio_free(RX51_WL1251_POWER_GPIO);
a24e61a9
KV
1087error:
1088 printk(KERN_ERR "wl1251 board initialisation failed\n");
1089 wl1251_pdata.set_power = NULL;
1090
1091 /*
1092 * Now rx51_peripherals_spi_board_info[1].irq is zero and
1093 * set_power is null, and wl1251_probe() will fail.
1094 */
1095}
1096
3dad5356
AK
1097static struct tsc2005_platform_data tsc2005_pdata = {
1098 .ts_pressure_max = 2048,
1099 .ts_pressure_fudge = 2,
1100 .ts_x_max = 4096,
1101 .ts_x_fudge = 4,
1102 .ts_y_max = 4096,
1103 .ts_y_fudge = 7,
1104 .ts_x_plate_ohm = 280,
1105 .esd_timeout_ms = 8000,
1106};
1107
1108static void rx51_tsc2005_set_reset(bool enable)
1109{
1110 gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
1111}
1112
1113static void __init rx51_init_tsc2005(void)
1114{
1115 int r;
1116
1117 r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
1118 if (r < 0) {
1119 printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
1120 rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
1121 }
1122
1123 r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
1124 "tsc2005 reset");
1125 if (r >= 0) {
1126 tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
1127 } else {
1128 printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
1129 tsc2005_pdata.esd_timeout_ms = 0;
1130 }
1131}
1132
ffe7f95b
LL
1133void __init rx51_peripherals_init(void)
1134{
ffe7f95b 1135 rx51_i2c_init();
094fc559 1136 regulator_has_full_constraints();
5403187f 1137 gpmc_onenand_init(board_onenand_data);
1a48e157 1138 board_smc91x_init();
f014ee32 1139 rx51_add_gpio_keys();
a24e61a9 1140 rx51_init_wl1251();
3dad5356 1141 rx51_init_tsc2005();
589541c0 1142 rx51_init_si4713();
a24e61a9
KV
1143 spi_register_board_info(rx51_peripherals_spi_board_info,
1144 ARRAY_SIZE(rx51_peripherals_spi_board_info));
112485e9
BC
1145
1146 partition = omap_mux_get("core");
1147 if (partition)
1148 omap2_hsmmc_init(mmc);
1149
10299e2e 1150 rx51_charger_init();
ffe7f95b
LL
1151}
1152
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