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cb26867e RN |
1 | /* |
2 | * OMAP4 Clock data | |
3 | * | |
4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
6 | * | |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * Mike Turquette (mturquette@ti.com) | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * XXX Some of the ES1 clocks have been removed/changed; once support | |
17 | * is added for discriminating clocks by ES level, these should be added back | |
18 | * in. | |
17b7e7d3 | 19 | * |
ee877acd PW |
20 | * XXX All of the remaining MODULEMODE clock nodes should be removed |
21 | * once the drivers are updated to use pm_runtime or to use the appropriate | |
22 | * upstream clock node for rate/parent selection. | |
cb26867e RN |
23 | */ |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/clk-private.h> | |
28 | #include <linux/clkdev.h> | |
29 | #include <linux/io.h> | |
30 | ||
31 | #include "soc.h" | |
32 | #include "iomap.h" | |
33 | #include "clock.h" | |
34 | #include "clock44xx.h" | |
35 | #include "cm1_44xx.h" | |
36 | #include "cm2_44xx.h" | |
37 | #include "cm-regbits-44xx.h" | |
38 | #include "prm44xx.h" | |
39 | #include "prm-regbits-44xx.h" | |
40 | #include "control.h" | |
41 | #include "scrm44xx.h" | |
42 | ||
43 | /* OMAP4 modulemode control */ | |
44 | #define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 | |
45 | #define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 | |
46 | ||
8c197ccf JH |
47 | /* |
48 | * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section | |
49 | * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK | |
50 | * must be set to 196.608 MHz" and hence, the DPLL locked frequency is | |
51 | * half of this value. | |
52 | */ | |
53 | #define OMAP4_DPLL_ABE_DEFFREQ 98304000 | |
54 | ||
cb26867e RN |
55 | /* Root clocks */ |
56 | ||
57 | DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); | |
58 | ||
59 | DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); | |
60 | ||
61 | DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, | |
62 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, | |
63 | 0x0, NULL); | |
64 | ||
65 | DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); | |
66 | ||
67 | DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); | |
68 | ||
69 | DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); | |
70 | ||
71 | DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, | |
72 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | |
73 | 0x0, NULL); | |
74 | ||
75 | DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |
76 | ||
77 | DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); | |
78 | ||
79 | DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); | |
80 | ||
81 | DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); | |
82 | ||
83 | DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); | |
84 | ||
85 | DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); | |
86 | ||
87 | DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); | |
88 | ||
89 | DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); | |
90 | ||
91 | static const char *sys_clkin_ck_parents[] = { | |
92 | "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", | |
93 | "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", | |
94 | "virt_38400000_ck", | |
95 | }; | |
96 | ||
97 | DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, | |
98 | OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, | |
99 | OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); | |
100 | ||
101 | DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); | |
102 | ||
103 | DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); | |
104 | ||
105 | DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); | |
106 | ||
107 | DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); | |
108 | ||
109 | DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); | |
110 | ||
111 | /* Module clocks and DPLL outputs */ | |
112 | ||
113 | static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { | |
114 | "sys_clkin_ck", "sys_32k_ck", | |
115 | }; | |
116 | ||
117 | DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, | |
118 | NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, | |
119 | OMAP4430_CLKSEL_WIDTH, 0x0, NULL); | |
120 | ||
121 | DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, | |
122 | 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
123 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
124 | ||
125 | /* DPLL_ABE */ | |
126 | static struct dpll_data dpll_abe_dd = { | |
127 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | |
128 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, | |
129 | .clk_ref = &abe_dpll_refclk_mux_ck, | |
130 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | |
131 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
132 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | |
133 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | |
134 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
135 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
136 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
137 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
138 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
3ff51ed8 JH |
139 | .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK, |
140 | .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK, | |
cb26867e RN |
141 | .max_multiplier = 2047, |
142 | .max_divider = 128, | |
143 | .min_divider = 1, | |
144 | }; | |
145 | ||
146 | ||
147 | static const char *dpll_abe_ck_parents[] = { | |
148 | "abe_dpll_refclk_mux_ck", | |
149 | }; | |
150 | ||
151 | static struct clk dpll_abe_ck; | |
152 | ||
153 | static const struct clk_ops dpll_abe_ck_ops = { | |
154 | .enable = &omap3_noncore_dpll_enable, | |
155 | .disable = &omap3_noncore_dpll_disable, | |
156 | .recalc_rate = &omap4_dpll_regm4xen_recalc, | |
157 | .round_rate = &omap4_dpll_regm4xen_round_rate, | |
158 | .set_rate = &omap3_noncore_dpll_set_rate, | |
159 | .get_parent = &omap2_init_dpll_parent, | |
160 | }; | |
161 | ||
162 | static struct clk_hw_omap dpll_abe_ck_hw = { | |
163 | .hw = { | |
164 | .clk = &dpll_abe_ck, | |
165 | }, | |
166 | .dpll_data = &dpll_abe_dd, | |
167 | .ops = &clkhwops_omap3_dpll, | |
168 | }; | |
169 | ||
170 | DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); | |
171 | ||
172 | static const char *dpll_abe_x2_ck_parents[] = { | |
173 | "dpll_abe_ck", | |
174 | }; | |
175 | ||
176 | static struct clk dpll_abe_x2_ck; | |
177 | ||
178 | static const struct clk_ops dpll_abe_x2_ck_ops = { | |
179 | .recalc_rate = &omap3_clkoutx2_recalc, | |
180 | }; | |
181 | ||
182 | static struct clk_hw_omap dpll_abe_x2_ck_hw = { | |
183 | .hw = { | |
184 | .clk = &dpll_abe_x2_ck, | |
185 | }, | |
186 | .flags = CLOCK_CLKOUTX2, | |
187 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | |
188 | .ops = &clkhwops_omap4_dpllmx, | |
189 | }; | |
190 | ||
191 | DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); | |
192 | ||
193 | static const struct clk_ops omap_hsdivider_ops = { | |
194 | .set_rate = &omap2_clksel_set_rate, | |
195 | .recalc_rate = &omap2_clksel_recalc, | |
196 | .round_rate = &omap2_clksel_round_rate, | |
197 | }; | |
198 | ||
199 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, | |
200 | 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, | |
201 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
202 | ||
203 | DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, | |
204 | 0x0, 1, 8); | |
205 | ||
206 | DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, | |
207 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, | |
208 | OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
209 | ||
210 | DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, | |
211 | OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
212 | OMAP4430_CLKSEL_AESS_FCLK_SHIFT, | |
213 | OMAP4430_CLKSEL_AESS_FCLK_WIDTH, | |
214 | 0x0, NULL); | |
215 | ||
216 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, | |
217 | 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, | |
218 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); | |
219 | ||
220 | static const char *core_hsd_byp_clk_mux_ck_parents[] = { | |
221 | "sys_clkin_ck", "dpll_abe_m3x2_ck", | |
222 | }; | |
223 | ||
224 | DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, | |
225 | 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, | |
226 | OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, | |
227 | 0x0, NULL); | |
228 | ||
229 | /* DPLL_CORE */ | |
230 | static struct dpll_data dpll_core_dd = { | |
231 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
232 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | |
233 | .clk_ref = &sys_clkin_ck, | |
234 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, | |
235 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
236 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | |
237 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | |
238 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
239 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
240 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
241 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
242 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
243 | .max_multiplier = 2047, | |
244 | .max_divider = 128, | |
245 | .min_divider = 1, | |
246 | }; | |
247 | ||
248 | ||
249 | static const char *dpll_core_ck_parents[] = { | |
b8675e2c | 250 | "sys_clkin_ck", "core_hsd_byp_clk_mux_ck" |
cb26867e RN |
251 | }; |
252 | ||
253 | static struct clk dpll_core_ck; | |
254 | ||
255 | static const struct clk_ops dpll_core_ck_ops = { | |
256 | .recalc_rate = &omap3_dpll_recalc, | |
257 | .get_parent = &omap2_init_dpll_parent, | |
258 | }; | |
259 | ||
260 | static struct clk_hw_omap dpll_core_ck_hw = { | |
261 | .hw = { | |
262 | .clk = &dpll_core_ck, | |
263 | }, | |
264 | .dpll_data = &dpll_core_dd, | |
265 | .ops = &clkhwops_omap3_dpll, | |
266 | }; | |
267 | ||
268 | DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); | |
269 | ||
270 | static const char *dpll_core_x2_ck_parents[] = { | |
271 | "dpll_core_ck", | |
272 | }; | |
273 | ||
274 | static struct clk dpll_core_x2_ck; | |
275 | ||
276 | static struct clk_hw_omap dpll_core_x2_ck_hw = { | |
277 | .hw = { | |
278 | .clk = &dpll_core_x2_ck, | |
279 | }, | |
280 | }; | |
281 | ||
282 | DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); | |
283 | ||
284 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", | |
285 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, | |
286 | OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); | |
287 | ||
288 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, | |
289 | OMAP4430_CM_DIV_M2_DPLL_CORE, | |
290 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
291 | ||
292 | DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, | |
293 | 2); | |
294 | ||
295 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", | |
296 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, | |
297 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
298 | ||
299 | DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, | |
300 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, | |
301 | OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); | |
302 | ||
628a37d4 PW |
303 | DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, |
304 | 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT, | |
305 | OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
cb26867e RN |
306 | |
307 | DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, | |
308 | 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, | |
309 | OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
310 | ||
311 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", | |
312 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, | |
313 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
314 | ||
315 | DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, | |
316 | 0x0, 1, 2); | |
317 | ||
318 | DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, | |
319 | OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, | |
320 | OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); | |
321 | ||
ee877acd | 322 | static const struct clk_ops dpll_hsd_ops = { |
cb26867e RN |
323 | .enable = &omap2_dflt_clk_enable, |
324 | .disable = &omap2_dflt_clk_disable, | |
325 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
326 | .recalc_rate = &omap2_clksel_recalc, | |
327 | .get_parent = &omap2_clksel_find_parent_index, | |
328 | .set_parent = &omap2_clksel_set_parent, | |
329 | .init = &omap2_init_clk_clkdm, | |
330 | }; | |
331 | ||
ee877acd PW |
332 | static const struct clk_ops func_dmic_abe_gfclk_ops = { |
333 | .recalc_rate = &omap2_clksel_recalc, | |
334 | .get_parent = &omap2_clksel_find_parent_index, | |
335 | .set_parent = &omap2_clksel_set_parent, | |
336 | }; | |
337 | ||
cb26867e RN |
338 | static const char *dpll_core_m3x2_ck_parents[] = { |
339 | "dpll_core_x2_ck", | |
340 | }; | |
341 | ||
342 | static const struct clksel dpll_core_m3x2_div[] = { | |
343 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | |
344 | { .parent = NULL }, | |
345 | }; | |
346 | ||
347 | /* XXX Missing round_rate, set_rate in ops */ | |
348 | DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, | |
349 | OMAP4430_CM_DIV_M3_DPLL_CORE, | |
350 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
351 | OMAP4430_CM_DIV_M3_DPLL_CORE, | |
352 | OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, | |
ee877acd | 353 | dpll_core_m3x2_ck_parents, dpll_hsd_ops); |
cb26867e RN |
354 | |
355 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", | |
356 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, | |
357 | OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); | |
358 | ||
359 | static const char *iva_hsd_byp_clk_mux_ck_parents[] = { | |
360 | "sys_clkin_ck", "div_iva_hs_clk", | |
361 | }; | |
362 | ||
363 | DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, | |
364 | 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, | |
365 | OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); | |
366 | ||
367 | /* DPLL_IVA */ | |
368 | static struct dpll_data dpll_iva_dd = { | |
369 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
370 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | |
371 | .clk_ref = &sys_clkin_ck, | |
372 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, | |
373 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
374 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | |
375 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | |
376 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
377 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
378 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
379 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
380 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
381 | .max_multiplier = 2047, | |
382 | .max_divider = 128, | |
383 | .min_divider = 1, | |
384 | }; | |
385 | ||
b8675e2c PW |
386 | static const char *dpll_iva_ck_parents[] = { |
387 | "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck" | |
388 | }; | |
389 | ||
cb26867e RN |
390 | static struct clk dpll_iva_ck; |
391 | ||
9b4fcc86 JH |
392 | static const struct clk_ops dpll_ck_ops = { |
393 | .enable = &omap3_noncore_dpll_enable, | |
394 | .disable = &omap3_noncore_dpll_disable, | |
395 | .recalc_rate = &omap3_dpll_recalc, | |
396 | .round_rate = &omap2_dpll_round_rate, | |
397 | .set_rate = &omap3_noncore_dpll_set_rate, | |
398 | .get_parent = &omap2_init_dpll_parent, | |
399 | }; | |
400 | ||
cb26867e RN |
401 | static struct clk_hw_omap dpll_iva_ck_hw = { |
402 | .hw = { | |
403 | .clk = &dpll_iva_ck, | |
404 | }, | |
405 | .dpll_data = &dpll_iva_dd, | |
406 | .ops = &clkhwops_omap3_dpll, | |
407 | }; | |
408 | ||
b8675e2c | 409 | DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops); |
cb26867e RN |
410 | |
411 | static const char *dpll_iva_x2_ck_parents[] = { | |
412 | "dpll_iva_ck", | |
413 | }; | |
414 | ||
415 | static struct clk dpll_iva_x2_ck; | |
416 | ||
417 | static struct clk_hw_omap dpll_iva_x2_ck_hw = { | |
418 | .hw = { | |
419 | .clk = &dpll_iva_x2_ck, | |
420 | }, | |
421 | }; | |
422 | ||
423 | DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); | |
424 | ||
425 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, | |
426 | 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, | |
427 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
428 | ||
429 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, | |
430 | 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, | |
431 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
432 | ||
433 | /* DPLL_MPU */ | |
434 | static struct dpll_data dpll_mpu_dd = { | |
435 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | |
436 | .clk_bypass = &div_mpu_hs_clk, | |
437 | .clk_ref = &sys_clkin_ck, | |
438 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, | |
439 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
440 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | |
441 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | |
442 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
443 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
444 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
445 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
446 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
447 | .max_multiplier = 2047, | |
448 | .max_divider = 128, | |
449 | .min_divider = 1, | |
450 | }; | |
451 | ||
b8675e2c PW |
452 | static const char *dpll_mpu_ck_parents[] = { |
453 | "sys_clkin_ck", "div_mpu_hs_clk" | |
454 | }; | |
455 | ||
cb26867e RN |
456 | static struct clk dpll_mpu_ck; |
457 | ||
458 | static struct clk_hw_omap dpll_mpu_ck_hw = { | |
459 | .hw = { | |
460 | .clk = &dpll_mpu_ck, | |
461 | }, | |
462 | .dpll_data = &dpll_mpu_dd, | |
463 | .ops = &clkhwops_omap3_dpll, | |
464 | }; | |
465 | ||
b8675e2c | 466 | DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops); |
cb26867e RN |
467 | |
468 | DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); | |
469 | ||
470 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, | |
471 | OMAP4430_CM_DIV_M2_DPLL_MPU, | |
472 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
473 | ||
474 | DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", | |
475 | &dpll_abe_m3x2_ck, 0x0, 1, 2); | |
476 | ||
477 | static const char *per_hsd_byp_clk_mux_ck_parents[] = { | |
478 | "sys_clkin_ck", "per_hs_clk_div_ck", | |
479 | }; | |
480 | ||
481 | DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, | |
482 | 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, | |
483 | OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); | |
484 | ||
485 | /* DPLL_PER */ | |
486 | static struct dpll_data dpll_per_dd = { | |
487 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
488 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | |
489 | .clk_ref = &sys_clkin_ck, | |
490 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, | |
491 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
492 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | |
493 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | |
494 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
495 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
496 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
497 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
498 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
499 | .max_multiplier = 2047, | |
500 | .max_divider = 128, | |
501 | .min_divider = 1, | |
502 | }; | |
503 | ||
b8675e2c PW |
504 | static const char *dpll_per_ck_parents[] = { |
505 | "sys_clkin_ck", "per_hsd_byp_clk_mux_ck" | |
506 | }; | |
cb26867e RN |
507 | |
508 | static struct clk dpll_per_ck; | |
509 | ||
510 | static struct clk_hw_omap dpll_per_ck_hw = { | |
511 | .hw = { | |
512 | .clk = &dpll_per_ck, | |
513 | }, | |
514 | .dpll_data = &dpll_per_dd, | |
515 | .ops = &clkhwops_omap3_dpll, | |
516 | }; | |
517 | ||
b8675e2c | 518 | DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops); |
cb26867e RN |
519 | |
520 | DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, | |
521 | OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, | |
522 | OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); | |
523 | ||
524 | static const char *dpll_per_x2_ck_parents[] = { | |
525 | "dpll_per_ck", | |
526 | }; | |
527 | ||
528 | static struct clk dpll_per_x2_ck; | |
529 | ||
530 | static struct clk_hw_omap dpll_per_x2_ck_hw = { | |
531 | .hw = { | |
532 | .clk = &dpll_per_x2_ck, | |
533 | }, | |
534 | .flags = CLOCK_CLKOUTX2, | |
535 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
536 | .ops = &clkhwops_omap4_dpllmx, | |
537 | }; | |
538 | ||
539 | DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); | |
540 | ||
541 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
542 | 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, | |
543 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
544 | ||
545 | static const char *dpll_per_m3x2_ck_parents[] = { | |
546 | "dpll_per_x2_ck", | |
547 | }; | |
548 | ||
549 | static const struct clksel dpll_per_m3x2_div[] = { | |
550 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | |
551 | { .parent = NULL }, | |
552 | }; | |
553 | ||
554 | /* XXX Missing round_rate, set_rate in ops */ | |
555 | DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, | |
556 | OMAP4430_CM_DIV_M3_DPLL_PER, | |
557 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
558 | OMAP4430_CM_DIV_M3_DPLL_PER, | |
559 | OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, | |
ee877acd | 560 | dpll_per_m3x2_ck_parents, dpll_hsd_ops); |
cb26867e RN |
561 | |
562 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
563 | 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, | |
564 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
565 | ||
566 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
567 | 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, | |
568 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
569 | ||
570 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
571 | 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, | |
572 | OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); | |
573 | ||
574 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
575 | 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, | |
576 | OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); | |
577 | ||
578 | DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", | |
579 | &dpll_abe_m3x2_ck, 0x0, 1, 3); | |
580 | ||
581 | /* DPLL_USB */ | |
582 | static struct dpll_data dpll_usb_dd = { | |
583 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | |
584 | .clk_bypass = &usb_hs_clk_div_ck, | |
585 | .flags = DPLL_J_TYPE, | |
586 | .clk_ref = &sys_clkin_ck, | |
587 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, | |
588 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
589 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | |
590 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | |
591 | .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, | |
592 | .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, | |
593 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
594 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
595 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
596 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, | |
597 | .max_multiplier = 4095, | |
598 | .max_divider = 256, | |
599 | .min_divider = 1, | |
600 | }; | |
601 | ||
b8675e2c PW |
602 | static const char *dpll_usb_ck_parents[] = { |
603 | "sys_clkin_ck", "usb_hs_clk_div_ck" | |
604 | }; | |
605 | ||
cb26867e RN |
606 | static struct clk dpll_usb_ck; |
607 | ||
d0758237 RN |
608 | static const struct clk_ops dpll_usb_ck_ops = { |
609 | .enable = &omap3_noncore_dpll_enable, | |
610 | .disable = &omap3_noncore_dpll_disable, | |
611 | .recalc_rate = &omap3_dpll_recalc, | |
612 | .round_rate = &omap2_dpll_round_rate, | |
613 | .set_rate = &omap3_noncore_dpll_set_rate, | |
614 | .get_parent = &omap2_init_dpll_parent, | |
615 | .init = &omap2_init_clk_clkdm, | |
616 | }; | |
617 | ||
cb26867e RN |
618 | static struct clk_hw_omap dpll_usb_ck_hw = { |
619 | .hw = { | |
620 | .clk = &dpll_usb_ck, | |
621 | }, | |
622 | .dpll_data = &dpll_usb_dd, | |
d0758237 | 623 | .clkdm_name = "l3_init_clkdm", |
cb26867e RN |
624 | .ops = &clkhwops_omap3_dpll, |
625 | }; | |
626 | ||
d0758237 | 627 | DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops); |
cb26867e RN |
628 | |
629 | static const char *dpll_usb_clkdcoldo_ck_parents[] = { | |
630 | "dpll_usb_ck", | |
631 | }; | |
632 | ||
633 | static struct clk dpll_usb_clkdcoldo_ck; | |
634 | ||
635 | static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { | |
636 | }; | |
637 | ||
638 | static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { | |
639 | .hw = { | |
640 | .clk = &dpll_usb_clkdcoldo_ck, | |
641 | }, | |
642 | .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, | |
643 | .ops = &clkhwops_omap4_dpllmx, | |
644 | }; | |
645 | ||
646 | DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, | |
647 | dpll_usb_clkdcoldo_ck_ops); | |
648 | ||
649 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, | |
650 | OMAP4430_CM_DIV_M2_DPLL_USB, | |
651 | OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); | |
652 | ||
653 | static const char *ducati_clk_mux_ck_parents[] = { | |
654 | "div_core_ck", "dpll_per_m6x2_ck", | |
655 | }; | |
656 | ||
657 | DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, | |
658 | OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, | |
659 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
660 | ||
661 | DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
662 | 0x0, 1, 16); | |
663 | ||
664 | DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, | |
665 | 1, 4); | |
666 | ||
667 | DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
668 | 0x0, 1, 8); | |
669 | ||
670 | static const struct clk_div_table func_48m_fclk_rates[] = { | |
671 | { .div = 4, .val = 0 }, | |
672 | { .div = 8, .val = 1 }, | |
673 | { .div = 0 }, | |
674 | }; | |
675 | DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
676 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
677 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, | |
678 | NULL); | |
679 | ||
680 | DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
681 | 0x0, 1, 4); | |
682 | ||
683 | static const struct clk_div_table func_64m_fclk_rates[] = { | |
684 | { .div = 2, .val = 0 }, | |
685 | { .div = 4, .val = 1 }, | |
686 | { .div = 0 }, | |
687 | }; | |
688 | DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, | |
689 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
690 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, | |
691 | NULL); | |
692 | ||
693 | static const struct clk_div_table func_96m_fclk_rates[] = { | |
694 | { .div = 2, .val = 0 }, | |
695 | { .div = 4, .val = 1 }, | |
696 | { .div = 0 }, | |
697 | }; | |
698 | DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
699 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
700 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, | |
701 | NULL); | |
702 | ||
703 | static const struct clk_div_table init_60m_fclk_rates[] = { | |
704 | { .div = 1, .val = 0 }, | |
705 | { .div = 8, .val = 1 }, | |
706 | { .div = 0 }, | |
707 | }; | |
708 | DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, | |
709 | 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, | |
710 | OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, | |
711 | 0x0, init_60m_fclk_rates, NULL); | |
712 | ||
713 | DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, | |
714 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, | |
715 | OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); | |
716 | ||
717 | DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, | |
718 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, | |
719 | OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); | |
720 | ||
721 | DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, | |
722 | 0x0, 1, 16); | |
723 | ||
724 | static const char *l4_wkup_clk_mux_ck_parents[] = { | |
725 | "sys_clkin_ck", "lp_clk_div_ck", | |
726 | }; | |
727 | ||
728 | DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, | |
729 | OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
730 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
731 | ||
732 | static const struct clk_div_table ocp_abe_iclk_rates[] = { | |
733 | { .div = 2, .val = 0 }, | |
734 | { .div = 1, .val = 1 }, | |
735 | { .div = 0 }, | |
736 | }; | |
737 | DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, | |
738 | OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
739 | OMAP4430_CLKSEL_AESS_FCLK_SHIFT, | |
740 | OMAP4430_CLKSEL_AESS_FCLK_WIDTH, | |
741 | 0x0, ocp_abe_iclk_rates, NULL); | |
742 | ||
743 | DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, | |
744 | 0x0, 1, 4); | |
745 | ||
746 | DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, | |
747 | OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
748 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); | |
749 | ||
750 | DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, | |
751 | OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
752 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
753 | ||
b8675e2c PW |
754 | static const char *dbgclk_mux_ck_parents[] = { |
755 | "sys_clkin_ck" | |
756 | }; | |
757 | ||
cb26867e RN |
758 | static struct clk dbgclk_mux_ck; |
759 | DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); | |
b8675e2c | 760 | DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents, |
cb26867e RN |
761 | dpll_usb_clkdcoldo_ck_ops); |
762 | ||
763 | /* Leaf clocks controlled by modules */ | |
764 | ||
765 | DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
766 | OMAP4430_CM_L4SEC_AES1_CLKCTRL, | |
767 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
768 | ||
769 | DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
770 | OMAP4430_CM_L4SEC_AES2_CLKCTRL, | |
771 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
772 | ||
cb26867e RN |
773 | DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
774 | OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
775 | OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); | |
776 | ||
777 | static const struct clk_div_table div_ts_ck_rates[] = { | |
778 | { .div = 8, .val = 0 }, | |
779 | { .div = 16, .val = 1 }, | |
780 | { .div = 32, .val = 2 }, | |
781 | { .div = 0 }, | |
782 | }; | |
783 | DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
784 | 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
785 | OMAP4430_CLKSEL_24_25_SHIFT, | |
786 | OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, | |
787 | NULL); | |
788 | ||
789 | DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, | |
790 | OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
791 | OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, | |
792 | 0x0, NULL); | |
793 | ||
cb26867e RN |
794 | static const char *dmic_sync_mux_ck_parents[] = { |
795 | "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", | |
796 | }; | |
797 | ||
798 | DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, | |
799 | 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
800 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
801 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
802 | ||
803 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | |
804 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | |
805 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
806 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
807 | { .parent = NULL }, | |
808 | }; | |
809 | ||
ee877acd | 810 | static const char *func_dmic_abe_gfclk_parents[] = { |
cb26867e RN |
811 | "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", |
812 | }; | |
813 | ||
ee877acd PW |
814 | DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel, |
815 | OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, | |
816 | func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops); | |
cb26867e | 817 | |
cb26867e RN |
818 | DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, |
819 | OMAP4430_CM_DSS_DSS_CLKCTRL, | |
820 | OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); | |
821 | ||
822 | DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, | |
823 | OMAP4430_CM_DSS_DSS_CLKCTRL, | |
824 | OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); | |
825 | ||
826 | DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, | |
827 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | |
828 | 0x0, NULL); | |
829 | ||
830 | DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, | |
831 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, | |
832 | 0x0, NULL); | |
833 | ||
834 | DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
835 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
836 | 0x0, NULL); | |
837 | ||
cb26867e RN |
838 | DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, |
839 | OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, | |
840 | OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
841 | ||
cb26867e RN |
842 | DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
843 | OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
844 | OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); | |
845 | ||
cb26867e RN |
846 | DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
847 | OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
848 | 0x0, NULL); | |
849 | ||
cb26867e RN |
850 | DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
851 | OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
852 | OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); | |
853 | ||
cb26867e RN |
854 | DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
855 | OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
856 | 0x0, NULL); | |
857 | ||
cb26867e RN |
858 | DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
859 | OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
860 | 0x0, NULL); | |
861 | ||
cb26867e RN |
862 | DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, |
863 | OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
864 | 0x0, NULL); | |
865 | ||
cb26867e RN |
866 | static const struct clksel sgx_clk_mux_sel[] = { |
867 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, | |
868 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, | |
869 | { .parent = NULL }, | |
870 | }; | |
871 | ||
ee877acd | 872 | static const char *sgx_clk_mux_parents[] = { |
cb26867e RN |
873 | "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", |
874 | }; | |
875 | ||
ee877acd PW |
876 | DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel, |
877 | OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK, | |
878 | sgx_clk_mux_parents, func_dmic_abe_gfclk_ops); | |
cb26867e | 879 | |
cb26867e RN |
880 | DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, |
881 | OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, | |
882 | OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | |
883 | NULL); | |
884 | ||
cb26867e RN |
885 | DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, |
886 | OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, | |
887 | 0x0, NULL); | |
888 | ||
cb26867e RN |
889 | DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, |
890 | OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
891 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
892 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
893 | ||
894 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |
895 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | |
896 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
897 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
898 | { .parent = NULL }, | |
899 | }; | |
900 | ||
ee877acd | 901 | static const char *func_mcasp_abe_gfclk_parents[] = { |
cb26867e RN |
902 | "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", |
903 | }; | |
904 | ||
ee877acd PW |
905 | DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel, |
906 | OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, | |
907 | func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops); | |
cb26867e RN |
908 | |
909 | DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
910 | OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
911 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
912 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
913 | ||
914 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | |
915 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | |
916 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
917 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
918 | { .parent = NULL }, | |
919 | }; | |
920 | ||
ee877acd | 921 | static const char *func_mcbsp1_gfclk_parents[] = { |
cb26867e RN |
922 | "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", |
923 | }; | |
924 | ||
ee877acd PW |
925 | DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel, |
926 | OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
927 | OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents, | |
928 | func_dmic_abe_gfclk_ops); | |
cb26867e RN |
929 | |
930 | DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
931 | OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
932 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
933 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
934 | ||
935 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | |
936 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | |
937 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
938 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
939 | { .parent = NULL }, | |
940 | }; | |
941 | ||
ee877acd | 942 | static const char *func_mcbsp2_gfclk_parents[] = { |
cb26867e RN |
943 | "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", |
944 | }; | |
945 | ||
ee877acd PW |
946 | DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel, |
947 | OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
948 | OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents, | |
949 | func_dmic_abe_gfclk_ops); | |
cb26867e RN |
950 | |
951 | DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
952 | OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
953 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
954 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
955 | ||
956 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | |
957 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | |
958 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
959 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
960 | { .parent = NULL }, | |
961 | }; | |
962 | ||
ee877acd | 963 | static const char *func_mcbsp3_gfclk_parents[] = { |
cb26867e RN |
964 | "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", |
965 | }; | |
966 | ||
ee877acd PW |
967 | DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel, |
968 | OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
969 | OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents, | |
970 | func_dmic_abe_gfclk_ops); | |
cb26867e RN |
971 | |
972 | static const char *mcbsp4_sync_mux_ck_parents[] = { | |
973 | "func_96m_fclk", "per_abe_nc_fclk", | |
974 | }; | |
975 | ||
976 | DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, | |
977 | OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
978 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
979 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
980 | ||
981 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | |
982 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | |
983 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
984 | { .parent = NULL }, | |
985 | }; | |
986 | ||
ee877acd | 987 | static const char *per_mcbsp4_gfclk_parents[] = { |
cb26867e RN |
988 | "mcbsp4_sync_mux_ck", "pad_clks_ck", |
989 | }; | |
990 | ||
ee877acd PW |
991 | DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel, |
992 | OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
993 | OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents, | |
994 | func_dmic_abe_gfclk_ops); | |
cb26867e | 995 | |
cb26867e RN |
996 | static const struct clksel hsmmc1_fclk_sel[] = { |
997 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | |
998 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | |
999 | { .parent = NULL }, | |
1000 | }; | |
1001 | ||
ee877acd | 1002 | static const char *hsmmc1_fclk_parents[] = { |
cb26867e RN |
1003 | "func_64m_fclk", "func_96m_fclk", |
1004 | }; | |
1005 | ||
ee877acd PW |
1006 | DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, |
1007 | OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1008 | hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); | |
cb26867e | 1009 | |
ee877acd PW |
1010 | DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, |
1011 | OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1012 | hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); | |
cb26867e | 1013 | |
cb26867e RN |
1014 | DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, |
1015 | OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | |
1016 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1017 | ||
cb26867e RN |
1018 | DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, |
1019 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1020 | OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); | |
1021 | ||
1022 | DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, | |
1023 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1024 | OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); | |
1025 | ||
1026 | DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, | |
1027 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1028 | OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); | |
1029 | ||
1030 | DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, | |
1031 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1032 | OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); | |
1033 | ||
cb26867e RN |
1034 | DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, |
1035 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1036 | OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); | |
1037 | ||
1038 | DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, | |
1039 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1040 | OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); | |
1041 | ||
1042 | DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", | |
1043 | &pad_slimbus_core_clks_ck, 0x0, | |
1044 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1045 | OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); | |
1046 | ||
cb26867e RN |
1047 | DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, |
1048 | 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
1049 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1050 | ||
1051 | DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
1052 | 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
1053 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1054 | ||
1055 | DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
1056 | 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
1057 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1058 | ||
1059 | static const struct clksel dmt1_clk_mux_sel[] = { | |
1060 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1061 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
1062 | { .parent = NULL }, | |
1063 | }; | |
1064 | ||
ee877acd PW |
1065 | DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel, |
1066 | OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1067 | abe_dpll_bypass_clk_mux_ck_parents, | |
1068 | func_dmic_abe_gfclk_ops); | |
1069 | ||
1070 | DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1071 | OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1072 | abe_dpll_bypass_clk_mux_ck_parents, | |
1073 | func_dmic_abe_gfclk_ops); | |
1074 | ||
1075 | DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1076 | OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1077 | abe_dpll_bypass_clk_mux_ck_parents, | |
1078 | func_dmic_abe_gfclk_ops); | |
1079 | ||
1080 | DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1081 | OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1082 | abe_dpll_bypass_clk_mux_ck_parents, | |
1083 | func_dmic_abe_gfclk_ops); | |
1084 | ||
1085 | DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1086 | OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1087 | abe_dpll_bypass_clk_mux_ck_parents, | |
1088 | func_dmic_abe_gfclk_ops); | |
1089 | ||
1090 | DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1091 | OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1092 | abe_dpll_bypass_clk_mux_ck_parents, | |
1093 | func_dmic_abe_gfclk_ops); | |
cb26867e RN |
1094 | |
1095 | static const struct clksel timer5_sync_mux_sel[] = { | |
1096 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | |
1097 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
1098 | { .parent = NULL }, | |
1099 | }; | |
1100 | ||
ee877acd | 1101 | static const char *timer5_sync_mux_parents[] = { |
cb26867e RN |
1102 | "syc_clk_div_ck", "sys_32k_ck", |
1103 | }; | |
1104 | ||
ee877acd PW |
1105 | DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel, |
1106 | OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1107 | timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); | |
1108 | ||
1109 | DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel, | |
1110 | OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1111 | timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); | |
1112 | ||
1113 | DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel, | |
1114 | OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1115 | timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); | |
1116 | ||
1117 | DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel, | |
1118 | OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1119 | timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); | |
1120 | ||
1121 | DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1122 | OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1123 | abe_dpll_bypass_clk_mux_ck_parents, | |
1124 | func_dmic_abe_gfclk_ops); | |
cb26867e | 1125 | |
cb26867e RN |
1126 | static struct clk usb_host_fs_fck; |
1127 | ||
1128 | static const char *usb_host_fs_fck_parent_names[] = { | |
1129 | "func_48mc_fclk", | |
1130 | }; | |
1131 | ||
1132 | static const struct clk_ops usb_host_fs_fck_ops = { | |
1133 | .enable = &omap2_dflt_clk_enable, | |
1134 | .disable = &omap2_dflt_clk_disable, | |
1135 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
1136 | }; | |
1137 | ||
1138 | static struct clk_hw_omap usb_host_fs_fck_hw = { | |
1139 | .hw = { | |
1140 | .clk = &usb_host_fs_fck, | |
1141 | }, | |
1142 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, | |
1143 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
1144 | .clkdm_name = "l3_init_clkdm", | |
1145 | }; | |
1146 | ||
1147 | DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, | |
1148 | usb_host_fs_fck_ops); | |
1149 | ||
1150 | static const char *utmi_p1_gfclk_parents[] = { | |
1151 | "init_60m_fclk", "xclk60mhsp1_ck", | |
1152 | }; | |
1153 | ||
1154 | DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, | |
1155 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1156 | OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, | |
1157 | 0x0, NULL); | |
1158 | ||
1159 | DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, | |
1160 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1161 | OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); | |
1162 | ||
1163 | static const char *utmi_p2_gfclk_parents[] = { | |
1164 | "init_60m_fclk", "xclk60mhsp2_ck", | |
1165 | }; | |
1166 | ||
1167 | DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, | |
1168 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1169 | OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, | |
1170 | 0x0, NULL); | |
1171 | ||
1172 | DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, | |
1173 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1174 | OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); | |
1175 | ||
1176 | DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1177 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1178 | OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); | |
1179 | ||
1180 | DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", | |
1181 | &dpll_usb_m2_ck, 0x0, | |
1182 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1183 | OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); | |
1184 | ||
1185 | DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", | |
1186 | &init_60m_fclk, 0x0, | |
1187 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1188 | OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); | |
1189 | ||
1190 | DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", | |
1191 | &init_60m_fclk, 0x0, | |
1192 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1193 | OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); | |
1194 | ||
1195 | DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", | |
1196 | &dpll_usb_m2_ck, 0x0, | |
1197 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1198 | OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); | |
1199 | ||
1200 | DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, | |
1201 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1202 | OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); | |
1203 | ||
1204 | DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1205 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1206 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1207 | ||
1208 | static const char *otg_60m_gfclk_parents[] = { | |
1209 | "utmi_phy_clkout_ck", "xclk60motg_ck", | |
1210 | }; | |
1211 | ||
1212 | DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, | |
1213 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, | |
1214 | OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); | |
1215 | ||
1216 | DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, | |
1217 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
1218 | OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); | |
1219 | ||
1220 | DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, | |
1221 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
1222 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
1223 | ||
1224 | DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, | |
1225 | OMAP4430_CM_ALWON_USBPHY_CLKCTRL, | |
1226 | OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); | |
1227 | ||
1228 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1229 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1230 | OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); | |
1231 | ||
1232 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1233 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1234 | OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); | |
1235 | ||
1236 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1237 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1238 | OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); | |
1239 | ||
1240 | DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
1241 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1242 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
1243 | ||
1244 | static const struct clk_div_table usim_ck_rates[] = { | |
1245 | { .div = 14, .val = 0 }, | |
1246 | { .div = 18, .val = 1 }, | |
1247 | { .div = 0 }, | |
1248 | }; | |
1249 | DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, | |
1250 | OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
1251 | OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, | |
1252 | 0x0, usim_ck_rates, NULL); | |
1253 | ||
1254 | DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, | |
1255 | OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, | |
1256 | 0x0, NULL); | |
1257 | ||
cb26867e RN |
1258 | /* Remaining optional clocks */ |
1259 | static const char *pmd_stm_clock_mux_ck_parents[] = { | |
1260 | "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", | |
1261 | }; | |
1262 | ||
1263 | DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, | |
1264 | OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, | |
1265 | OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); | |
1266 | ||
1267 | DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, | |
1268 | OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1269 | OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, | |
1270 | OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); | |
1271 | ||
1272 | DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", | |
1273 | &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1274 | OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, | |
1275 | OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | |
1276 | NULL); | |
1277 | ||
1278 | static const char *trace_clk_div_ck_parents[] = { | |
1279 | "pmd_trace_clk_mux_ck", | |
1280 | }; | |
1281 | ||
1282 | static const struct clksel trace_clk_div_div[] = { | |
1283 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | |
1284 | { .parent = NULL }, | |
1285 | }; | |
1286 | ||
1287 | static struct clk trace_clk_div_ck; | |
1288 | ||
1289 | static const struct clk_ops trace_clk_div_ck_ops = { | |
1290 | .recalc_rate = &omap2_clksel_recalc, | |
1291 | .set_rate = &omap2_clksel_set_rate, | |
1292 | .round_rate = &omap2_clksel_round_rate, | |
1293 | .init = &omap2_init_clk_clkdm, | |
1294 | .enable = &omap2_clkops_enable_clkdm, | |
1295 | .disable = &omap2_clkops_disable_clkdm, | |
1296 | }; | |
1297 | ||
1298 | static struct clk_hw_omap trace_clk_div_ck_hw = { | |
1299 | .hw = { | |
1300 | .clk = &trace_clk_div_ck, | |
1301 | }, | |
1302 | .clkdm_name = "emu_sys_clkdm", | |
1303 | .clksel = trace_clk_div_div, | |
1304 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1305 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | |
1306 | }; | |
1307 | ||
1308 | DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, | |
1309 | trace_clk_div_ck_ops); | |
1310 | ||
1311 | /* SCRM aux clk nodes */ | |
1312 | ||
1313 | static const struct clksel auxclk_src_sel[] = { | |
1314 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1315 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, | |
1316 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, | |
1317 | { .parent = NULL }, | |
1318 | }; | |
1319 | ||
1320 | static const char *auxclk_src_ck_parents[] = { | |
1321 | "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", | |
1322 | }; | |
1323 | ||
1324 | static const struct clk_ops auxclk_src_ck_ops = { | |
1325 | .enable = &omap2_dflt_clk_enable, | |
1326 | .disable = &omap2_dflt_clk_disable, | |
1327 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
1328 | .recalc_rate = &omap2_clksel_recalc, | |
1329 | .get_parent = &omap2_clksel_find_parent_index, | |
1330 | }; | |
1331 | ||
1332 | DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, | |
1333 | OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, | |
1334 | OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, | |
1335 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1336 | ||
1337 | DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, | |
1338 | OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1339 | 0x0, NULL); | |
1340 | ||
1341 | DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, | |
1342 | OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, | |
1343 | OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, | |
1344 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1345 | ||
1346 | DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, | |
1347 | OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1348 | 0x0, NULL); | |
1349 | ||
1350 | DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, | |
1351 | OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, | |
1352 | OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, | |
1353 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1354 | ||
1355 | DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, | |
1356 | OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1357 | 0x0, NULL); | |
1358 | ||
1359 | DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, | |
1360 | OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, | |
1361 | OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, | |
1362 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1363 | ||
1364 | DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, | |
1365 | OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1366 | 0x0, NULL); | |
1367 | ||
1368 | DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, | |
1369 | OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, | |
1370 | OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, | |
1371 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1372 | ||
1373 | DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, | |
1374 | OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1375 | 0x0, NULL); | |
1376 | ||
1377 | DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, | |
1378 | OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, | |
1379 | OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, | |
1380 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1381 | ||
1382 | DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, | |
1383 | OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1384 | 0x0, NULL); | |
1385 | ||
1386 | static const char *auxclkreq_ck_parents[] = { | |
1387 | "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", | |
1388 | "auxclk5_ck", | |
1389 | }; | |
1390 | ||
1391 | DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1392 | OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1393 | 0x0, NULL); | |
1394 | ||
1395 | DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1396 | OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1397 | 0x0, NULL); | |
1398 | ||
1399 | DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1400 | OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1401 | 0x0, NULL); | |
1402 | ||
1403 | DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1404 | OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1405 | 0x0, NULL); | |
1406 | ||
1407 | DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1408 | OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1409 | 0x0, NULL); | |
1410 | ||
1411 | DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1412 | OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1413 | 0x0, NULL); | |
1414 | ||
1415 | /* | |
78e52e02 | 1416 | * clocks specific to omap4460 |
cb26867e | 1417 | */ |
78e52e02 K |
1418 | static struct omap_clk omap446x_clks[] = { |
1419 | CLK(NULL, "div_ts_ck", &div_ts_ck), | |
1420 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk), | |
1421 | }; | |
1422 | ||
1423 | /* | |
1424 | * clocks specific to omap4430 | |
1425 | */ | |
1426 | static struct omap_clk omap443x_clks[] = { | |
1427 | CLK(NULL, "bandgap_fclk", &bandgap_fclk), | |
1428 | }; | |
cb26867e | 1429 | |
78e52e02 K |
1430 | /* |
1431 | * clocks common to omap44xx | |
1432 | */ | |
cb26867e | 1433 | static struct omap_clk omap44xx_clks[] = { |
78e52e02 K |
1434 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck), |
1435 | CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck), | |
1436 | CLK(NULL, "pad_clks_ck", &pad_clks_ck), | |
1437 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck), | |
1438 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck), | |
1439 | CLK(NULL, "slimbus_src_clk", &slimbus_src_clk), | |
1440 | CLK(NULL, "slimbus_clk", &slimbus_clk), | |
1441 | CLK(NULL, "sys_32k_ck", &sys_32k_ck), | |
1442 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck), | |
1443 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck), | |
1444 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck), | |
1445 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), | |
1446 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), | |
1447 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck), | |
1448 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck), | |
1449 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), | |
1450 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck), | |
1451 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck), | |
1452 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck), | |
1453 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck), | |
1454 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck), | |
1455 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck), | |
1456 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck), | |
1457 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck), | |
1458 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck), | |
1459 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck), | |
1460 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk), | |
1461 | CLK(NULL, "abe_clk", &abe_clk), | |
1462 | CLK(NULL, "aess_fclk", &aess_fclk), | |
1463 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck), | |
1464 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck), | |
1465 | CLK(NULL, "dpll_core_ck", &dpll_core_ck), | |
1466 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), | |
1467 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck), | |
1468 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck), | |
1469 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck), | |
1470 | CLK(NULL, "ddrphy_ck", &ddrphy_ck), | |
1471 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck), | |
1472 | CLK(NULL, "div_core_ck", &div_core_ck), | |
1473 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk), | |
1474 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk), | |
1475 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck), | |
1476 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck), | |
1477 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck), | |
1478 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck), | |
1479 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck), | |
1480 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck), | |
1481 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck), | |
1482 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck), | |
1483 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck), | |
1484 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck), | |
1485 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), | |
1486 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), | |
1487 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck), | |
1488 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck), | |
1489 | CLK(NULL, "dpll_per_ck", &dpll_per_ck), | |
1490 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), | |
1491 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck), | |
1492 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck), | |
1493 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck), | |
1494 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck), | |
1495 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck), | |
1496 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck), | |
1497 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck), | |
1498 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck), | |
1499 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck), | |
1500 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck), | |
1501 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck), | |
1502 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck), | |
1503 | CLK(NULL, "func_12m_fclk", &func_12m_fclk), | |
1504 | CLK(NULL, "func_24m_clk", &func_24m_clk), | |
1505 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk), | |
1506 | CLK(NULL, "func_48m_fclk", &func_48m_fclk), | |
1507 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk), | |
1508 | CLK(NULL, "func_64m_fclk", &func_64m_fclk), | |
1509 | CLK(NULL, "func_96m_fclk", &func_96m_fclk), | |
1510 | CLK(NULL, "init_60m_fclk", &init_60m_fclk), | |
1511 | CLK(NULL, "l3_div_ck", &l3_div_ck), | |
1512 | CLK(NULL, "l4_div_ck", &l4_div_ck), | |
1513 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck), | |
1514 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck), | |
1515 | CLK("smp_twd", NULL, &mpu_periphclk), | |
1516 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk), | |
1517 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk), | |
1518 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk), | |
1519 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck), | |
1520 | CLK(NULL, "aes1_fck", &aes1_fck), | |
1521 | CLK(NULL, "aes2_fck", &aes2_fck), | |
1522 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck), | |
1523 | CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk), | |
1524 | CLK(NULL, "dss_sys_clk", &dss_sys_clk), | |
1525 | CLK(NULL, "dss_tv_clk", &dss_tv_clk), | |
1526 | CLK(NULL, "dss_dss_clk", &dss_dss_clk), | |
1527 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk), | |
1528 | CLK(NULL, "dss_fck", &dss_fck), | |
1529 | CLK("omapdss_dss", "ick", &dss_fck), | |
1530 | CLK(NULL, "fdif_fck", &fdif_fck), | |
1531 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), | |
1532 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), | |
1533 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), | |
1534 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk), | |
1535 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk), | |
1536 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk), | |
1537 | CLK(NULL, "sgx_clk_mux", &sgx_clk_mux), | |
1538 | CLK(NULL, "hsi_fck", &hsi_fck), | |
1539 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk), | |
1540 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck), | |
1541 | CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk), | |
1542 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck), | |
1543 | CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk), | |
1544 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck), | |
1545 | CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk), | |
1546 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck), | |
1547 | CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk), | |
1548 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck), | |
1549 | CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk), | |
1550 | CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk), | |
1551 | CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk), | |
1552 | CLK(NULL, "sha2md5_fck", &sha2md5_fck), | |
1553 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1), | |
1554 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0), | |
1555 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2), | |
1556 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk), | |
1557 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1), | |
1558 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0), | |
1559 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk), | |
1560 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck), | |
1561 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck), | |
1562 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck), | |
1563 | CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux), | |
1564 | CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux), | |
1565 | CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux), | |
1566 | CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux), | |
1567 | CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux), | |
1568 | CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux), | |
1569 | CLK(NULL, "timer5_sync_mux", &timer5_sync_mux), | |
1570 | CLK(NULL, "timer6_sync_mux", &timer6_sync_mux), | |
1571 | CLK(NULL, "timer7_sync_mux", &timer7_sync_mux), | |
1572 | CLK(NULL, "timer8_sync_mux", &timer8_sync_mux), | |
1573 | CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux), | |
1574 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck), | |
1575 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck), | |
1576 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk), | |
1577 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk), | |
1578 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk), | |
1579 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk), | |
1580 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk), | |
1581 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk), | |
1582 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk), | |
1583 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk), | |
1584 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk), | |
1585 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk), | |
1586 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck), | |
1587 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck), | |
1588 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk), | |
1589 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk), | |
1590 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick), | |
1591 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick), | |
1592 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k), | |
1593 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk), | |
1594 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk), | |
1595 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk), | |
1596 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick), | |
1597 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick), | |
1598 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick), | |
1599 | CLK(NULL, "usim_ck", &usim_ck), | |
1600 | CLK(NULL, "usim_fclk", &usim_fclk), | |
1601 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck), | |
1602 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck), | |
1603 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), | |
1604 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), | |
1605 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck), | |
1606 | CLK(NULL, "auxclk0_ck", &auxclk0_ck), | |
1607 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck), | |
1608 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck), | |
1609 | CLK(NULL, "auxclk1_ck", &auxclk1_ck), | |
1610 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck), | |
1611 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck), | |
1612 | CLK(NULL, "auxclk2_ck", &auxclk2_ck), | |
1613 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck), | |
1614 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck), | |
1615 | CLK(NULL, "auxclk3_ck", &auxclk3_ck), | |
1616 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck), | |
1617 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck), | |
1618 | CLK(NULL, "auxclk4_ck", &auxclk4_ck), | |
1619 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck), | |
1620 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), | |
1621 | CLK(NULL, "auxclk5_ck", &auxclk5_ck), | |
1622 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), | |
1623 | CLK("omap-gpmc", "fck", &dummy_ck), | |
1624 | CLK("omap_i2c.1", "ick", &dummy_ck), | |
1625 | CLK("omap_i2c.2", "ick", &dummy_ck), | |
1626 | CLK("omap_i2c.3", "ick", &dummy_ck), | |
1627 | CLK("omap_i2c.4", "ick", &dummy_ck), | |
1628 | CLK(NULL, "mailboxes_ick", &dummy_ck), | |
1629 | CLK("omap_hsmmc.0", "ick", &dummy_ck), | |
1630 | CLK("omap_hsmmc.1", "ick", &dummy_ck), | |
1631 | CLK("omap_hsmmc.2", "ick", &dummy_ck), | |
1632 | CLK("omap_hsmmc.3", "ick", &dummy_ck), | |
1633 | CLK("omap_hsmmc.4", "ick", &dummy_ck), | |
1634 | CLK("omap-mcbsp.1", "ick", &dummy_ck), | |
1635 | CLK("omap-mcbsp.2", "ick", &dummy_ck), | |
1636 | CLK("omap-mcbsp.3", "ick", &dummy_ck), | |
1637 | CLK("omap-mcbsp.4", "ick", &dummy_ck), | |
1638 | CLK("omap2_mcspi.1", "ick", &dummy_ck), | |
1639 | CLK("omap2_mcspi.2", "ick", &dummy_ck), | |
1640 | CLK("omap2_mcspi.3", "ick", &dummy_ck), | |
1641 | CLK("omap2_mcspi.4", "ick", &dummy_ck), | |
1642 | CLK(NULL, "uart1_ick", &dummy_ck), | |
1643 | CLK(NULL, "uart2_ick", &dummy_ck), | |
1644 | CLK(NULL, "uart3_ick", &dummy_ck), | |
1645 | CLK(NULL, "uart4_ick", &dummy_ck), | |
1646 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck), | |
1647 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck), | |
1648 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck), | |
1649 | CLK("omap_wdt", "ick", &dummy_ck), | |
1650 | CLK(NULL, "timer_32k_ck", &sys_32k_ck), | |
cb26867e | 1651 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ |
78e52e02 K |
1652 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck), |
1653 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck), | |
1654 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck), | |
1655 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck), | |
1656 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck), | |
1657 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck), | |
1658 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck), | |
1659 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck), | |
1660 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck), | |
1661 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck), | |
1662 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck), | |
1663 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1664 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1665 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1666 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1667 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1668 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1669 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck), | |
1670 | CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck), | |
1671 | CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck), | |
1672 | CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck), | |
1673 | CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck), | |
1674 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck), | |
cb26867e RN |
1675 | }; |
1676 | ||
cb26867e RN |
1677 | int __init omap4xxx_clk_init(void) |
1678 | { | |
8c197ccf | 1679 | int rc; |
cb26867e RN |
1680 | |
1681 | if (cpu_is_omap443x()) { | |
1682 | cpu_mask = RATE_IN_4430; | |
78e52e02 | 1683 | omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks)); |
cb26867e RN |
1684 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { |
1685 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; | |
78e52e02 | 1686 | omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks)); |
cb26867e RN |
1687 | if (cpu_is_omap447x()) |
1688 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); | |
1689 | } else { | |
1690 | return 0; | |
1691 | } | |
1692 | ||
78e52e02 | 1693 | omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks)); |
cb26867e RN |
1694 | |
1695 | omap2_clk_disable_autoidle_all(); | |
1696 | ||
8c197ccf JH |
1697 | /* |
1698 | * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power | |
1699 | * state when turning the ABE clock domain. Workaround this by | |
1700 | * locking the ABE DPLL on boot. | |
981827a2 | 1701 | * Lock the ABE DPLL in any case to avoid issues with audio. |
8c197ccf | 1702 | */ |
981827a2 PU |
1703 | rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); |
1704 | if (!rc) | |
1705 | rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); | |
1706 | if (rc) | |
1707 | pr_err("%s: failed to configure ABE DPLL!\n", __func__); | |
8c197ccf | 1708 | |
cb26867e RN |
1709 | return 0; |
1710 | } |