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0fd0c21b PW |
1 | /* |
2 | * OMAP2-specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2011 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | ||
0fd0c21b | 17 | #include "clock.h" |
ff4ae5d9 | 18 | #include "cm2xxx.h" |
0fd0c21b PW |
19 | #include "cm-regbits-24xx.h" |
20 | ||
21 | /* Private functions */ | |
22 | ||
23 | /** | |
24 | * _allow_idle - enable DPLL autoidle bits | |
25 | * @clk: struct clk * of the DPLL to operate on | |
26 | * | |
27 | * Enable DPLL automatic idle control. The DPLL will enter low-power | |
28 | * stop when its downstream clocks are gated. No return value. | |
29 | * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 | |
30 | * instead. Add some mechanism to optionally enter this mode. | |
31 | */ | |
ed1ebc49 | 32 | static void _allow_idle(struct clk_hw_omap *clk) |
0fd0c21b PW |
33 | { |
34 | if (!clk || !clk->dpll_data) | |
35 | return; | |
36 | ||
37 | omap2xxx_cm_set_dpll_auto_low_power_stop(); | |
38 | } | |
39 | ||
40 | /** | |
41 | * _deny_idle - prevent DPLL from automatically idling | |
42 | * @clk: struct clk * of the DPLL to operate on | |
43 | * | |
44 | * Disable DPLL automatic idle control. No return value. | |
45 | */ | |
ed1ebc49 | 46 | static void _deny_idle(struct clk_hw_omap *clk) |
0fd0c21b PW |
47 | { |
48 | if (!clk || !clk->dpll_data) | |
49 | return; | |
50 | ||
51 | omap2xxx_cm_set_dpll_disable_autoidle(); | |
52 | } | |
53 | ||
54 | ||
55 | /* Public data */ | |
ed1ebc49 RN |
56 | const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { |
57 | .allow_idle = _allow_idle, | |
58 | .deny_idle = _deny_idle, | |
59 | }; |