[deliverable/linux.git] / arch / arm / mach-omap2 / clkt34xx_dpll3m2.c

/*
 * OMAP34xx M2 divider clock code
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Jouni Högander
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>

#include "clock.h"
#include "clock3xxx.h"
#include "clock34xx.h"
#include "sdrc.h"

#define CYCLES_PER_MHZ			1000000

/*
 * CORE DPLL (DPLL3) M2 divider rate programming functions
 *
 * These call into SRAM code to do the actual CM writes, since the SDRAM
 * is clocked from DPLL3.
 */

/**
 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 * @clk: struct clk * of DPLL to set
 * @rate: rounded target rate
 *
 * Program the DPLL M2 divider with the rounded target rate.  Returns
 * -EINVAL upon error, or 0 upon success.
 */
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
	u32 new_div = 0;
	u32 unlock_dll = 0;
	u32 c;
	unsigned long validrate, sdrcrate, _mpurate;
	struct omap_sdrc_params *sdrc_cs0;
	struct omap_sdrc_params *sdrc_cs1;
	int ret;
	unsigned long clkrate;

	if (!clk || !rate)
		return -EINVAL;

	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	if (validrate != rate)
		return -EINVAL;

	sdrcrate = __clk_get_rate(sdrc_ick_p);
	clkrate = __clk_get_rate(clk);
	if (rate > clkrate)
		sdrcrate <<= ((rate / clkrate) >> 1);
	else
		sdrcrate >>= ((clkrate / rate) >> 1);

	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
	if (ret)
		return -EINVAL;

	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
		pr_debug("clock: will unlock SDRC DLL\n");
		unlock_dll = 1;
	}

	/*
	 * XXX This only needs to be done when the CPU frequency changes
	 */
	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
	c += 1;  /* for safety */
	c *= SDRC_MPURATE_LOOPS;
	c >>= SDRC_MPURATE_SCALE;
	if (c == 0)
		c = 1;

	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
		 clkrate, validrate);
	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	if (sdrc_cs1)
		pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
			 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
			 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);

	if (sdrc_cs1)
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clkrate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	else
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clkrate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  0, 0, 0, 0);
	clk->rate = rate;

	return 0;
}
Commit	Line	Data
35e424e2 PW	1	/*
	2	* OMAP34xx M2 divider clock code
	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2007-2010 Nokia Corporation
	6	*
	7	* Paul Walmsley
	8	* Jouni Högander
	9	*
	10	* Parts of this code are based on code written by
	11	* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17	#undef DEBUG
	18
	19	#include <linux/kernel.h>
	20	#include <linux/errno.h>
	21	#include <linux/clk.h>
	22	#include <linux/io.h>
	23
	24	#include <plat/clock.h>
	25	#include <plat/sram.h>
	26	#include <plat/sdrc.h>
	27
	28	#include "clock.h"
657ebfad	29	#include "clock3xxx.h"
35e424e2 PW	30	#include "clock34xx.h"
	31	#include "sdrc.h"
	32
	33	#define CYCLES_PER_MHZ 1000000
	34
	35	/*
	36	* CORE DPLL (DPLL3) M2 divider rate programming functions
	37	*
	38	* These call into SRAM code to do the actual CM writes, since the SDRAM
	39	* is clocked from DPLL3.
	40	*/
	41
	42	/**
	43	* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
	44	* @clk: struct clk * of DPLL to set
	45	* @rate: rounded target rate
	46	*
	47	* Program the DPLL M2 divider with the rounded target rate. Returns
	48	* -EINVAL upon error, or 0 upon success.
	49	*/
	50	int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
	51	{
	52	u32 new_div = 0;
	53	u32 unlock_dll = 0;
	54	u32 c;
	55	unsigned long validrate, sdrcrate, _mpurate;
	56	struct omap_sdrc_params *sdrc_cs0;
	57	struct omap_sdrc_params *sdrc_cs1;
	58	int ret;
5dcc3b97	59	unsigned long clkrate;
35e424e2 PW	60
	61	if (!clk \|\| !rate)
	62	return -EINVAL;
	63
	64	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	65	if (validrate != rate)
	66	return -EINVAL;
	67
5dcc3b97 RN	68	sdrcrate = __clk_get_rate(sdrc_ick_p);
	69	clkrate = __clk_get_rate(clk);
	70	if (rate > clkrate)
	71	sdrcrate <<= ((rate / clkrate) >> 1);
35e424e2	72	else
5dcc3b97	73	sdrcrate >>= ((clkrate / rate) >> 1);
35e424e2 PW	74
	75	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
	76	if (ret)
	77	return -EINVAL;
	78
	79	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
	80	pr_debug("clock: will unlock SDRC DLL\n");
	81	unlock_dll = 1;
	82	}
	83
	84	/*
	85	* XXX This only needs to be done when the CPU frequency changes
	86	*/
5dcc3b97	87	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
35e424e2 PW	88	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
	89	c += 1; /* for safety */
	90	c *= SDRC_MPURATE_LOOPS;
	91	c >>= SDRC_MPURATE_SCALE;
	92	if (c == 0)
	93	c = 1;
	94
5dcc3b97 RN	95	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
5dcc3b97 RN	96	clkrate, validrate);
7852ec05	97	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
35e424e2 PW	98	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	99	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	100	if (sdrc_cs1)
7852ec05 PW	101	pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
	102	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	103	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
35e424e2 PW	104
	105	if (sdrc_cs1)
	106	omap3_configure_core_dpll(
5dcc3b97	107	new_div, unlock_dll, c, rate > clkrate,
35e424e2 PW	108	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	109	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	110	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	111	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	112	else
	113	omap3_configure_core_dpll(
5dcc3b97	114	new_div, unlock_dll, c, rate > clkrate,
35e424e2 PW	115	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	116	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	117	0, 0, 0, 0);
5fd2a84a	118	clk->rate = rate;
35e424e2 PW	119
	120	return 0;
	121	}
	122