Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
1fe9be82 | 18 | #include <linux/export.h> |
543d9378 PW |
19 | #include <linux/list.h> |
20 | #include <linux/errno.h> | |
4d30e82c PW |
21 | #include <linux/err.h> |
22 | #include <linux/delay.h> | |
32cc0021 | 23 | #include <linux/clk-provider.h> |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
78e52e02 | 26 | #include <linux/clk-private.h> |
5e7c58dc | 27 | #include <asm/cpu.h> |
dbc04161 | 28 | |
dbc04161 TL |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include "soc.h" | |
32 | #include "clockdomain.h" | |
543d9378 | 33 | #include "clock.h" |
c4ceedcb | 34 | #include "cm.h" |
ff4ae5d9 PW |
35 | #include "cm2xxx.h" |
36 | #include "cm3xxx.h" | |
543d9378 PW |
37 | #include "cm-regbits-24xx.h" |
38 | #include "cm-regbits-34xx.h" | |
c4ceedcb PW |
39 | #include "common.h" |
40 | ||
41 | /* | |
42 | * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait | |
43 | * for a module to indicate that it is no longer in idle | |
44 | */ | |
45 | #define MAX_MODULE_ENABLE_WAIT 100000 | |
543d9378 | 46 | |
99541195 | 47 | u16 cpu_mask; |
543d9378 | 48 | |
8111e010 TK |
49 | /* |
50 | * Clock features setup. Used instead of CPU type checks. | |
51 | */ | |
52 | struct ti_clk_features ti_clk_features; | |
53 | ||
a24886e2 TK |
54 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ |
55 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 | |
56 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 | |
57 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 | |
58 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 | |
59 | ||
60 | /* | |
61 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. | |
62 | * From device data manual section 4.3 "DPLL and DLL Specifications". | |
63 | */ | |
64 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 | |
65 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 | |
66 | ||
12706c54 PW |
67 | /* |
68 | * clkdm_control: if true, then when a clock is enabled in the | |
69 | * hardware, its clockdomain will first be enabled; and when a clock | |
70 | * is disabled in the hardware, its clockdomain will be disabled | |
71 | * afterwards. | |
72 | */ | |
73 | static bool clkdm_control = true; | |
74 | ||
23fb8ba3 | 75 | static LIST_HEAD(clk_hw_omap_clocks); |
3ada6b10 TK |
76 | void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; |
77 | ||
78 | void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) | |
79 | { | |
80 | if (clk->flags & MEMMAP_ADDRESSING) { | |
81 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
82 | writel_relaxed(val, clk_memmaps[r->index] + r->offset); | |
83 | } else { | |
84 | writel_relaxed(val, reg); | |
85 | } | |
86 | } | |
87 | ||
88 | u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) | |
89 | { | |
90 | u32 val; | |
91 | ||
92 | if (clk->flags & MEMMAP_ADDRESSING) { | |
93 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
94 | val = readl_relaxed(clk_memmaps[r->index] + r->offset); | |
95 | } else { | |
96 | val = readl_relaxed(reg); | |
97 | } | |
98 | ||
99 | return val; | |
100 | } | |
32cc0021 | 101 | |
30962d9d PW |
102 | /* |
103 | * OMAP2+ specific clock functions | |
104 | */ | |
543d9378 | 105 | |
4b1f76ed PW |
106 | /* Private functions */ |
107 | ||
c4ceedcb PW |
108 | |
109 | /** | |
110 | * _wait_idlest_generic - wait for a module to leave the idle state | |
519ab8b2 | 111 | * @clk: module clock to wait for (needed for register offsets) |
c4ceedcb PW |
112 | * @reg: virtual address of module IDLEST register |
113 | * @mask: value to mask against to determine if the module is active | |
114 | * @idlest: idle state indicator (0 or 1) for the clock | |
115 | * @name: name of the clock (for printk) | |
116 | * | |
117 | * Wait for a module to leave idle, where its idle-status register is | |
118 | * not inside the CM module. Returns 1 if the module left idle | |
119 | * promptly, or 0 if the module did not leave idle before the timeout | |
120 | * elapsed. XXX Deprecated - should be moved into drivers for the | |
121 | * individual IP block that the IDLEST register exists in. | |
122 | */ | |
519ab8b2 TK |
123 | static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, |
124 | u32 mask, u8 idlest, const char *name) | |
c4ceedcb PW |
125 | { |
126 | int i = 0, ena = 0; | |
127 | ||
128 | ena = (idlest) ? 0 : mask; | |
129 | ||
519ab8b2 | 130 | omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), |
c4ceedcb PW |
131 | MAX_MODULE_ENABLE_WAIT, i); |
132 | ||
133 | if (i < MAX_MODULE_ENABLE_WAIT) | |
134 | pr_debug("omap clock: module associated with clock %s ready after %d loops\n", | |
135 | name, i); | |
136 | else | |
137 | pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", | |
138 | name, MAX_MODULE_ENABLE_WAIT); | |
139 | ||
140 | return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; | |
141 | }; | |
142 | ||
4b1f76ed PW |
143 | /** |
144 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
145 | * @clk: struct clk * belonging to the module | |
146 | * | |
147 | * If the necessary clocks for the OMAP hardware IP block that | |
148 | * corresponds to clock @clk are enabled, then wait for the module to | |
149 | * indicate readiness (i.e., to leave IDLE). This code does not | |
150 | * belong in the clock code and will be moved in the medium term to | |
151 | * module-dependent code. No return value. | |
152 | */ | |
32cc0021 | 153 | static void _omap2_module_wait_ready(struct clk_hw_omap *clk) |
4b1f76ed PW |
154 | { |
155 | void __iomem *companion_reg, *idlest_reg; | |
c4ceedcb PW |
156 | u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; |
157 | s16 prcm_mod; | |
158 | int r; | |
4b1f76ed PW |
159 | |
160 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
161 | if (clk->ops->find_companion) { | |
162 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
519ab8b2 | 163 | if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) |
4b1f76ed PW |
164 | return; |
165 | } | |
166 | ||
419cc97d | 167 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
c4ceedcb PW |
168 | r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); |
169 | if (r) { | |
170 | /* IDLEST register not in the CM module */ | |
519ab8b2 TK |
171 | _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), |
172 | idlest_val, __clk_get_name(clk->hw.clk)); | |
c4ceedcb | 173 | } else { |
021b6ff0 TK |
174 | omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id, |
175 | idlest_bit); | |
c4ceedcb | 176 | }; |
4b1f76ed PW |
177 | } |
178 | ||
4b1f76ed PW |
179 | /* Public functions */ |
180 | ||
333943ba PW |
181 | /** |
182 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
183 | * @clk: OMAP clock struct ptr to use | |
184 | * | |
185 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
186 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
187 | * called during clk_register(). No return value. | |
188 | */ | |
32cc0021 MT |
189 | void omap2_init_clk_clkdm(struct clk_hw *hw) |
190 | { | |
191 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
333943ba | 192 | struct clockdomain *clkdm; |
5dcc3b97 | 193 | const char *clk_name; |
333943ba PW |
194 | |
195 | if (!clk->clkdm_name) | |
196 | return; | |
197 | ||
32cc0021 | 198 | clk_name = __clk_get_name(hw->clk); |
5dcc3b97 | 199 | |
333943ba PW |
200 | clkdm = clkdm_lookup(clk->clkdm_name); |
201 | if (clkdm) { | |
202 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
5dcc3b97 | 203 | clk_name, clk->clkdm_name); |
333943ba PW |
204 | clk->clkdm = clkdm; |
205 | } else { | |
7852ec05 | 206 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
5dcc3b97 | 207 | clk_name, clk->clkdm_name); |
333943ba PW |
208 | } |
209 | } | |
210 | ||
12706c54 PW |
211 | /** |
212 | * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable | |
213 | * | |
214 | * Prevent the OMAP clock code from calling into the clockdomain code | |
215 | * when a hardware clock in that clockdomain is enabled or disabled. | |
216 | * Intended to be called at init time from omap*_clk_init(). No | |
217 | * return value. | |
218 | */ | |
219 | void __init omap2_clk_disable_clkdm_control(void) | |
220 | { | |
221 | clkdm_control = false; | |
222 | } | |
223 | ||
543d9378 | 224 | /** |
72350b29 PW |
225 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
226 | * @clk: struct clk * to find the companion clock of | |
227 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
228 | * @other_bit: u8 ** to return the companion clock bit shift in | |
229 | * | |
230 | * Note: We don't need special code here for INVERT_ENABLE for the | |
231 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
232 | * CM_CLKEN_PLL | |
543d9378 | 233 | * |
72350b29 PW |
234 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
235 | * just a matter of XORing the bits. | |
236 | * | |
237 | * Some clocks don't have companion clocks. For example, modules with | |
238 | * only an interface clock (such as MAILBOXES) don't have a companion | |
239 | * clock. Right now, this code relies on the hardware exporting a bit | |
240 | * in the correct companion register that indicates that the | |
241 | * nonexistent 'companion clock' is active. Future patches will | |
242 | * associate this type of code with per-module data structures to | |
243 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 244 | */ |
32cc0021 | 245 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
32cc0021 | 246 | void __iomem **other_reg, u8 *other_bit) |
543d9378 | 247 | { |
72350b29 | 248 | u32 r; |
543d9378 PW |
249 | |
250 | /* | |
72350b29 PW |
251 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
252 | * it's just a matter of XORing the bits. | |
543d9378 | 253 | */ |
72350b29 | 254 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 255 | |
72350b29 PW |
256 | *other_reg = (__force void __iomem *)r; |
257 | *other_bit = clk->enable_bit; | |
258 | } | |
543d9378 | 259 | |
72350b29 PW |
260 | /** |
261 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
262 | * @clk: struct clk * to find IDLEST info for | |
263 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
264 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
265 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
266 | * |
267 | * Return the CM_IDLEST register address and bit shift corresponding | |
268 | * to the module that "owns" this clock. This default code assumes | |
269 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
270 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
271 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
272 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 273 | */ |
32cc0021 | 274 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, |
32cc0021 | 275 | void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 276 | { |
72350b29 | 277 | u32 r; |
543d9378 | 278 | |
72350b29 PW |
279 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
280 | *idlest_reg = (__force void __iomem *)r; | |
281 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
282 | |
283 | /* | |
284 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
285 | * 34xx reverses this, just to keep us on our toes | |
286 | * AM35xx uses both, depending on the module. | |
287 | */ | |
066edb2d | 288 | *idlest_val = ti_clk_features.cm_idlest_val; |
72350b29 | 289 | } |
543d9378 | 290 | |
32cc0021 MT |
291 | /** |
292 | * omap2_dflt_clk_enable - enable a clock in the hardware | |
293 | * @hw: struct clk_hw * of the clock to enable | |
294 | * | |
295 | * Enable the clock @hw in the hardware. We first call into the OMAP | |
296 | * clockdomain code to "enable" the corresponding clockdomain if this | |
297 | * is the first enabled user of the clockdomain. Then program the | |
298 | * hardware to enable the clock. Then wait for the IP block that uses | |
299 | * this clock to leave idle (if applicable). Returns the error value | |
300 | * from clkdm_clk_enable() if it terminated with an error, or -EINVAL | |
301 | * if @hw has a null clock enable_reg, or zero upon success. | |
302 | */ | |
303 | int omap2_dflt_clk_enable(struct clk_hw *hw) | |
304 | { | |
305 | struct clk_hw_omap *clk; | |
306 | u32 v; | |
307 | int ret = 0; | |
308 | ||
309 | clk = to_clk_hw_omap(hw); | |
310 | ||
311 | if (clkdm_control && clk->clkdm) { | |
312 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
313 | if (ret) { | |
314 | WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", | |
315 | __func__, __clk_get_name(hw->clk), | |
316 | clk->clkdm->name, ret); | |
317 | return ret; | |
318 | } | |
319 | } | |
320 | ||
321 | if (unlikely(clk->enable_reg == NULL)) { | |
322 | pr_err("%s: %s missing enable_reg\n", __func__, | |
323 | __clk_get_name(hw->clk)); | |
324 | ret = -EINVAL; | |
325 | goto err; | |
326 | } | |
327 | ||
328 | /* FIXME should not have INVERT_ENABLE bit here */ | |
519ab8b2 | 329 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
330 | if (clk->flags & INVERT_ENABLE) |
331 | v &= ~(1 << clk->enable_bit); | |
332 | else | |
333 | v |= (1 << clk->enable_bit); | |
519ab8b2 TK |
334 | omap2_clk_writel(v, clk, clk->enable_reg); |
335 | v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ | |
32cc0021 MT |
336 | |
337 | if (clk->ops && clk->ops->find_idlest) | |
338 | _omap2_module_wait_ready(clk); | |
339 | ||
340 | return 0; | |
341 | ||
342 | err: | |
343 | if (clkdm_control && clk->clkdm) | |
344 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | /** | |
349 | * omap2_dflt_clk_disable - disable a clock in the hardware | |
350 | * @hw: struct clk_hw * of the clock to disable | |
351 | * | |
352 | * Disable the clock @hw in the hardware, and call into the OMAP | |
353 | * clockdomain code to "disable" the corresponding clockdomain if all | |
354 | * clocks/hwmods in that clockdomain are now disabled. No return | |
355 | * value. | |
356 | */ | |
357 | void omap2_dflt_clk_disable(struct clk_hw *hw) | |
358 | { | |
359 | struct clk_hw_omap *clk; | |
360 | u32 v; | |
361 | ||
362 | clk = to_clk_hw_omap(hw); | |
363 | if (!clk->enable_reg) { | |
364 | /* | |
365 | * 'independent' here refers to a clock which is not | |
366 | * controlled by its parent. | |
367 | */ | |
368 | pr_err("%s: independent clock %s has no enable_reg\n", | |
369 | __func__, __clk_get_name(hw->clk)); | |
370 | return; | |
371 | } | |
372 | ||
519ab8b2 | 373 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
374 | if (clk->flags & INVERT_ENABLE) |
375 | v |= (1 << clk->enable_bit); | |
376 | else | |
377 | v &= ~(1 << clk->enable_bit); | |
519ab8b2 | 378 | omap2_clk_writel(v, clk, clk->enable_reg); |
32cc0021 MT |
379 | /* No OCP barrier needed here since it is a disable operation */ |
380 | ||
381 | if (clkdm_control && clk->clkdm) | |
382 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
383 | } | |
384 | ||
385 | /** | |
386 | * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw | |
387 | * @hw: struct clk_hw * of the clock being enabled | |
388 | * | |
389 | * Increment the usecount of the clockdomain of the clock pointed to | |
390 | * by @hw; if the usecount is 1, the clockdomain will be "enabled." | |
391 | * Only needed for clocks that don't use omap2_dflt_clk_enable() as | |
392 | * their enable function pointer. Passes along the return value of | |
393 | * clkdm_clk_enable(), -EINVAL if @hw is not associated with a | |
394 | * clockdomain, or 0 if clock framework-based clockdomain control is | |
395 | * not implemented. | |
396 | */ | |
397 | int omap2_clkops_enable_clkdm(struct clk_hw *hw) | |
398 | { | |
399 | struct clk_hw_omap *clk; | |
400 | int ret = 0; | |
401 | ||
402 | clk = to_clk_hw_omap(hw); | |
403 | ||
404 | if (unlikely(!clk->clkdm)) { | |
405 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
406 | __clk_get_name(hw->clk)); | |
407 | return -EINVAL; | |
408 | } | |
409 | ||
410 | if (unlikely(clk->enable_reg)) | |
411 | pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, | |
412 | __clk_get_name(hw->clk)); | |
413 | ||
414 | if (!clkdm_control) { | |
415 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
416 | __func__, __clk_get_name(hw->clk)); | |
417 | return 0; | |
418 | } | |
419 | ||
420 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
421 | WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", | |
422 | __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); | |
423 | ||
424 | return ret; | |
425 | } | |
426 | ||
427 | /** | |
428 | * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw | |
429 | * @hw: struct clk_hw * of the clock being disabled | |
430 | * | |
431 | * Decrement the usecount of the clockdomain of the clock pointed to | |
432 | * by @hw; if the usecount is 0, the clockdomain will be "disabled." | |
433 | * Only needed for clocks that don't use omap2_dflt_clk_disable() as their | |
434 | * disable function pointer. No return value. | |
435 | */ | |
436 | void omap2_clkops_disable_clkdm(struct clk_hw *hw) | |
437 | { | |
438 | struct clk_hw_omap *clk; | |
439 | ||
440 | clk = to_clk_hw_omap(hw); | |
441 | ||
442 | if (unlikely(!clk->clkdm)) { | |
443 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
444 | __clk_get_name(hw->clk)); | |
445 | return; | |
446 | } | |
447 | ||
448 | if (unlikely(clk->enable_reg)) | |
449 | pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, | |
450 | __clk_get_name(hw->clk)); | |
451 | ||
452 | if (!clkdm_control) { | |
453 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
454 | __func__, __clk_get_name(hw->clk)); | |
455 | return; | |
456 | } | |
457 | ||
458 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
459 | } | |
460 | ||
461 | /** | |
462 | * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? | |
463 | * @hw: struct clk_hw * to check | |
464 | * | |
465 | * Return 1 if the clock represented by @hw is enabled in the | |
466 | * hardware, or 0 otherwise. Intended for use in the struct | |
467 | * clk_ops.is_enabled function pointer. | |
468 | */ | |
469 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw) | |
470 | { | |
471 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
472 | u32 v; | |
473 | ||
519ab8b2 | 474 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
475 | |
476 | if (clk->flags & INVERT_ENABLE) | |
477 | v ^= BIT(clk->enable_bit); | |
478 | ||
479 | v &= BIT(clk->enable_bit); | |
480 | ||
481 | return v ? 1 : 0; | |
482 | } | |
483 | ||
484 | static int __initdata mpurate; | |
485 | ||
486 | /* | |
487 | * By default we use the rate set by the bootloader. | |
488 | * You can override this with mpurate= cmdline option. | |
489 | */ | |
490 | static int __init omap_clk_setup(char *str) | |
491 | { | |
492 | get_option(&str, &mpurate); | |
493 | ||
494 | if (!mpurate) | |
495 | return 1; | |
496 | ||
497 | if (mpurate < 1000) | |
498 | mpurate *= 1000000; | |
499 | ||
500 | return 1; | |
501 | } | |
502 | __setup("mpurate=", omap_clk_setup); | |
503 | ||
23fb8ba3 RN |
504 | /** |
505 | * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock | |
506 | * @clk: struct clk * to initialize | |
507 | * | |
508 | * Add an OMAP clock @clk to the internal list of OMAP clocks. Used | |
509 | * temporarily for autoidle handling, until this support can be | |
510 | * integrated into the common clock framework code in some way. No | |
511 | * return value. | |
512 | */ | |
513 | void omap2_init_clk_hw_omap_clocks(struct clk *clk) | |
514 | { | |
515 | struct clk_hw_omap *c; | |
516 | ||
517 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
518 | return; | |
519 | ||
520 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
521 | list_add(&c->node, &clk_hw_omap_clocks); | |
522 | } | |
523 | ||
524 | /** | |
525 | * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that | |
526 | * support it | |
527 | * | |
528 | * Enable clock autoidle on all OMAP clocks that have allow_idle | |
529 | * function pointers associated with them. This function is intended | |
530 | * to be temporary until support for this is added to the common clock | |
531 | * code. Returns 0. | |
532 | */ | |
533 | int omap2_clk_enable_autoidle_all(void) | |
534 | { | |
535 | struct clk_hw_omap *c; | |
536 | ||
537 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
538 | if (c->ops && c->ops->allow_idle) | |
539 | c->ops->allow_idle(c); | |
b1a07b47 TK |
540 | |
541 | of_ti_clk_allow_autoidle_all(); | |
542 | ||
23fb8ba3 RN |
543 | return 0; |
544 | } | |
545 | ||
546 | /** | |
547 | * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that | |
548 | * support it | |
549 | * | |
550 | * Disable clock autoidle on all OMAP clocks that have allow_idle | |
551 | * function pointers associated with them. This function is intended | |
552 | * to be temporary until support for this is added to the common clock | |
553 | * code. Returns 0. | |
554 | */ | |
555 | int omap2_clk_disable_autoidle_all(void) | |
556 | { | |
557 | struct clk_hw_omap *c; | |
558 | ||
559 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
560 | if (c->ops && c->ops->deny_idle) | |
561 | c->ops->deny_idle(c); | |
b1a07b47 TK |
562 | |
563 | of_ti_clk_deny_autoidle_all(); | |
564 | ||
23fb8ba3 RN |
565 | return 0; |
566 | } | |
567 | ||
818b40e5 TK |
568 | /** |
569 | * omap2_clk_deny_idle - disable autoidle on an OMAP clock | |
570 | * @clk: struct clk * to disable autoidle for | |
571 | * | |
572 | * Disable autoidle on an OMAP clock. | |
573 | */ | |
574 | int omap2_clk_deny_idle(struct clk *clk) | |
575 | { | |
576 | struct clk_hw_omap *c; | |
577 | ||
578 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
579 | return -EINVAL; | |
580 | ||
581 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
582 | if (c->ops && c->ops->deny_idle) | |
583 | c->ops->deny_idle(c); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | /** | |
588 | * omap2_clk_allow_idle - enable autoidle on an OMAP clock | |
589 | * @clk: struct clk * to enable autoidle for | |
590 | * | |
591 | * Enable autoidle on an OMAP clock. | |
592 | */ | |
593 | int omap2_clk_allow_idle(struct clk *clk) | |
594 | { | |
595 | struct clk_hw_omap *c; | |
596 | ||
597 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
598 | return -EINVAL; | |
599 | ||
600 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
601 | if (c->ops && c->ops->allow_idle) | |
602 | c->ops->allow_idle(c); | |
603 | return 0; | |
604 | } | |
605 | ||
8577413c RN |
606 | /** |
607 | * omap2_clk_enable_init_clocks - prepare & enable a list of clocks | |
608 | * @clk_names: ptr to an array of strings of clock names to enable | |
609 | * @num_clocks: number of clock names in @clk_names | |
610 | * | |
611 | * Prepare and enable a list of clocks, named by @clk_names. No | |
612 | * return value. XXX Deprecated; only needed until these clocks are | |
613 | * properly claimed and enabled by the drivers or core code that uses | |
614 | * them. XXX What code disables & calls clk_put on these clocks? | |
615 | */ | |
616 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) | |
617 | { | |
618 | struct clk *init_clk; | |
619 | int i; | |
620 | ||
621 | for (i = 0; i < num_clocks; i++) { | |
622 | init_clk = clk_get(NULL, clk_names[i]); | |
339d095a TL |
623 | if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", |
624 | clk_names[i])) | |
625 | continue; | |
8577413c RN |
626 | clk_prepare_enable(init_clk); |
627 | } | |
628 | } | |
629 | ||
32cc0021 MT |
630 | const struct clk_hw_omap_ops clkhwops_wait = { |
631 | .find_idlest = omap2_clk_dflt_find_idlest, | |
632 | .find_companion = omap2_clk_dflt_find_companion, | |
633 | }; | |
32cc0021 | 634 | |
78e52e02 K |
635 | /** |
636 | * omap_clocks_register - register an array of omap_clk | |
637 | * @ocs: pointer to an array of omap_clk to register | |
638 | */ | |
639 | void __init omap_clocks_register(struct omap_clk oclks[], int cnt) | |
640 | { | |
641 | struct omap_clk *c; | |
642 | ||
643 | for (c = oclks; c < oclks + cnt; c++) { | |
644 | clkdev_add(&c->lk); | |
645 | if (!__clk_init(NULL, c->lk.clk)) | |
646 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | |
647 | } | |
648 | } | |
649 | ||
4d30e82c PW |
650 | /** |
651 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
652 | * @mpurate_ck_name: clk name of the clock to change rate | |
653 | * | |
654 | * Change the ARM MPU clock rate to the rate specified on the command | |
655 | * line, if one was specified. @mpurate_ck_name should be | |
656 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
657 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
658 | * handled by the virt_prcm_set clock, but this should be handled by | |
659 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
660 | * code in the near future and should be removed from the clock code. | |
661 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
662 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
663 | * cannot be found, or 0 upon success. | |
664 | */ | |
665 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
666 | { | |
667 | struct clk *mpurate_ck; | |
668 | int r; | |
669 | ||
670 | if (!mpurate) | |
671 | return -EINVAL; | |
672 | ||
673 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
674 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
675 | return -ENOENT; | |
676 | ||
677 | r = clk_set_rate(mpurate_ck, mpurate); | |
c48cd659 | 678 | if (r < 0) { |
4d30e82c | 679 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
32cc0021 | 680 | mpurate_ck_name, mpurate, r); |
f6281f66 | 681 | clk_put(mpurate_ck); |
4d30e82c PW |
682 | return -EINVAL; |
683 | } | |
684 | ||
685 | calibrate_delay(); | |
4d30e82c PW |
686 | clk_put(mpurate_ck); |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | /** | |
692 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
693 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
694 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
695 | * @mpu_ck_name: clk name for the ARM MPU clock | |
696 | * | |
697 | * Prints a short message to the console with the HFCLKIN oscillator | |
698 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
699 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
700 | * to be handled by the OPP layer code in the near future and should be | |
701 | * removed from the clock code. No return value. | |
702 | */ | |
703 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
704 | const char *core_ck_name, | |
705 | const char *mpu_ck_name) | |
706 | { | |
707 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
708 | unsigned long hfclkin_rate; | |
709 | ||
710 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
711 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
712 | return; | |
713 | ||
714 | core_ck = clk_get(NULL, core_ck_name); | |
715 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
716 | return; | |
717 | ||
718 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
719 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
720 | return; | |
721 | ||
722 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
723 | ||
7852ec05 PW |
724 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
725 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), | |
4d30e82c PW |
726 | (clk_get_rate(core_ck) / 1000000), |
727 | (clk_get_rate(mpu_ck) / 1000000)); | |
728 | } | |
8111e010 TK |
729 | |
730 | /** | |
731 | * ti_clk_init_features - init clock features struct for the SoC | |
732 | * | |
733 | * Initializes the clock features struct based on the SoC type. | |
734 | */ | |
735 | void __init ti_clk_init_features(void) | |
736 | { | |
a24886e2 TK |
737 | /* Fint setup for DPLLs */ |
738 | if (cpu_is_omap3430()) { | |
739 | ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; | |
740 | ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; | |
741 | ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; | |
742 | ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; | |
743 | } else { | |
744 | ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; | |
745 | ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; | |
746 | } | |
512d91cb TK |
747 | |
748 | /* Bypass value setup for DPLLs */ | |
749 | if (cpu_is_omap24xx()) { | |
750 | ti_clk_features.dpll_bypass_vals |= | |
751 | (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | | |
752 | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); | |
753 | } else if (cpu_is_omap34xx()) { | |
754 | ti_clk_features.dpll_bypass_vals |= | |
755 | (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | | |
756 | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); | |
757 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || | |
758 | soc_is_omap54xx() || soc_is_dra7xx()) { | |
759 | ti_clk_features.dpll_bypass_vals |= | |
760 | (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | | |
761 | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | | |
762 | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); | |
763 | } | |
2337c5b5 TK |
764 | |
765 | /* Jitter correction only available on OMAP343X */ | |
766 | if (cpu_is_omap343x()) | |
767 | ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; | |
066edb2d TK |
768 | |
769 | /* Idlest value for interface clocks. | |
770 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
771 | * 34xx reverses this, just to keep us on our toes | |
772 | * AM35xx uses both, depending on the module. | |
773 | */ | |
774 | if (cpu_is_omap24xx()) | |
775 | ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
776 | else if (cpu_is_omap34xx()) | |
777 | ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
f0d2f68a TK |
778 | |
779 | /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ | |
780 | if (omap_rev() == OMAP3430_REV_ES1_0) | |
781 | ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; | |
8111e010 | 782 | } |