Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
1fe9be82 | 18 | #include <linux/export.h> |
543d9378 PW |
19 | #include <linux/list.h> |
20 | #include <linux/errno.h> | |
4d30e82c PW |
21 | #include <linux/err.h> |
22 | #include <linux/delay.h> | |
32cc0021 | 23 | #include <linux/clk-provider.h> |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
5e7c58dc | 26 | #include <asm/cpu.h> |
dbc04161 | 27 | |
dbc04161 TL |
28 | #include <trace/events/power.h> |
29 | ||
30 | #include "soc.h" | |
31 | #include "clockdomain.h" | |
543d9378 | 32 | #include "clock.h" |
c4ceedcb | 33 | #include "cm.h" |
ff4ae5d9 PW |
34 | #include "cm2xxx.h" |
35 | #include "cm3xxx.h" | |
543d9378 PW |
36 | #include "cm-regbits-24xx.h" |
37 | #include "cm-regbits-34xx.h" | |
c4ceedcb PW |
38 | #include "common.h" |
39 | ||
40 | /* | |
41 | * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait | |
42 | * for a module to indicate that it is no longer in idle | |
43 | */ | |
44 | #define MAX_MODULE_ENABLE_WAIT 100000 | |
543d9378 | 45 | |
99541195 | 46 | u16 cpu_mask; |
543d9378 | 47 | |
8111e010 TK |
48 | /* |
49 | * Clock features setup. Used instead of CPU type checks. | |
50 | */ | |
51 | struct ti_clk_features ti_clk_features; | |
52 | ||
a24886e2 TK |
53 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ |
54 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 | |
55 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 | |
56 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 | |
57 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 | |
58 | ||
59 | /* | |
60 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. | |
61 | * From device data manual section 4.3 "DPLL and DLL Specifications". | |
62 | */ | |
63 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 | |
64 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 | |
65 | ||
12706c54 PW |
66 | /* |
67 | * clkdm_control: if true, then when a clock is enabled in the | |
68 | * hardware, its clockdomain will first be enabled; and when a clock | |
69 | * is disabled in the hardware, its clockdomain will be disabled | |
70 | * afterwards. | |
71 | */ | |
72 | static bool clkdm_control = true; | |
73 | ||
23fb8ba3 | 74 | static LIST_HEAD(clk_hw_omap_clocks); |
3ada6b10 TK |
75 | void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; |
76 | ||
77 | void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) | |
78 | { | |
79 | if (clk->flags & MEMMAP_ADDRESSING) { | |
80 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
81 | writel_relaxed(val, clk_memmaps[r->index] + r->offset); | |
82 | } else { | |
83 | writel_relaxed(val, reg); | |
84 | } | |
85 | } | |
86 | ||
87 | u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) | |
88 | { | |
89 | u32 val; | |
90 | ||
91 | if (clk->flags & MEMMAP_ADDRESSING) { | |
92 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
93 | val = readl_relaxed(clk_memmaps[r->index] + r->offset); | |
94 | } else { | |
95 | val = readl_relaxed(reg); | |
96 | } | |
97 | ||
98 | return val; | |
99 | } | |
32cc0021 | 100 | |
30962d9d PW |
101 | /* |
102 | * OMAP2+ specific clock functions | |
103 | */ | |
543d9378 | 104 | |
4b1f76ed PW |
105 | /* Private functions */ |
106 | ||
c4ceedcb PW |
107 | |
108 | /** | |
109 | * _wait_idlest_generic - wait for a module to leave the idle state | |
519ab8b2 | 110 | * @clk: module clock to wait for (needed for register offsets) |
c4ceedcb PW |
111 | * @reg: virtual address of module IDLEST register |
112 | * @mask: value to mask against to determine if the module is active | |
113 | * @idlest: idle state indicator (0 or 1) for the clock | |
114 | * @name: name of the clock (for printk) | |
115 | * | |
116 | * Wait for a module to leave idle, where its idle-status register is | |
117 | * not inside the CM module. Returns 1 if the module left idle | |
118 | * promptly, or 0 if the module did not leave idle before the timeout | |
119 | * elapsed. XXX Deprecated - should be moved into drivers for the | |
120 | * individual IP block that the IDLEST register exists in. | |
121 | */ | |
519ab8b2 TK |
122 | static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, |
123 | u32 mask, u8 idlest, const char *name) | |
c4ceedcb PW |
124 | { |
125 | int i = 0, ena = 0; | |
126 | ||
127 | ena = (idlest) ? 0 : mask; | |
128 | ||
519ab8b2 | 129 | omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), |
c4ceedcb PW |
130 | MAX_MODULE_ENABLE_WAIT, i); |
131 | ||
132 | if (i < MAX_MODULE_ENABLE_WAIT) | |
133 | pr_debug("omap clock: module associated with clock %s ready after %d loops\n", | |
134 | name, i); | |
135 | else | |
136 | pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", | |
137 | name, MAX_MODULE_ENABLE_WAIT); | |
138 | ||
139 | return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; | |
140 | }; | |
141 | ||
4b1f76ed PW |
142 | /** |
143 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
144 | * @clk: struct clk * belonging to the module | |
145 | * | |
146 | * If the necessary clocks for the OMAP hardware IP block that | |
147 | * corresponds to clock @clk are enabled, then wait for the module to | |
148 | * indicate readiness (i.e., to leave IDLE). This code does not | |
149 | * belong in the clock code and will be moved in the medium term to | |
150 | * module-dependent code. No return value. | |
151 | */ | |
32cc0021 | 152 | static void _omap2_module_wait_ready(struct clk_hw_omap *clk) |
4b1f76ed PW |
153 | { |
154 | void __iomem *companion_reg, *idlest_reg; | |
c4ceedcb PW |
155 | u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; |
156 | s16 prcm_mod; | |
157 | int r; | |
4b1f76ed PW |
158 | |
159 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
160 | if (clk->ops->find_companion) { | |
161 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
519ab8b2 | 162 | if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) |
4b1f76ed PW |
163 | return; |
164 | } | |
165 | ||
419cc97d | 166 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
c4ceedcb PW |
167 | r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); |
168 | if (r) { | |
169 | /* IDLEST register not in the CM module */ | |
519ab8b2 TK |
170 | _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), |
171 | idlest_val, __clk_get_name(clk->hw.clk)); | |
c4ceedcb | 172 | } else { |
021b6ff0 TK |
173 | omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id, |
174 | idlest_bit); | |
c4ceedcb | 175 | }; |
4b1f76ed PW |
176 | } |
177 | ||
4b1f76ed PW |
178 | /* Public functions */ |
179 | ||
333943ba PW |
180 | /** |
181 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
182 | * @clk: OMAP clock struct ptr to use | |
183 | * | |
184 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
185 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
186 | * called during clk_register(). No return value. | |
187 | */ | |
32cc0021 MT |
188 | void omap2_init_clk_clkdm(struct clk_hw *hw) |
189 | { | |
190 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
333943ba | 191 | struct clockdomain *clkdm; |
5dcc3b97 | 192 | const char *clk_name; |
333943ba PW |
193 | |
194 | if (!clk->clkdm_name) | |
195 | return; | |
196 | ||
32cc0021 | 197 | clk_name = __clk_get_name(hw->clk); |
5dcc3b97 | 198 | |
333943ba PW |
199 | clkdm = clkdm_lookup(clk->clkdm_name); |
200 | if (clkdm) { | |
201 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
5dcc3b97 | 202 | clk_name, clk->clkdm_name); |
333943ba PW |
203 | clk->clkdm = clkdm; |
204 | } else { | |
7852ec05 | 205 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
5dcc3b97 | 206 | clk_name, clk->clkdm_name); |
333943ba PW |
207 | } |
208 | } | |
209 | ||
12706c54 PW |
210 | /** |
211 | * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable | |
212 | * | |
213 | * Prevent the OMAP clock code from calling into the clockdomain code | |
214 | * when a hardware clock in that clockdomain is enabled or disabled. | |
215 | * Intended to be called at init time from omap*_clk_init(). No | |
216 | * return value. | |
217 | */ | |
218 | void __init omap2_clk_disable_clkdm_control(void) | |
219 | { | |
220 | clkdm_control = false; | |
221 | } | |
222 | ||
543d9378 | 223 | /** |
72350b29 PW |
224 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
225 | * @clk: struct clk * to find the companion clock of | |
226 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
227 | * @other_bit: u8 ** to return the companion clock bit shift in | |
228 | * | |
229 | * Note: We don't need special code here for INVERT_ENABLE for the | |
230 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
231 | * CM_CLKEN_PLL | |
543d9378 | 232 | * |
72350b29 PW |
233 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
234 | * just a matter of XORing the bits. | |
235 | * | |
236 | * Some clocks don't have companion clocks. For example, modules with | |
237 | * only an interface clock (such as MAILBOXES) don't have a companion | |
238 | * clock. Right now, this code relies on the hardware exporting a bit | |
239 | * in the correct companion register that indicates that the | |
240 | * nonexistent 'companion clock' is active. Future patches will | |
241 | * associate this type of code with per-module data structures to | |
242 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 243 | */ |
32cc0021 | 244 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
32cc0021 | 245 | void __iomem **other_reg, u8 *other_bit) |
543d9378 | 246 | { |
72350b29 | 247 | u32 r; |
543d9378 PW |
248 | |
249 | /* | |
72350b29 PW |
250 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
251 | * it's just a matter of XORing the bits. | |
543d9378 | 252 | */ |
72350b29 | 253 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 254 | |
72350b29 PW |
255 | *other_reg = (__force void __iomem *)r; |
256 | *other_bit = clk->enable_bit; | |
257 | } | |
543d9378 | 258 | |
72350b29 PW |
259 | /** |
260 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
261 | * @clk: struct clk * to find IDLEST info for | |
262 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
263 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
264 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
265 | * |
266 | * Return the CM_IDLEST register address and bit shift corresponding | |
267 | * to the module that "owns" this clock. This default code assumes | |
268 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
269 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
270 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
271 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 272 | */ |
32cc0021 | 273 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, |
32cc0021 | 274 | void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 275 | { |
72350b29 | 276 | u32 r; |
543d9378 | 277 | |
72350b29 PW |
278 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
279 | *idlest_reg = (__force void __iomem *)r; | |
280 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
281 | |
282 | /* | |
283 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
284 | * 34xx reverses this, just to keep us on our toes | |
285 | * AM35xx uses both, depending on the module. | |
286 | */ | |
066edb2d | 287 | *idlest_val = ti_clk_features.cm_idlest_val; |
72350b29 | 288 | } |
543d9378 | 289 | |
32cc0021 MT |
290 | /** |
291 | * omap2_dflt_clk_enable - enable a clock in the hardware | |
292 | * @hw: struct clk_hw * of the clock to enable | |
293 | * | |
294 | * Enable the clock @hw in the hardware. We first call into the OMAP | |
295 | * clockdomain code to "enable" the corresponding clockdomain if this | |
296 | * is the first enabled user of the clockdomain. Then program the | |
297 | * hardware to enable the clock. Then wait for the IP block that uses | |
298 | * this clock to leave idle (if applicable). Returns the error value | |
299 | * from clkdm_clk_enable() if it terminated with an error, or -EINVAL | |
300 | * if @hw has a null clock enable_reg, or zero upon success. | |
301 | */ | |
302 | int omap2_dflt_clk_enable(struct clk_hw *hw) | |
303 | { | |
304 | struct clk_hw_omap *clk; | |
305 | u32 v; | |
306 | int ret = 0; | |
307 | ||
308 | clk = to_clk_hw_omap(hw); | |
309 | ||
310 | if (clkdm_control && clk->clkdm) { | |
311 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
312 | if (ret) { | |
313 | WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", | |
314 | __func__, __clk_get_name(hw->clk), | |
315 | clk->clkdm->name, ret); | |
316 | return ret; | |
317 | } | |
318 | } | |
319 | ||
320 | if (unlikely(clk->enable_reg == NULL)) { | |
321 | pr_err("%s: %s missing enable_reg\n", __func__, | |
322 | __clk_get_name(hw->clk)); | |
323 | ret = -EINVAL; | |
324 | goto err; | |
325 | } | |
326 | ||
327 | /* FIXME should not have INVERT_ENABLE bit here */ | |
519ab8b2 | 328 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
329 | if (clk->flags & INVERT_ENABLE) |
330 | v &= ~(1 << clk->enable_bit); | |
331 | else | |
332 | v |= (1 << clk->enable_bit); | |
519ab8b2 TK |
333 | omap2_clk_writel(v, clk, clk->enable_reg); |
334 | v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ | |
32cc0021 MT |
335 | |
336 | if (clk->ops && clk->ops->find_idlest) | |
337 | _omap2_module_wait_ready(clk); | |
338 | ||
339 | return 0; | |
340 | ||
341 | err: | |
342 | if (clkdm_control && clk->clkdm) | |
343 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
344 | return ret; | |
345 | } | |
346 | ||
347 | /** | |
348 | * omap2_dflt_clk_disable - disable a clock in the hardware | |
349 | * @hw: struct clk_hw * of the clock to disable | |
350 | * | |
351 | * Disable the clock @hw in the hardware, and call into the OMAP | |
352 | * clockdomain code to "disable" the corresponding clockdomain if all | |
353 | * clocks/hwmods in that clockdomain are now disabled. No return | |
354 | * value. | |
355 | */ | |
356 | void omap2_dflt_clk_disable(struct clk_hw *hw) | |
357 | { | |
358 | struct clk_hw_omap *clk; | |
359 | u32 v; | |
360 | ||
361 | clk = to_clk_hw_omap(hw); | |
362 | if (!clk->enable_reg) { | |
363 | /* | |
364 | * 'independent' here refers to a clock which is not | |
365 | * controlled by its parent. | |
366 | */ | |
367 | pr_err("%s: independent clock %s has no enable_reg\n", | |
368 | __func__, __clk_get_name(hw->clk)); | |
369 | return; | |
370 | } | |
371 | ||
519ab8b2 | 372 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
373 | if (clk->flags & INVERT_ENABLE) |
374 | v |= (1 << clk->enable_bit); | |
375 | else | |
376 | v &= ~(1 << clk->enable_bit); | |
519ab8b2 | 377 | omap2_clk_writel(v, clk, clk->enable_reg); |
32cc0021 MT |
378 | /* No OCP barrier needed here since it is a disable operation */ |
379 | ||
380 | if (clkdm_control && clk->clkdm) | |
381 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
382 | } | |
383 | ||
384 | /** | |
385 | * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw | |
386 | * @hw: struct clk_hw * of the clock being enabled | |
387 | * | |
388 | * Increment the usecount of the clockdomain of the clock pointed to | |
389 | * by @hw; if the usecount is 1, the clockdomain will be "enabled." | |
390 | * Only needed for clocks that don't use omap2_dflt_clk_enable() as | |
391 | * their enable function pointer. Passes along the return value of | |
392 | * clkdm_clk_enable(), -EINVAL if @hw is not associated with a | |
393 | * clockdomain, or 0 if clock framework-based clockdomain control is | |
394 | * not implemented. | |
395 | */ | |
396 | int omap2_clkops_enable_clkdm(struct clk_hw *hw) | |
397 | { | |
398 | struct clk_hw_omap *clk; | |
399 | int ret = 0; | |
400 | ||
401 | clk = to_clk_hw_omap(hw); | |
402 | ||
403 | if (unlikely(!clk->clkdm)) { | |
404 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
405 | __clk_get_name(hw->clk)); | |
406 | return -EINVAL; | |
407 | } | |
408 | ||
409 | if (unlikely(clk->enable_reg)) | |
410 | pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, | |
411 | __clk_get_name(hw->clk)); | |
412 | ||
413 | if (!clkdm_control) { | |
414 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
415 | __func__, __clk_get_name(hw->clk)); | |
416 | return 0; | |
417 | } | |
418 | ||
419 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
420 | WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", | |
421 | __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); | |
422 | ||
423 | return ret; | |
424 | } | |
425 | ||
426 | /** | |
427 | * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw | |
428 | * @hw: struct clk_hw * of the clock being disabled | |
429 | * | |
430 | * Decrement the usecount of the clockdomain of the clock pointed to | |
431 | * by @hw; if the usecount is 0, the clockdomain will be "disabled." | |
432 | * Only needed for clocks that don't use omap2_dflt_clk_disable() as their | |
433 | * disable function pointer. No return value. | |
434 | */ | |
435 | void omap2_clkops_disable_clkdm(struct clk_hw *hw) | |
436 | { | |
437 | struct clk_hw_omap *clk; | |
438 | ||
439 | clk = to_clk_hw_omap(hw); | |
440 | ||
441 | if (unlikely(!clk->clkdm)) { | |
442 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
443 | __clk_get_name(hw->clk)); | |
444 | return; | |
445 | } | |
446 | ||
447 | if (unlikely(clk->enable_reg)) | |
448 | pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, | |
449 | __clk_get_name(hw->clk)); | |
450 | ||
451 | if (!clkdm_control) { | |
452 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
453 | __func__, __clk_get_name(hw->clk)); | |
454 | return; | |
455 | } | |
456 | ||
457 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
458 | } | |
459 | ||
460 | /** | |
461 | * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? | |
462 | * @hw: struct clk_hw * to check | |
463 | * | |
464 | * Return 1 if the clock represented by @hw is enabled in the | |
465 | * hardware, or 0 otherwise. Intended for use in the struct | |
466 | * clk_ops.is_enabled function pointer. | |
467 | */ | |
468 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw) | |
469 | { | |
470 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
471 | u32 v; | |
472 | ||
519ab8b2 | 473 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
474 | |
475 | if (clk->flags & INVERT_ENABLE) | |
476 | v ^= BIT(clk->enable_bit); | |
477 | ||
478 | v &= BIT(clk->enable_bit); | |
479 | ||
480 | return v ? 1 : 0; | |
481 | } | |
482 | ||
483 | static int __initdata mpurate; | |
484 | ||
485 | /* | |
486 | * By default we use the rate set by the bootloader. | |
487 | * You can override this with mpurate= cmdline option. | |
488 | */ | |
489 | static int __init omap_clk_setup(char *str) | |
490 | { | |
491 | get_option(&str, &mpurate); | |
492 | ||
493 | if (!mpurate) | |
494 | return 1; | |
495 | ||
496 | if (mpurate < 1000) | |
497 | mpurate *= 1000000; | |
498 | ||
499 | return 1; | |
500 | } | |
501 | __setup("mpurate=", omap_clk_setup); | |
502 | ||
23fb8ba3 RN |
503 | /** |
504 | * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock | |
505 | * @clk: struct clk * to initialize | |
506 | * | |
507 | * Add an OMAP clock @clk to the internal list of OMAP clocks. Used | |
508 | * temporarily for autoidle handling, until this support can be | |
509 | * integrated into the common clock framework code in some way. No | |
510 | * return value. | |
511 | */ | |
512 | void omap2_init_clk_hw_omap_clocks(struct clk *clk) | |
513 | { | |
514 | struct clk_hw_omap *c; | |
515 | ||
516 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
517 | return; | |
518 | ||
519 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
520 | list_add(&c->node, &clk_hw_omap_clocks); | |
521 | } | |
522 | ||
523 | /** | |
524 | * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that | |
525 | * support it | |
526 | * | |
527 | * Enable clock autoidle on all OMAP clocks that have allow_idle | |
528 | * function pointers associated with them. This function is intended | |
529 | * to be temporary until support for this is added to the common clock | |
530 | * code. Returns 0. | |
531 | */ | |
532 | int omap2_clk_enable_autoidle_all(void) | |
533 | { | |
534 | struct clk_hw_omap *c; | |
535 | ||
536 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
537 | if (c->ops && c->ops->allow_idle) | |
538 | c->ops->allow_idle(c); | |
b1a07b47 TK |
539 | |
540 | of_ti_clk_allow_autoidle_all(); | |
541 | ||
23fb8ba3 RN |
542 | return 0; |
543 | } | |
544 | ||
545 | /** | |
546 | * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that | |
547 | * support it | |
548 | * | |
549 | * Disable clock autoidle on all OMAP clocks that have allow_idle | |
550 | * function pointers associated with them. This function is intended | |
551 | * to be temporary until support for this is added to the common clock | |
552 | * code. Returns 0. | |
553 | */ | |
554 | int omap2_clk_disable_autoidle_all(void) | |
555 | { | |
556 | struct clk_hw_omap *c; | |
557 | ||
558 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
559 | if (c->ops && c->ops->deny_idle) | |
560 | c->ops->deny_idle(c); | |
b1a07b47 TK |
561 | |
562 | of_ti_clk_deny_autoidle_all(); | |
563 | ||
23fb8ba3 RN |
564 | return 0; |
565 | } | |
566 | ||
818b40e5 TK |
567 | /** |
568 | * omap2_clk_deny_idle - disable autoidle on an OMAP clock | |
569 | * @clk: struct clk * to disable autoidle for | |
570 | * | |
571 | * Disable autoidle on an OMAP clock. | |
572 | */ | |
573 | int omap2_clk_deny_idle(struct clk *clk) | |
574 | { | |
575 | struct clk_hw_omap *c; | |
576 | ||
577 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
578 | return -EINVAL; | |
579 | ||
580 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
581 | if (c->ops && c->ops->deny_idle) | |
582 | c->ops->deny_idle(c); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | /** | |
587 | * omap2_clk_allow_idle - enable autoidle on an OMAP clock | |
588 | * @clk: struct clk * to enable autoidle for | |
589 | * | |
590 | * Enable autoidle on an OMAP clock. | |
591 | */ | |
592 | int omap2_clk_allow_idle(struct clk *clk) | |
593 | { | |
594 | struct clk_hw_omap *c; | |
595 | ||
596 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
597 | return -EINVAL; | |
598 | ||
599 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
600 | if (c->ops && c->ops->allow_idle) | |
601 | c->ops->allow_idle(c); | |
602 | return 0; | |
603 | } | |
604 | ||
8577413c RN |
605 | /** |
606 | * omap2_clk_enable_init_clocks - prepare & enable a list of clocks | |
607 | * @clk_names: ptr to an array of strings of clock names to enable | |
608 | * @num_clocks: number of clock names in @clk_names | |
609 | * | |
610 | * Prepare and enable a list of clocks, named by @clk_names. No | |
611 | * return value. XXX Deprecated; only needed until these clocks are | |
612 | * properly claimed and enabled by the drivers or core code that uses | |
613 | * them. XXX What code disables & calls clk_put on these clocks? | |
614 | */ | |
615 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) | |
616 | { | |
617 | struct clk *init_clk; | |
618 | int i; | |
619 | ||
620 | for (i = 0; i < num_clocks; i++) { | |
621 | init_clk = clk_get(NULL, clk_names[i]); | |
339d095a TL |
622 | if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", |
623 | clk_names[i])) | |
624 | continue; | |
8577413c RN |
625 | clk_prepare_enable(init_clk); |
626 | } | |
627 | } | |
628 | ||
32cc0021 MT |
629 | const struct clk_hw_omap_ops clkhwops_wait = { |
630 | .find_idlest = omap2_clk_dflt_find_idlest, | |
631 | .find_companion = omap2_clk_dflt_find_companion, | |
632 | }; | |
32cc0021 | 633 | |
4d30e82c PW |
634 | /** |
635 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
636 | * @mpurate_ck_name: clk name of the clock to change rate | |
637 | * | |
638 | * Change the ARM MPU clock rate to the rate specified on the command | |
639 | * line, if one was specified. @mpurate_ck_name should be | |
640 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
641 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
642 | * handled by the virt_prcm_set clock, but this should be handled by | |
643 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
644 | * code in the near future and should be removed from the clock code. | |
645 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
646 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
647 | * cannot be found, or 0 upon success. | |
648 | */ | |
649 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
650 | { | |
651 | struct clk *mpurate_ck; | |
652 | int r; | |
653 | ||
654 | if (!mpurate) | |
655 | return -EINVAL; | |
656 | ||
657 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
658 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
659 | return -ENOENT; | |
660 | ||
661 | r = clk_set_rate(mpurate_ck, mpurate); | |
c48cd659 | 662 | if (r < 0) { |
4d30e82c | 663 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
32cc0021 | 664 | mpurate_ck_name, mpurate, r); |
f6281f66 | 665 | clk_put(mpurate_ck); |
4d30e82c PW |
666 | return -EINVAL; |
667 | } | |
668 | ||
669 | calibrate_delay(); | |
4d30e82c PW |
670 | clk_put(mpurate_ck); |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | /** | |
676 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
677 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
678 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
679 | * @mpu_ck_name: clk name for the ARM MPU clock | |
680 | * | |
681 | * Prints a short message to the console with the HFCLKIN oscillator | |
682 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
683 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
684 | * to be handled by the OPP layer code in the near future and should be | |
685 | * removed from the clock code. No return value. | |
686 | */ | |
687 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
688 | const char *core_ck_name, | |
689 | const char *mpu_ck_name) | |
690 | { | |
691 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
692 | unsigned long hfclkin_rate; | |
693 | ||
694 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
695 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
696 | return; | |
697 | ||
698 | core_ck = clk_get(NULL, core_ck_name); | |
699 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
700 | return; | |
701 | ||
702 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
703 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
704 | return; | |
705 | ||
706 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
707 | ||
7852ec05 PW |
708 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
709 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), | |
4d30e82c PW |
710 | (clk_get_rate(core_ck) / 1000000), |
711 | (clk_get_rate(mpu_ck) / 1000000)); | |
712 | } | |
8111e010 TK |
713 | |
714 | /** | |
715 | * ti_clk_init_features - init clock features struct for the SoC | |
716 | * | |
717 | * Initializes the clock features struct based on the SoC type. | |
718 | */ | |
719 | void __init ti_clk_init_features(void) | |
720 | { | |
a24886e2 TK |
721 | /* Fint setup for DPLLs */ |
722 | if (cpu_is_omap3430()) { | |
723 | ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; | |
724 | ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; | |
725 | ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; | |
726 | ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; | |
727 | } else { | |
728 | ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; | |
729 | ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; | |
730 | } | |
512d91cb TK |
731 | |
732 | /* Bypass value setup for DPLLs */ | |
733 | if (cpu_is_omap24xx()) { | |
734 | ti_clk_features.dpll_bypass_vals |= | |
735 | (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | | |
736 | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); | |
737 | } else if (cpu_is_omap34xx()) { | |
738 | ti_clk_features.dpll_bypass_vals |= | |
739 | (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | | |
740 | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); | |
741 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || | |
742 | soc_is_omap54xx() || soc_is_dra7xx()) { | |
743 | ti_clk_features.dpll_bypass_vals |= | |
744 | (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | | |
745 | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | | |
746 | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); | |
747 | } | |
2337c5b5 TK |
748 | |
749 | /* Jitter correction only available on OMAP343X */ | |
750 | if (cpu_is_omap343x()) | |
751 | ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; | |
066edb2d TK |
752 | |
753 | /* Idlest value for interface clocks. | |
754 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
755 | * 34xx reverses this, just to keep us on our toes | |
756 | * AM35xx uses both, depending on the module. | |
757 | */ | |
758 | if (cpu_is_omap24xx()) | |
759 | ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
760 | else if (cpu_is_omap34xx()) | |
761 | ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
f0d2f68a TK |
762 | |
763 | /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ | |
764 | if (omap_rev() == OMAP3430_REV_ES1_0) | |
765 | ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; | |
8111e010 | 766 | } |