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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
543d9378 | 26 | |
a09e64fb | 27 | #include <mach/clock.h> |
333943ba | 28 | #include <mach/clockdomain.h> |
a09e64fb | 29 | #include <mach/cpu.h> |
72350b29 | 30 | #include <mach/prcm.h> |
543d9378 PW |
31 | #include <asm/div64.h> |
32 | ||
f8de9b2c | 33 | #include <mach/sdrc.h> |
543d9378 PW |
34 | #include "sdrc.h" |
35 | #include "clock.h" | |
36 | #include "prm.h" | |
37 | #include "prm-regbits-24xx.h" | |
38 | #include "cm.h" | |
39 | #include "cm-regbits-24xx.h" | |
40 | #include "cm-regbits-34xx.h" | |
41 | ||
88b8ba90 PW |
42 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
43 | #define DPLL_MIN_MULTIPLIER 1 | |
44 | #define DPLL_MIN_DIVIDER 1 | |
45 | ||
46 | /* Possible error results from _dpll_test_mult */ | |
85a5f78d | 47 | #define DPLL_MULT_UNDERFLOW -1 |
88b8ba90 PW |
48 | |
49 | /* | |
50 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | |
51 | * The higher the scale factor, the greater the risk of arithmetic overflow, | |
52 | * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR | |
53 | * must be a power of DPLL_SCALE_BASE. | |
54 | */ | |
55 | #define DPLL_SCALE_FACTOR 64 | |
56 | #define DPLL_SCALE_BASE 2 | |
57 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | |
58 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | |
59 | ||
95f538ac PW |
60 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ |
61 | #define DPLL_FINT_BAND1_MIN 750000 | |
62 | #define DPLL_FINT_BAND1_MAX 2100000 | |
63 | #define DPLL_FINT_BAND2_MIN 7500000 | |
64 | #define DPLL_FINT_BAND2_MAX 21000000 | |
65 | ||
66 | /* _dpll_test_fint() return codes */ | |
67 | #define DPLL_FINT_UNDERFLOW -1 | |
68 | #define DPLL_FINT_INVALID -2 | |
69 | ||
543d9378 PW |
70 | u8 cpu_mask; |
71 | ||
72 | /*------------------------------------------------------------------------- | |
333943ba | 73 | * OMAP2/3 specific clock functions |
543d9378 PW |
74 | *-------------------------------------------------------------------------*/ |
75 | ||
439764cc PW |
76 | /** |
77 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | |
78 | * @clk: struct clk * | |
79 | * | |
80 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | |
81 | * don't take effect until the VALID_CONFIG bit is written, write the | |
82 | * VALID_CONFIG bit and wait for the write to complete. No return value. | |
83 | */ | |
84 | static void _omap2xxx_clk_commit(struct clk *clk) | |
85 | { | |
86 | if (!cpu_is_omap24xx()) | |
87 | return; | |
88 | ||
89 | if (!(clk->flags & DELAYED_APP)) | |
90 | return; | |
91 | ||
92 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | |
8e3bd351 | 93 | OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc | 94 | /* OCP barrier */ |
8e3bd351 | 95 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc PW |
96 | } |
97 | ||
95f538ac PW |
98 | /* |
99 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | |
100 | * @clk: DPLL struct clk to test | |
101 | * @n: divider value (N) to test | |
102 | * | |
103 | * Tests whether a particular divider @n will result in a valid DPLL | |
104 | * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter | |
105 | * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate | |
106 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | |
107 | * should skip to the next iteration (again assuming N is increasing). | |
108 | */ | |
109 | static int _dpll_test_fint(struct clk *clk, u8 n) | |
110 | { | |
111 | struct dpll_data *dd; | |
112 | long fint; | |
113 | int ret = 0; | |
114 | ||
115 | dd = clk->dpll_data; | |
116 | ||
117 | /* DPLL divider must result in a valid jitter correction val */ | |
118 | fint = clk->parent->rate / (n + 1); | |
119 | if (fint < DPLL_FINT_BAND1_MIN) { | |
120 | ||
121 | pr_debug("rejecting n=%d due to Fint failure, " | |
122 | "lowering max_divider\n", n); | |
123 | dd->max_divider = n; | |
124 | ret = DPLL_FINT_UNDERFLOW; | |
125 | ||
126 | } else if (fint > DPLL_FINT_BAND1_MAX && | |
127 | fint < DPLL_FINT_BAND2_MIN) { | |
128 | ||
129 | pr_debug("rejecting n=%d due to Fint failure\n", n); | |
130 | ret = DPLL_FINT_INVALID; | |
131 | ||
132 | } else if (fint > DPLL_FINT_BAND2_MAX) { | |
133 | ||
134 | pr_debug("rejecting n=%d due to Fint failure, " | |
135 | "boosting min_divider\n", n); | |
136 | dd->min_divider = n; | |
137 | ret = DPLL_FINT_INVALID; | |
138 | ||
139 | } | |
140 | ||
141 | return ret; | |
142 | } | |
143 | ||
333943ba PW |
144 | /** |
145 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
146 | * @clk: OMAP clock struct ptr to use | |
147 | * | |
148 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
149 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
150 | * called during clk_register(). No return value. | |
151 | */ | |
152 | void omap2_init_clk_clkdm(struct clk *clk) | |
153 | { | |
154 | struct clockdomain *clkdm; | |
155 | ||
156 | if (!clk->clkdm_name) | |
157 | return; | |
158 | ||
159 | clkdm = clkdm_lookup(clk->clkdm_name); | |
160 | if (clkdm) { | |
161 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
162 | clk->name, clk->clkdm_name); | |
163 | clk->clkdm = clkdm; | |
164 | } else { | |
165 | pr_debug("clock: could not associate clk %s to " | |
166 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
167 | } | |
168 | } | |
169 | ||
543d9378 PW |
170 | /** |
171 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | |
172 | * @clk: OMAP clock struct ptr to use | |
173 | * | |
174 | * Given a pointer to a source-selectable struct clk, read the hardware | |
175 | * register and determine what its parent is currently set to. Update the | |
176 | * clk->parent field with the appropriate clk ptr. | |
177 | */ | |
178 | void omap2_init_clksel_parent(struct clk *clk) | |
179 | { | |
180 | const struct clksel *clks; | |
181 | const struct clksel_rate *clkr; | |
182 | u32 r, found = 0; | |
183 | ||
184 | if (!clk->clksel) | |
185 | return; | |
186 | ||
187 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | |
188 | r >>= __ffs(clk->clksel_mask); | |
189 | ||
190 | for (clks = clk->clksel; clks->parent && !found; clks++) { | |
191 | for (clkr = clks->rates; clkr->div && !found; clkr++) { | |
192 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { | |
193 | if (clk->parent != clks->parent) { | |
194 | pr_debug("clock: inited %s parent " | |
195 | "to %s (was %s)\n", | |
196 | clk->name, clks->parent->name, | |
197 | ((clk->parent) ? | |
198 | clk->parent->name : "NULL")); | |
3f0a820c | 199 | clk_reparent(clk, clks->parent); |
543d9378 PW |
200 | }; |
201 | found = 1; | |
202 | } | |
203 | } | |
204 | } | |
205 | ||
206 | if (!found) | |
207 | printk(KERN_ERR "clock: init parent: could not find " | |
208 | "regval %0x for clock %s\n", r, clk->name); | |
209 | ||
210 | return; | |
211 | } | |
212 | ||
c0bf3132 RK |
213 | /** |
214 | * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate | |
215 | * @clk: struct clk * of a DPLL | |
216 | * | |
217 | * DPLLs can be locked or bypassed - basically, enabled or disabled. | |
218 | * When locked, the DPLL output depends on the M and N values. When | |
219 | * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock | |
220 | * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and | |
221 | * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively | |
222 | * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. | |
223 | * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is | |
224 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | |
225 | * if the clock @clk is not a DPLL. | |
226 | */ | |
543d9378 PW |
227 | u32 omap2_get_dpll_rate(struct clk *clk) |
228 | { | |
229 | long long dpll_clk; | |
c0bf3132 | 230 | u32 dpll_mult, dpll_div, v; |
88b8ba90 | 231 | struct dpll_data *dd; |
543d9378 PW |
232 | |
233 | dd = clk->dpll_data; | |
543d9378 PW |
234 | if (!dd) |
235 | return 0; | |
236 | ||
c0bf3132 RK |
237 | /* Return bypass rate if DPLL is bypassed */ |
238 | v = __raw_readl(dd->control_reg); | |
239 | v &= dd->enable_mask; | |
240 | v >>= __ffs(dd->enable_mask); | |
241 | ||
242 | if (cpu_is_omap24xx()) { | |
243 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | |
244 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | |
245 | return dd->clk_bypass->rate; | |
246 | } else if (cpu_is_omap34xx()) { | |
247 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | |
248 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | |
249 | return dd->clk_bypass->rate; | |
250 | } | |
251 | ||
252 | v = __raw_readl(dd->mult_div1_reg); | |
253 | dpll_mult = v & dd->mult_mask; | |
543d9378 | 254 | dpll_mult >>= __ffs(dd->mult_mask); |
c0bf3132 | 255 | dpll_div = v & dd->div1_mask; |
543d9378 PW |
256 | dpll_div >>= __ffs(dd->div1_mask); |
257 | ||
c0bf3132 | 258 | dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; |
543d9378 PW |
259 | do_div(dpll_clk, dpll_div + 1); |
260 | ||
543d9378 PW |
261 | return dpll_clk; |
262 | } | |
263 | ||
264 | /* | |
265 | * Used for clocks that have the same value as the parent clock, | |
266 | * divided by some factor | |
267 | */ | |
8b9dbc16 | 268 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk) |
543d9378 PW |
269 | { |
270 | WARN_ON(!clk->fixed_div); | |
271 | ||
8b9dbc16 | 272 | return clk->parent->rate / clk->fixed_div; |
543d9378 PW |
273 | } |
274 | ||
275 | /** | |
72350b29 PW |
276 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
277 | * @clk: struct clk * to find the companion clock of | |
278 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
279 | * @other_bit: u8 ** to return the companion clock bit shift in | |
280 | * | |
281 | * Note: We don't need special code here for INVERT_ENABLE for the | |
282 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
283 | * CM_CLKEN_PLL | |
543d9378 | 284 | * |
72350b29 PW |
285 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
286 | * just a matter of XORing the bits. | |
287 | * | |
288 | * Some clocks don't have companion clocks. For example, modules with | |
289 | * only an interface clock (such as MAILBOXES) don't have a companion | |
290 | * clock. Right now, this code relies on the hardware exporting a bit | |
291 | * in the correct companion register that indicates that the | |
292 | * nonexistent 'companion clock' is active. Future patches will | |
293 | * associate this type of code with per-module data structures to | |
294 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 295 | */ |
72350b29 PW |
296 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
297 | u8 *other_bit) | |
543d9378 | 298 | { |
72350b29 | 299 | u32 r; |
543d9378 PW |
300 | |
301 | /* | |
72350b29 PW |
302 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
303 | * it's just a matter of XORing the bits. | |
543d9378 | 304 | */ |
72350b29 | 305 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 306 | |
72350b29 PW |
307 | *other_reg = (__force void __iomem *)r; |
308 | *other_bit = clk->enable_bit; | |
309 | } | |
543d9378 | 310 | |
72350b29 PW |
311 | /** |
312 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
313 | * @clk: struct clk * to find IDLEST info for | |
314 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
315 | * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in | |
316 | * | |
317 | * Return the CM_IDLEST register address and bit shift corresponding | |
318 | * to the module that "owns" this clock. This default code assumes | |
319 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
320 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
321 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
322 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 323 | */ |
72350b29 PW |
324 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
325 | u8 *idlest_bit) | |
543d9378 | 326 | { |
72350b29 | 327 | u32 r; |
543d9378 | 328 | |
72350b29 PW |
329 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
330 | *idlest_reg = (__force void __iomem *)r; | |
331 | *idlest_bit = clk->enable_bit; | |
332 | } | |
543d9378 | 333 | |
72350b29 PW |
334 | /** |
335 | * omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
336 | * @clk: struct clk * belonging to the module | |
337 | * | |
338 | * If the necessary clocks for the OMAP hardware IP block that | |
339 | * corresponds to clock @clk are enabled, then wait for the module to | |
340 | * indicate readiness (i.e., to leave IDLE). This code does not | |
341 | * belong in the clock code and will be moved in the medium term to | |
342 | * module-dependent code. No return value. | |
343 | */ | |
344 | static void omap2_module_wait_ready(struct clk *clk) | |
345 | { | |
346 | void __iomem *companion_reg, *idlest_reg; | |
347 | u8 other_bit, idlest_bit; | |
348 | ||
349 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
350 | if (clk->ops->find_companion) { | |
351 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
352 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
353 | return; | |
354 | } | |
543d9378 | 355 | |
72350b29 | 356 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); |
543d9378 | 357 | |
72350b29 | 358 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); |
543d9378 PW |
359 | } |
360 | ||
72350b29 | 361 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 362 | { |
ee1eec36 | 363 | u32 v; |
543d9378 | 364 | |
c0fc18c5 | 365 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 366 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
367 | clk->name); |
368 | return 0; /* REVISIT: -EINVAL */ | |
369 | } | |
370 | ||
ee1eec36 | 371 | v = __raw_readl(clk->enable_reg); |
543d9378 | 372 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 373 | v &= ~(1 << clk->enable_bit); |
543d9378 | 374 | else |
ee1eec36 PW |
375 | v |= (1 << clk->enable_bit); |
376 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 377 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 378 | |
72350b29 PW |
379 | if (clk->ops->find_idlest) |
380 | omap2_module_wait_ready(clk); | |
543d9378 | 381 | |
72350b29 | 382 | return 0; |
bc51da4e RK |
383 | } |
384 | ||
72350b29 | 385 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 386 | { |
ee1eec36 | 387 | u32 v; |
543d9378 | 388 | |
fecb494b | 389 | if (!clk->enable_reg) { |
543d9378 PW |
390 | /* |
391 | * 'Independent' here refers to a clock which is not | |
392 | * controlled by its parent. | |
393 | */ | |
394 | printk(KERN_ERR "clock: clk_disable called on independent " | |
395 | "clock %s which has no enable_reg\n", clk->name); | |
396 | return; | |
397 | } | |
398 | ||
ee1eec36 | 399 | v = __raw_readl(clk->enable_reg); |
543d9378 | 400 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 401 | v |= (1 << clk->enable_bit); |
543d9378 | 402 | else |
ee1eec36 PW |
403 | v &= ~(1 << clk->enable_bit); |
404 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 405 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
406 | } |
407 | ||
b36ee724 | 408 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 409 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 410 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
411 | .find_companion = omap2_clk_dflt_find_companion, |
412 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
413 | }; |
414 | ||
bc51da4e RK |
415 | const struct clkops clkops_omap2_dflt = { |
416 | .enable = omap2_dflt_clk_enable, | |
417 | .disable = omap2_dflt_clk_disable, | |
418 | }; | |
419 | ||
b36ee724 RK |
420 | /* Enables clock without considering parent dependencies or use count |
421 | * REVISIT: Maybe change this to use clk->enable like on omap1? | |
422 | */ | |
423 | static int _omap2_clk_enable(struct clk *clk) | |
424 | { | |
425 | return clk->ops->enable(clk); | |
426 | } | |
427 | ||
428 | /* Disables clock without considering parent dependencies or use count */ | |
429 | static void _omap2_clk_disable(struct clk *clk) | |
430 | { | |
431 | clk->ops->disable(clk); | |
543d9378 PW |
432 | } |
433 | ||
434 | void omap2_clk_disable(struct clk *clk) | |
435 | { | |
436 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
437 | _omap2_clk_disable(clk); | |
fecb494b | 438 | if (clk->parent) |
543d9378 | 439 | omap2_clk_disable(clk->parent); |
333943ba PW |
440 | if (clk->clkdm) |
441 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
442 | ||
543d9378 PW |
443 | } |
444 | } | |
445 | ||
446 | int omap2_clk_enable(struct clk *clk) | |
447 | { | |
448 | int ret = 0; | |
449 | ||
450 | if (clk->usecount++ == 0) { | |
333943ba PW |
451 | if (clk->clkdm) |
452 | omap2_clkdm_clk_enable(clk->clkdm, clk); | |
453 | ||
a7f8c599 | 454 | if (clk->parent) { |
543d9378 | 455 | ret = omap2_clk_enable(clk->parent); |
a7f8c599 RK |
456 | if (ret) |
457 | goto err; | |
543d9378 | 458 | } |
333943ba | 459 | |
543d9378 | 460 | ret = _omap2_clk_enable(clk); |
a7f8c599 | 461 | if (ret) { |
a7f8c599 | 462 | if (clk->parent) |
333943ba | 463 | omap2_clk_disable(clk->parent); |
a7f8c599 RK |
464 | |
465 | goto err; | |
543d9378 PW |
466 | } |
467 | } | |
a7f8c599 | 468 | return ret; |
543d9378 | 469 | |
a7f8c599 | 470 | err: |
8263e5b3 RK |
471 | if (clk->clkdm) |
472 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
a7f8c599 | 473 | clk->usecount--; |
543d9378 PW |
474 | return ret; |
475 | } | |
476 | ||
477 | /* | |
478 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | |
479 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | |
480 | */ | |
8b9dbc16 | 481 | unsigned long omap2_clksel_recalc(struct clk *clk) |
543d9378 | 482 | { |
8b9dbc16 | 483 | unsigned long rate; |
543d9378 PW |
484 | u32 div = 0; |
485 | ||
486 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | |
487 | ||
488 | div = omap2_clksel_get_divisor(clk); | |
489 | if (div == 0) | |
8b9dbc16 | 490 | return clk->rate; |
543d9378 | 491 | |
8b9dbc16 | 492 | rate = clk->parent->rate / div; |
543d9378 | 493 | |
8b9dbc16 | 494 | pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); |
543d9378 | 495 | |
8b9dbc16 | 496 | return rate; |
543d9378 PW |
497 | } |
498 | ||
499 | /** | |
500 | * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent | |
501 | * @clk: OMAP struct clk ptr to inspect | |
502 | * @src_clk: OMAP struct clk ptr of the parent clk to search for | |
503 | * | |
504 | * Scan the struct clksel array associated with the clock to find | |
505 | * the element associated with the supplied parent clock address. | |
506 | * Returns a pointer to the struct clksel on success or NULL on error. | |
507 | */ | |
fecb494b PW |
508 | static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, |
509 | struct clk *src_clk) | |
543d9378 PW |
510 | { |
511 | const struct clksel *clks; | |
512 | ||
513 | if (!clk->clksel) | |
514 | return NULL; | |
515 | ||
516 | for (clks = clk->clksel; clks->parent; clks++) { | |
517 | if (clks->parent == src_clk) | |
518 | break; /* Found the requested parent */ | |
519 | } | |
520 | ||
521 | if (!clks->parent) { | |
522 | printk(KERN_ERR "clock: Could not find parent clock %s in " | |
523 | "clksel array of clock %s\n", src_clk->name, | |
524 | clk->name); | |
525 | return NULL; | |
526 | } | |
527 | ||
528 | return clks; | |
529 | } | |
530 | ||
531 | /** | |
532 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate | |
533 | * @clk: OMAP struct clk to use | |
534 | * @target_rate: desired clock rate | |
535 | * @new_div: ptr to where we should store the divisor | |
536 | * | |
537 | * Finds 'best' divider value in an array based on the source and target | |
538 | * rates. The divider array must be sorted with smallest divider first. | |
539 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | |
540 | * they are only settable as part of virtual_prcm set. | |
541 | * | |
542 | * Returns the rounded clock rate or returns 0xffffffff on error. | |
543 | */ | |
544 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |
545 | u32 *new_div) | |
546 | { | |
547 | unsigned long test_rate; | |
548 | const struct clksel *clks; | |
549 | const struct clksel_rate *clkr; | |
550 | u32 last_div = 0; | |
551 | ||
b7aee4bf PW |
552 | pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", |
553 | clk->name, target_rate); | |
543d9378 PW |
554 | |
555 | *new_div = 1; | |
556 | ||
557 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
fecb494b | 558 | if (!clks) |
543d9378 PW |
559 | return ~0; |
560 | ||
561 | for (clkr = clks->rates; clkr->div; clkr++) { | |
562 | if (!(clkr->flags & cpu_mask)) | |
563 | continue; | |
564 | ||
565 | /* Sanity check */ | |
566 | if (clkr->div <= last_div) | |
b7aee4bf | 567 | pr_err("clock: clksel_rate table not sorted " |
543d9378 PW |
568 | "for clock %s", clk->name); |
569 | ||
570 | last_div = clkr->div; | |
571 | ||
572 | test_rate = clk->parent->rate / clkr->div; | |
573 | ||
574 | if (test_rate <= target_rate) | |
575 | break; /* found it */ | |
576 | } | |
577 | ||
578 | if (!clkr->div) { | |
b7aee4bf | 579 | pr_err("clock: Could not find divisor for target " |
543d9378 PW |
580 | "rate %ld for clock %s parent %s\n", target_rate, |
581 | clk->name, clk->parent->name); | |
582 | return ~0; | |
583 | } | |
584 | ||
585 | *new_div = clkr->div; | |
586 | ||
b7aee4bf PW |
587 | pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, |
588 | (clk->parent->rate / clkr->div)); | |
543d9378 PW |
589 | |
590 | return (clk->parent->rate / clkr->div); | |
591 | } | |
592 | ||
593 | /** | |
594 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate | |
595 | * @clk: OMAP struct clk to use | |
596 | * @target_rate: desired clock rate | |
597 | * | |
598 | * Compatibility wrapper for OMAP clock framework | |
599 | * Finds best target rate based on the source clock and possible dividers. | |
600 | * rates. The divider array must be sorted with smallest divider first. | |
601 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | |
602 | * they are only settable as part of virtual_prcm set. | |
603 | * | |
604 | * Returns the rounded clock rate or returns 0xffffffff on error. | |
605 | */ | |
606 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | |
607 | { | |
608 | u32 new_div; | |
609 | ||
610 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); | |
611 | } | |
612 | ||
613 | ||
614 | /* Given a clock and a rate apply a clock specific rounding function */ | |
615 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |
616 | { | |
fecb494b | 617 | if (clk->round_rate) |
543d9378 PW |
618 | return clk->round_rate(clk, rate); |
619 | ||
620 | if (clk->flags & RATE_FIXED) | |
621 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " | |
622 | "on fixed-rate clock %s\n", clk->name); | |
623 | ||
624 | return clk->rate; | |
625 | } | |
626 | ||
627 | /** | |
628 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider | |
629 | * @clk: OMAP struct clk to use | |
630 | * @field_val: register field value to find | |
631 | * | |
632 | * Given a struct clk of a rate-selectable clksel clock, and a register field | |
633 | * value to search for, find the corresponding clock divisor. The register | |
634 | * field value should be pre-masked and shifted down so the LSB is at bit 0 | |
635 | * before calling. Returns 0 on error | |
636 | */ | |
637 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | |
638 | { | |
639 | const struct clksel *clks; | |
640 | const struct clksel_rate *clkr; | |
641 | ||
642 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
fecb494b | 643 | if (!clks) |
543d9378 PW |
644 | return 0; |
645 | ||
646 | for (clkr = clks->rates; clkr->div; clkr++) { | |
647 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) | |
648 | break; | |
649 | } | |
650 | ||
651 | if (!clkr->div) { | |
652 | printk(KERN_ERR "clock: Could not find fieldval %d for " | |
653 | "clock %s parent %s\n", field_val, clk->name, | |
654 | clk->parent->name); | |
655 | return 0; | |
656 | } | |
657 | ||
658 | return clkr->div; | |
659 | } | |
660 | ||
661 | /** | |
662 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value | |
663 | * @clk: OMAP struct clk to use | |
664 | * @div: integer divisor to search for | |
665 | * | |
666 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, | |
667 | * find the corresponding register field value. The return register value is | |
9132f1b4 | 668 | * the value before left-shifting. Returns ~0 on error |
543d9378 PW |
669 | */ |
670 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |
671 | { | |
672 | const struct clksel *clks; | |
673 | const struct clksel_rate *clkr; | |
674 | ||
675 | /* should never happen */ | |
676 | WARN_ON(div == 0); | |
677 | ||
678 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
fecb494b | 679 | if (!clks) |
9132f1b4 | 680 | return ~0; |
543d9378 PW |
681 | |
682 | for (clkr = clks->rates; clkr->div; clkr++) { | |
683 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) | |
684 | break; | |
685 | } | |
686 | ||
687 | if (!clkr->div) { | |
688 | printk(KERN_ERR "clock: Could not find divisor %d for " | |
689 | "clock %s parent %s\n", div, clk->name, | |
690 | clk->parent->name); | |
9132f1b4 | 691 | return ~0; |
543d9378 PW |
692 | } |
693 | ||
694 | return clkr->val; | |
695 | } | |
696 | ||
543d9378 PW |
697 | /** |
698 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | |
699 | * @clk: OMAP struct clk to use. | |
700 | * | |
701 | * Returns the integer divisor upon success or 0 on error. | |
702 | */ | |
703 | u32 omap2_clksel_get_divisor(struct clk *clk) | |
704 | { | |
ee1eec36 | 705 | u32 v; |
543d9378 | 706 | |
ee1eec36 | 707 | if (!clk->clksel_mask) |
543d9378 PW |
708 | return 0; |
709 | ||
ee1eec36 PW |
710 | v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; |
711 | v >>= __ffs(clk->clksel_mask); | |
543d9378 | 712 | |
ee1eec36 | 713 | return omap2_clksel_to_divisor(clk, v); |
543d9378 PW |
714 | } |
715 | ||
716 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | |
717 | { | |
ee1eec36 | 718 | u32 v, field_val, validrate, new_div = 0; |
543d9378 | 719 | |
ee1eec36 | 720 | if (!clk->clksel_mask) |
543d9378 PW |
721 | return -EINVAL; |
722 | ||
ee1eec36 PW |
723 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
724 | if (validrate != rate) | |
543d9378 PW |
725 | return -EINVAL; |
726 | ||
727 | field_val = omap2_divisor_to_clksel(clk, new_div); | |
728 | if (field_val == ~0) | |
729 | return -EINVAL; | |
730 | ||
ee1eec36 PW |
731 | v = __raw_readl(clk->clksel_reg); |
732 | v &= ~clk->clksel_mask; | |
733 | v |= field_val << __ffs(clk->clksel_mask); | |
734 | __raw_writel(v, clk->clksel_reg); | |
f11fda6a | 735 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ |
543d9378 PW |
736 | |
737 | clk->rate = clk->parent->rate / new_div; | |
738 | ||
439764cc | 739 | _omap2xxx_clk_commit(clk); |
543d9378 PW |
740 | |
741 | return 0; | |
742 | } | |
743 | ||
744 | ||
745 | /* Set the clock rate for a clock source */ | |
746 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
747 | { | |
748 | int ret = -EINVAL; | |
749 | ||
750 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
751 | ||
752 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | |
753 | rate table mechanism, driven by mpu_speed */ | |
754 | if (clk->flags & CONFIG_PARTICIPANT) | |
755 | return -EINVAL; | |
756 | ||
757 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | |
fecb494b | 758 | if (clk->set_rate) |
543d9378 PW |
759 | ret = clk->set_rate(clk, rate); |
760 | ||
543d9378 PW |
761 | return ret; |
762 | } | |
763 | ||
764 | /* | |
765 | * Converts encoded control register address into a full address | |
ee1eec36 | 766 | * On error, the return value (parent_div) will be 0. |
543d9378 | 767 | */ |
ee1eec36 PW |
768 | static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, |
769 | u32 *field_val) | |
543d9378 PW |
770 | { |
771 | const struct clksel *clks; | |
772 | const struct clksel_rate *clkr; | |
773 | ||
543d9378 | 774 | clks = omap2_get_clksel_by_parent(clk, src_clk); |
fecb494b | 775 | if (!clks) |
543d9378 PW |
776 | return 0; |
777 | ||
778 | for (clkr = clks->rates; clkr->div; clkr++) { | |
abf23965 | 779 | if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) |
543d9378 PW |
780 | break; /* Found the default rate for this platform */ |
781 | } | |
782 | ||
783 | if (!clkr->div) { | |
784 | printk(KERN_ERR "clock: Could not find default rate for " | |
785 | "clock %s parent %s\n", clk->name, | |
786 | src_clk->parent->name); | |
787 | return 0; | |
788 | } | |
789 | ||
790 | /* Should never happen. Add a clksel mask to the struct clk. */ | |
791 | WARN_ON(clk->clksel_mask == 0); | |
792 | ||
ee1eec36 | 793 | *field_val = clkr->val; |
543d9378 | 794 | |
ee1eec36 | 795 | return clkr->div; |
543d9378 PW |
796 | } |
797 | ||
798 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |
799 | { | |
ee1eec36 | 800 | u32 field_val, v, parent_div; |
543d9378 | 801 | |
fecb494b | 802 | if (clk->flags & CONFIG_PARTICIPANT) |
543d9378 PW |
803 | return -EINVAL; |
804 | ||
805 | if (!clk->clksel) | |
806 | return -EINVAL; | |
807 | ||
ee1eec36 PW |
808 | parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); |
809 | if (!parent_div) | |
543d9378 PW |
810 | return -EINVAL; |
811 | ||
543d9378 | 812 | /* Set new source value (previous dividers if any in effect) */ |
ee1eec36 PW |
813 | v = __raw_readl(clk->clksel_reg); |
814 | v &= ~clk->clksel_mask; | |
815 | v |= field_val << __ffs(clk->clksel_mask); | |
816 | __raw_writel(v, clk->clksel_reg); | |
f11fda6a | 817 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ |
543d9378 | 818 | |
439764cc | 819 | _omap2xxx_clk_commit(clk); |
543d9378 | 820 | |
3f0a820c | 821 | clk_reparent(clk, new_parent); |
41f3103f | 822 | |
543d9378 PW |
823 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
824 | clk->rate = new_parent->rate; | |
825 | ||
826 | if (parent_div > 0) | |
827 | clk->rate /= parent_div; | |
828 | ||
829 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | |
830 | clk->name, clk->parent->name, clk->rate); | |
831 | ||
543d9378 PW |
832 | return 0; |
833 | } | |
834 | ||
88b8ba90 PW |
835 | /* DPLL rate rounding code */ |
836 | ||
837 | /** | |
838 | * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding | |
839 | * @clk: struct clk * of the DPLL | |
840 | * @tolerance: maximum rate error tolerance | |
841 | * | |
842 | * Set the maximum DPLL rate error tolerance for the rate rounding | |
843 | * algorithm. The rate tolerance is an attempt to balance DPLL power | |
844 | * saving (the least divider value "n") vs. rate fidelity (the least | |
845 | * difference between the desired DPLL target rate and the rounded | |
846 | * rate out of the algorithm). So, increasing the tolerance is likely | |
847 | * to decrease DPLL power consumption and increase DPLL rate error. | |
848 | * Returns -EINVAL if provided a null clock ptr or a clk that is not a | |
849 | * DPLL; or 0 upon success. | |
850 | */ | |
851 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | |
852 | { | |
853 | if (!clk || !clk->dpll_data) | |
854 | return -EINVAL; | |
855 | ||
856 | clk->dpll_data->rate_tolerance = tolerance; | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
fecb494b PW |
861 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, |
862 | unsigned int m, unsigned int n) | |
88b8ba90 PW |
863 | { |
864 | unsigned long long num; | |
865 | ||
866 | num = (unsigned long long)parent_rate * m; | |
867 | do_div(num, n); | |
868 | return num; | |
869 | } | |
870 | ||
871 | /* | |
872 | * _dpll_test_mult - test a DPLL multiplier value | |
873 | * @m: pointer to the DPLL m (multiplier) value under test | |
874 | * @n: current DPLL n (divider) value under test | |
875 | * @new_rate: pointer to storage for the resulting rounded rate | |
876 | * @target_rate: the desired DPLL rate | |
877 | * @parent_rate: the DPLL's parent clock rate | |
878 | * | |
879 | * This code tests a DPLL multiplier value, ensuring that the | |
880 | * resulting rate will not be higher than the target_rate, and that | |
881 | * the multiplier value itself is valid for the DPLL. Initially, the | |
882 | * integer pointed to by the m argument should be prescaled by | |
883 | * multiplying by DPLL_SCALE_FACTOR. The code will replace this with | |
884 | * a non-scaled m upon return. This non-scaled m will result in a | |
885 | * new_rate as close as possible to target_rate (but not greater than | |
886 | * target_rate) given the current (parent_rate, n, prescaled m) | |
887 | * triple. Returns DPLL_MULT_UNDERFLOW in the event that the | |
888 | * non-scaled m attempted to underflow, which can allow the calling | |
889 | * function to bail out early; or 0 upon success. | |
890 | */ | |
891 | static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |
892 | unsigned long target_rate, | |
893 | unsigned long parent_rate) | |
894 | { | |
85a5f78d | 895 | int r = 0, carry = 0; |
88b8ba90 PW |
896 | |
897 | /* Unscale m and round if necessary */ | |
898 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | |
899 | carry = 1; | |
900 | *m = (*m / DPLL_SCALE_FACTOR) + carry; | |
901 | ||
902 | /* | |
903 | * The new rate must be <= the target rate to avoid programming | |
904 | * a rate that is impossible for the hardware to handle | |
905 | */ | |
906 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | |
907 | if (*new_rate > target_rate) { | |
908 | (*m)--; | |
909 | *new_rate = 0; | |
910 | } | |
911 | ||
912 | /* Guard against m underflow */ | |
913 | if (*m < DPLL_MIN_MULTIPLIER) { | |
914 | *m = DPLL_MIN_MULTIPLIER; | |
915 | *new_rate = 0; | |
85a5f78d | 916 | r = DPLL_MULT_UNDERFLOW; |
88b8ba90 PW |
917 | } |
918 | ||
919 | if (*new_rate == 0) | |
920 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | |
921 | ||
85a5f78d | 922 | return r; |
88b8ba90 PW |
923 | } |
924 | ||
925 | /** | |
926 | * omap2_dpll_round_rate - round a target rate for an OMAP DPLL | |
927 | * @clk: struct clk * for a DPLL | |
928 | * @target_rate: desired DPLL clock rate | |
929 | * | |
930 | * Given a DPLL, a desired target rate, and a rate tolerance, round | |
931 | * the target rate to a possible, programmable rate for this DPLL. | |
932 | * Rate tolerance is assumed to be set by the caller before this | |
933 | * function is called. Attempts to select the minimum possible n | |
934 | * within the tolerance to reduce power consumption. Stores the | |
935 | * computed (m, n) in the DPLL's dpll_data structure so set_rate() | |
936 | * will not need to call this (expensive) function again. Returns ~0 | |
937 | * if the target rate cannot be rounded, either because the rate is | |
938 | * too low or because the rate tolerance is set too tightly; or the | |
939 | * rounded rate upon success. | |
940 | */ | |
941 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |
942 | { | |
943 | int m, n, r, e, scaled_max_m; | |
944 | unsigned long scaled_rt_rp, new_rate; | |
945 | int min_e = -1, min_e_m = -1, min_e_n = -1; | |
b3245040 | 946 | struct dpll_data *dd; |
88b8ba90 PW |
947 | |
948 | if (!clk || !clk->dpll_data) | |
949 | return ~0; | |
950 | ||
b3245040 PW |
951 | dd = clk->dpll_data; |
952 | ||
88b8ba90 PW |
953 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " |
954 | "%ld\n", clk->name, target_rate); | |
955 | ||
c0bf3132 | 956 | scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); |
b3245040 | 957 | scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; |
88b8ba90 | 958 | |
b3245040 | 959 | dd->last_rounded_rate = 0; |
88b8ba90 | 960 | |
95f538ac PW |
961 | for (n = dd->min_divider; n <= dd->max_divider; n++) { |
962 | ||
963 | /* Is the (input clk, divider) pair valid for the DPLL? */ | |
964 | r = _dpll_test_fint(clk, n); | |
965 | if (r == DPLL_FINT_UNDERFLOW) | |
966 | break; | |
967 | else if (r == DPLL_FINT_INVALID) | |
968 | continue; | |
88b8ba90 PW |
969 | |
970 | /* Compute the scaled DPLL multiplier, based on the divider */ | |
971 | m = scaled_rt_rp * n; | |
972 | ||
973 | /* | |
85a5f78d PW |
974 | * Since we're counting n up, a m overflow means we |
975 | * can bail out completely (since as n increases in | |
976 | * the next iteration, there's no way that m can | |
977 | * increase beyond the current m) | |
88b8ba90 PW |
978 | */ |
979 | if (m > scaled_max_m) | |
85a5f78d | 980 | break; |
88b8ba90 PW |
981 | |
982 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | |
c0bf3132 | 983 | dd->clk_ref->rate); |
88b8ba90 | 984 | |
85a5f78d PW |
985 | /* m can't be set low enough for this n - try with a larger n */ |
986 | if (r == DPLL_MULT_UNDERFLOW) | |
987 | continue; | |
88b8ba90 PW |
988 | |
989 | e = target_rate - new_rate; | |
990 | pr_debug("clock: n = %d: m = %d: rate error is %d " | |
991 | "(new_rate = %ld)\n", n, m, e, new_rate); | |
992 | ||
993 | if (min_e == -1 || | |
b3245040 | 994 | min_e >= (int)(abs(e) - dd->rate_tolerance)) { |
88b8ba90 PW |
995 | min_e = e; |
996 | min_e_m = m; | |
997 | min_e_n = n; | |
998 | ||
999 | pr_debug("clock: found new least error %d\n", min_e); | |
88b8ba90 | 1000 | |
85a5f78d | 1001 | /* We found good settings -- bail out now */ |
95f538ac | 1002 | if (min_e <= dd->rate_tolerance) |
85a5f78d PW |
1003 | break; |
1004 | } | |
88b8ba90 PW |
1005 | } |
1006 | ||
1007 | if (min_e < 0) { | |
1008 | pr_debug("clock: error: target rate or tolerance too low\n"); | |
1009 | return ~0; | |
1010 | } | |
1011 | ||
b3245040 PW |
1012 | dd->last_rounded_m = min_e_m; |
1013 | dd->last_rounded_n = min_e_n; | |
c0bf3132 | 1014 | dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, |
b3245040 | 1015 | min_e_m, min_e_n); |
88b8ba90 PW |
1016 | |
1017 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | |
1018 | min_e, min_e_m, min_e_n); | |
1019 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | |
b3245040 | 1020 | dd->last_rounded_rate, target_rate); |
88b8ba90 | 1021 | |
b3245040 | 1022 | return dd->last_rounded_rate; |
88b8ba90 PW |
1023 | } |
1024 | ||
543d9378 PW |
1025 | /*------------------------------------------------------------------------- |
1026 | * Omap2 clock reset and init functions | |
1027 | *-------------------------------------------------------------------------*/ | |
1028 | ||
1029 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
1030 | void omap2_clk_disable_unused(struct clk *clk) | |
1031 | { | |
1032 | u32 regval32, v; | |
1033 | ||
1034 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
1035 | ||
1036 | regval32 = __raw_readl(clk->enable_reg); | |
1037 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
1038 | return; | |
1039 | ||
0db4e825 | 1040 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
1041 | if (cpu_is_omap34xx()) { |
1042 | omap2_clk_enable(clk); | |
1043 | omap2_clk_disable(clk); | |
1044 | } else | |
1045 | _omap2_clk_disable(clk); | |
543d9378 PW |
1046 | } |
1047 | #endif |