[deliverable/linux.git] / arch / arm / mach-omap2 / clock24xx.c

/*
 *  linux/arch/arm/mach-omap2/clock.c
 *
 *  Copyright (C) 2005-2008 Texas Instruments, Inc.
 *  Copyright (C) 2004-2008 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
 *  Gordon McNutt and RidgeRun, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>

#include <mach/clock.h>
#include <mach/sram.h>
#include <asm/div64.h>
#include <asm/bitops.h>

#include "memory.h"
#include "clock.h"
#include "clock24xx.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"

/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
#define EN_APLL_STOPPED			0
#define EN_APLL_LOCKED			3

/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
#define APLLS_CLKIN_19_2MHZ		0
#define APLLS_CLKIN_13MHZ		2
#define APLLS_CLKIN_12MHZ		3

/* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */

static struct prcm_config *curr_prcm_set;
static struct clk *vclk;
static struct clk *sclk;

/*-------------------------------------------------------------------------
 * Omap24xx specific clock functions
 *-------------------------------------------------------------------------*/

/* This actually returns the rate of core_ck, not dpll_ck. */
static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
{
	long long dpll_clk;
	u8 amult;

	dpll_clk = omap2_get_dpll_rate(tclk);

	amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	amult &= OMAP24XX_CORE_CLK_SRC_MASK;
	dpll_clk *= amult;

	return dpll_clk;
}

static int omap2_enable_osc_ck(struct clk *clk)
{
	u32 pcc;

	pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);

	__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
		      OMAP24XX_PRCM_CLKSRC_CTRL);

	return 0;
}

static void omap2_disable_osc_ck(struct clk *clk)
{
	u32 pcc;

	pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);

	__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
		      OMAP24XX_PRCM_CLKSRC_CTRL);
}

#ifdef OLD_CK
/* Recalculate SYST_CLK */
static void omap2_sys_clk_recalc(struct clk * clk)
{
	u32 div = PRCM_CLKSRC_CTRL;
	div &= (1 << 7) | (1 << 6);	/* Test if ext clk divided by 1 or 2 */
	div >>= clk->rate_offset;
	clk->rate = (clk->parent->rate / div);
	propagate_rate(clk);
}
#endif	/* OLD_CK */

/* Enable an APLL if off */
static int omap2_clk_fixed_enable(struct clk *clk)
{
	u32 cval, apll_mask;

	apll_mask = EN_APLL_LOCKED << clk->enable_bit;

	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	if ((cval & apll_mask) == apll_mask)
		return 0;   /* apll already enabled */

	cval &= ~apll_mask;
	cval |= apll_mask;
	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

	if (clk == &apll96_ck)
		cval = OMAP24XX_ST_96M_APLL;
	else if (clk == &apll54_ck)
		cval = OMAP24XX_ST_54M_APLL;

	omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
			    clk->name);

	/*
	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
	 * fails?
	 */
	return 0;
}

/* Stop APLL */
static void omap2_clk_fixed_disable(struct clk *clk)
{
	u32 cval;

	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
}

/*
 * Uses the current prcm set to tell if a rate is valid.
 * You can go slower, but not faster within a given rate set.
 */
long omap2_dpllcore_round_rate(unsigned long target_rate)
{
	u32 high, low, core_clk_src;

	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;

	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
		high = curr_prcm_set->dpll_speed * 2;
		low = curr_prcm_set->dpll_speed;
	} else {				/* DPLL clockout x 2 */
		high = curr_prcm_set->dpll_speed;
		low = curr_prcm_set->dpll_speed / 2;
	}

#ifdef DOWN_VARIABLE_DPLL
	if (target_rate > high)
		return high;
	else
		return target_rate;
#else
	if (target_rate > low)
		return high;
	else
		return low;
#endif

}

static void omap2_dpllcore_recalc(struct clk *clk)
{
	clk->rate = omap2_get_dpll_rate_24xx(clk);

	propagate_rate(clk);
}

static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
{
	u32 cur_rate, low, mult, div, valid_rate, done_rate;
	u32 bypass = 0;
	struct prcm_config tmpset;
	const struct dpll_data *dd;
	unsigned long flags;
	int ret = -EINVAL;

	local_irq_save(flags);
	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	mult &= OMAP24XX_CORE_CLK_SRC_MASK;

	if ((rate == (cur_rate / 2)) && (mult == 2)) {
		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
	} else if (rate != cur_rate) {
		valid_rate = omap2_dpllcore_round_rate(rate);
		if (valid_rate != rate)
			goto dpll_exit;

		if (mult == 1)
			low = curr_prcm_set->dpll_speed;
		else
			low = curr_prcm_set->dpll_speed / 2;

		dd = clk->dpll_data;
		if (!dd)
			goto dpll_exit;

		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
					   dd->div1_mask);
		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
		tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
		if (rate > low) {
			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
			mult = ((rate / 2) / 1000000);
			done_rate = CORE_CLK_SRC_DPLL_X2;
		} else {
			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
			mult = (rate / 1000000);
			done_rate = CORE_CLK_SRC_DPLL;
		}
		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));

		/* Worst case */
		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;

		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
			bypass = 1;

		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */

		/* Force dll lock mode */
		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
			       bypass);

		/* Errata: ret dll entry state */
		omap2_init_memory_params(omap2_dll_force_needed());
		omap2_reprogram_sdrc(done_rate, 0);
	}
	omap2_dpllcore_recalc(&dpll_ck);
	ret = 0;

dpll_exit:
	local_irq_restore(flags);
	return(ret);
}

/**
 * omap2_table_mpu_recalc - just return the MPU speed
 * @clk: virt_prcm_set struct clk
 *
 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 */
static void omap2_table_mpu_recalc(struct clk *clk)
{
	clk->rate = curr_prcm_set->mpu_speed;
}

/*
 * Look for a rate equal or less than the target rate given a configuration set.
 *
 * What's not entirely clear is "which" field represents the key field.
 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 * just uses the ARM rates.
 */
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
	struct prcm_config *ptr;
	long highest_rate;

	if (clk != &virt_prcm_set)
		return -EINVAL;

	highest_rate = -EINVAL;

	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
		if (!(ptr->flags & cpu_mask))
			continue;
		if (ptr->xtal_speed != sys_ck.rate)
			continue;

		highest_rate = ptr->mpu_speed;

		/* Can check only after xtal frequency check */
		if (ptr->mpu_speed <= rate)
			break;
	}
	return highest_rate;
}

/* Sets basic clocks based on the specified rate */
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
{
	u32 cur_rate, done_rate, bypass = 0, tmp;
	struct prcm_config *prcm;
	unsigned long found_speed = 0;
	unsigned long flags;

	if (clk != &virt_prcm_set)
		return -EINVAL;

	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
			continue;

		if (prcm->xtal_speed != sys_ck.rate)
			continue;

		if (prcm->mpu_speed <= rate) {
			found_speed = prcm->mpu_speed;
			break;
		}
	}

	if (!found_speed) {
		printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
		       rate / 1000000);
		return -EINVAL;
	}

	curr_prcm_set = prcm;
	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);

	if (prcm->dpll_speed == cur_rate / 2) {
		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
	} else if (prcm->dpll_speed == cur_rate * 2) {
		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
	} else if (prcm->dpll_speed != cur_rate) {
		local_irq_save(flags);

		if (prcm->dpll_speed == prcm->xtal_speed)
			bypass = 1;

		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
		    CORE_CLK_SRC_DPLL_X2)
			done_rate = CORE_CLK_SRC_DPLL_X2;
		else
			done_rate = CORE_CLK_SRC_DPLL;

		/* MPU divider */
		cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);

		/* dsp + iva1 div(2420), iva2.1(2430) */
		cm_write_mod_reg(prcm->cm_clksel_dsp,
				 OMAP24XX_DSP_MOD, CM_CLKSEL);

		cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);

		/* Major subsystem dividers */
		tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
		cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
		if (cpu_is_omap2430())
			cm_write_mod_reg(prcm->cm_clksel_mdm,
					 OMAP2430_MDM_MOD, CM_CLKSEL);

		/* x2 to enter init_mem */
		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);

		omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
			       bypass);

		omap2_init_memory_params(omap2_dll_force_needed());
		omap2_reprogram_sdrc(done_rate, 0);

		local_irq_restore(flags);
	}
	omap2_dpllcore_recalc(&dpll_ck);

	return 0;
}

static struct clk_functions omap2_clk_functions = {
	.clk_enable		= omap2_clk_enable,
	.clk_disable		= omap2_clk_disable,
	.clk_round_rate		= omap2_clk_round_rate,
	.clk_set_rate		= omap2_clk_set_rate,
	.clk_set_parent		= omap2_clk_set_parent,
	.clk_disable_unused	= omap2_clk_disable_unused,
};

static u32 omap2_get_apll_clkin(void)
{
	u32 aplls, sclk = 0;

	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
	aplls &= OMAP24XX_APLLS_CLKIN_MASK;
	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;

	if (aplls == APLLS_CLKIN_19_2MHZ)
		sclk = 19200000;
	else if (aplls == APLLS_CLKIN_13MHZ)
		sclk = 13000000;
	else if (aplls == APLLS_CLKIN_12MHZ)
		sclk = 12000000;

	return sclk;
}

static u32 omap2_get_sysclkdiv(void)
{
	u32 div;

	div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
	div &= OMAP_SYSCLKDIV_MASK;
	div >>= OMAP_SYSCLKDIV_SHIFT;

	return div;
}

static void omap2_osc_clk_recalc(struct clk *clk)
{
	clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
	propagate_rate(clk);
}

static void omap2_sys_clk_recalc(struct clk *clk)
{
	clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
	propagate_rate(clk);
}

/*
 * Set clocks for bypass mode for reboot to work.
 */
void omap2_clk_prepare_for_reboot(void)
{
	u32 rate;

	if (vclk == NULL || sclk == NULL)
		return;

	rate = clk_get_rate(sclk);
	clk_set_rate(vclk, rate);
}

/*
 * Switch the MPU rate if specified on cmdline.
 * We cannot do this early until cmdline is parsed.
 */
static int __init omap2_clk_arch_init(void)
{
	if (!mpurate)
		return -EINVAL;

	if (omap2_select_table_rate(&virt_prcm_set, mpurate))
		printk(KERN_ERR "Could not find matching MPU rate\n");

	recalculate_root_clocks();

	printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
	       "%ld.%01ld/%ld/%ld MHz\n",
	       (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
	       (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;

	return 0;
}
arch_initcall(omap2_clk_arch_init);

int __init omap2_clk_init(void)
{
	struct prcm_config *prcm;
	struct clk **clkp;
	u32 clkrate;

	if (cpu_is_omap242x())
		cpu_mask = RATE_IN_242X;
	else if (cpu_is_omap2430())
		cpu_mask = RATE_IN_243X;

	clk_init(&omap2_clk_functions);

	omap2_osc_clk_recalc(&osc_ck);
	omap2_sys_clk_recalc(&sys_ck);

	for (clkp = onchip_24xx_clks;
	     clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
	     clkp++) {

		if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
			clk_register(*clkp);
			continue;
		}

		if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
			clk_register(*clkp);
			continue;
		}
	}

	/* Check the MPU rate set by bootloader */
	clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
			continue;
		if (prcm->xtal_speed != sys_ck.rate)
			continue;
		if (prcm->dpll_speed <= clkrate)
			 break;
	}
	curr_prcm_set = prcm;

	recalculate_root_clocks();

	printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
	       "%ld.%01ld/%ld/%ld MHz\n",
	       (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
	       (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;

	/*
	 * Only enable those clocks we will need, let the drivers
	 * enable other clocks as necessary
	 */
	clk_enable_init_clocks();

	/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
	vclk = clk_get(NULL, "virt_prcm_set");
	sclk = clk_get(NULL, "sys_ck");

	return 0;
}
Commit	Line	Data
046d6b28 TL	1	/*
	2	* linux/arch/arm/mach-omap2/clock.c
	3	*
a16e9703 TL	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
a16e9703 TL	5	* Copyright (C) 2004-2008 Nokia Corporation
046d6b28	6	*
a16e9703 TL	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
046d6b28	10	*
a16e9703 TL	11	* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
a16e9703 TL	12	* Gordon McNutt and RidgeRun, Inc.
046d6b28 TL	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
6b8858a9 PW	18	#undef DEBUG
6b8858a9 PW	19
046d6b28 TL	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/device.h>
	23	#include <linux/list.h>
	24	#include <linux/errno.h>
	25	#include <linux/delay.h>
f8ce2547	26	#include <linux/clk.h>
6b8858a9 PW	27	#include <linux/io.h>
6b8858a9 PW	28	#include <linux/cpufreq.h>
046d6b28	29
a09e64fb RK	30	#include <mach/clock.h>
a09e64fb RK	31	#include <mach/sram.h>
76631486	32	#include <asm/div64.h>
6b8858a9	33	#include <asm/bitops.h>
046d6b28	34
b824efae	35	#include "memory.h"
6b8858a9	36	#include "clock.h"
32ab2cb9	37	#include "clock24xx.h"
6b8858a9 PW	38	#include "prm.h"
	39	#include "prm-regbits-24xx.h"
	40	#include "cm.h"
	41	#include "cm-regbits-24xx.h"
046d6b28	42
6b8858a9 PW	43	/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
	44	#define EN_APLL_STOPPED 0
	45	#define EN_APLL_LOCKED 3
ddc32a87	46
6b8858a9 PW	47	/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
	48	#define APLLS_CLKIN_19_2MHZ 0
	49	#define APLLS_CLKIN_13MHZ 2
	50	#define APLLS_CLKIN_12MHZ 3
	51
	52	/* #define DOWN_VARIABLE_DPLL 1 / / Experimental */
046d6b28 TL	53
046d6b28 TL	54	static struct prcm_config *curr_prcm_set;
ae78dcf7 TL	55	static struct clk *vclk;
ae78dcf7 TL	56	static struct clk *sclk;
046d6b28 TL	57
046d6b28 TL	58	/*-------------------------------------------------------------------------
6b8858a9	59	* Omap24xx specific clock functions
046d6b28 TL	60	-------------------------------------------------------------------------/
046d6b28 TL	61
a16e9703 TL	62	/* This actually returns the rate of core_ck, not dpll_ck. */
	63	static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
	64	{
	65	long long dpll_clk;
	66	u8 amult;
	67
	68	dpll_clk = omap2_get_dpll_rate(tclk);
	69
	70	amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	71	amult &= OMAP24XX_CORE_CLK_SRC_MASK;
	72	dpll_clk *= amult;
	73
	74	return dpll_clk;
	75	}
	76
6b8858a9 PW	77	static int omap2_enable_osc_ck(struct clk *clk)
	78	{
	79	u32 pcc;
	80
	81	pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
	82
	83	__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
	84	OMAP24XX_PRCM_CLKSRC_CTRL);
	85
	86	return 0;
	87	}
	88
	89	static void omap2_disable_osc_ck(struct clk *clk)
	90	{
	91	u32 pcc;
	92
	93	pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
	94
	95	__raw_writel(pcc \| OMAP_AUTOEXTCLKMODE_MASK,
	96	OMAP24XX_PRCM_CLKSRC_CTRL);
	97	}
	98
	99	#ifdef OLD_CK
046d6b28 TL	100	/* Recalculate SYST_CLK */
	101	static void omap2_sys_clk_recalc(struct clk * clk)
	102	{
	103	u32 div = PRCM_CLKSRC_CTRL;
	104	div &= (1 << 7) \| (1 << 6); /* Test if ext clk divided by 1 or 2 */
	105	div >>= clk->rate_offset;
	106	clk->rate = (clk->parent->rate / div);
	107	propagate_rate(clk);
	108	}
6b8858a9	109	#endif /* OLD_CK */
046d6b28	110
046d6b28	111	/* Enable an APLL if off */
6b8858a9	112	static int omap2_clk_fixed_enable(struct clk *clk)
046d6b28	113	{
6b8858a9	114	u32 cval, apll_mask;
046d6b28	115
6b8858a9	116	apll_mask = EN_APLL_LOCKED << clk->enable_bit;
046d6b28	117
6b8858a9	118	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
046d6b28	119
6b8858a9 PW	120	if ((cval & apll_mask) == apll_mask)
6b8858a9 PW	121	return 0; /* apll already enabled */
046d6b28	122
6b8858a9 PW	123	cval &= ~apll_mask;
	124	cval \|= apll_mask;
	125	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28 TL	126
046d6b28 TL	127	if (clk == &apll96_ck)
6b8858a9	128	cval = OMAP24XX_ST_96M_APLL;
046d6b28	129	else if (clk == &apll54_ck)
6b8858a9	130	cval = OMAP24XX_ST_54M_APLL;
046d6b28	131
6b8858a9 PW	132	omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
	133	clk->name);
	134
	135	/*
	136	* REVISIT: Should we return an error code if omap2_wait_clock_ready()
	137	* fails?
	138	*/
	139	return 0;
046d6b28 TL	140	}
046d6b28 TL	141
046d6b28 TL	142	/* Stop APLL */
	143	static void omap2_clk_fixed_disable(struct clk *clk)
	144	{
	145	u32 cval;
	146
6b8858a9 PW	147	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	148	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
	149	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28 TL	150	}
046d6b28 TL	151
046d6b28 TL	152	/*
	153	* Uses the current prcm set to tell if a rate is valid.
	154	* You can go slower, but not faster within a given rate set.
	155	*/
88b8ba90	156	long omap2_dpllcore_round_rate(unsigned long target_rate)
046d6b28	157	{
6b8858a9	158	u32 high, low, core_clk_src;
046d6b28	159
6b8858a9 PW	160	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	161	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
	162
	163	if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
046d6b28 TL	164	high = curr_prcm_set->dpll_speed * 2;
	165	low = curr_prcm_set->dpll_speed;
	166	} else { /* DPLL clockout x 2 */
	167	high = curr_prcm_set->dpll_speed;
	168	low = curr_prcm_set->dpll_speed / 2;
	169	}
	170
	171	#ifdef DOWN_VARIABLE_DPLL
	172	if (target_rate > high)
	173	return high;
	174	else
	175	return target_rate;
	176	#else
	177	if (target_rate > low)
	178	return high;
	179	else
	180	return low;
	181	#endif
	182
	183	}
	184
88b8ba90	185	static void omap2_dpllcore_recalc(struct clk *clk)
6b8858a9 PW	186	{
	187	clk->rate = omap2_get_dpll_rate_24xx(clk);
	188
	189	propagate_rate(clk);
	190	}
046d6b28	191
88b8ba90	192	static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
046d6b28	193	{
6b8858a9	194	u32 cur_rate, low, mult, div, valid_rate, done_rate;
046d6b28 TL	195	u32 bypass = 0;
046d6b28 TL	196	struct prcm_config tmpset;
6b8858a9 PW	197	const struct dpll_data *dd;
6b8858a9 PW	198	unsigned long flags;
046d6b28 TL	199	int ret = -EINVAL;
	200
	201	local_irq_save(flags);
6b8858a9 PW	202	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
	203	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	204	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28 TL	205
046d6b28 TL	206	if ((rate == (cur_rate / 2)) && (mult == 2)) {
6b8858a9	207	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
046d6b28	208	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
6b8858a9	209	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28	210	} else if (rate != cur_rate) {
88b8ba90	211	valid_rate = omap2_dpllcore_round_rate(rate);
046d6b28 TL	212	if (valid_rate != rate)
	213	goto dpll_exit;
	214
6b8858a9	215	if (mult == 1)
046d6b28 TL	216	low = curr_prcm_set->dpll_speed;
	217	else
	218	low = curr_prcm_set->dpll_speed / 2;
	219
6b8858a9 PW	220	dd = clk->dpll_data;
	221	if (!dd)
	222	goto dpll_exit;
	223
	224	tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
	225	tmpset.cm_clksel1_pll &= ~(dd->mult_mask \|
	226	dd->div1_mask);
046d6b28	227	div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
6b8858a9 PW	228	tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
6b8858a9 PW	229	tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28	230	if (rate > low) {
6b8858a9	231	tmpset.cm_clksel2_pll \|= CORE_CLK_SRC_DPLL_X2;
046d6b28	232	mult = ((rate / 2) / 1000000);
6b8858a9	233	done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28	234	} else {
6b8858a9	235	tmpset.cm_clksel2_pll \|= CORE_CLK_SRC_DPLL;
046d6b28	236	mult = (rate / 1000000);
6b8858a9	237	done_rate = CORE_CLK_SRC_DPLL;
046d6b28	238	}
6b8858a9 PW	239	tmpset.cm_clksel1_pll \|= (div << __ffs(dd->mult_mask));
6b8858a9 PW	240	tmpset.cm_clksel1_pll \|= (mult << __ffs(dd->div1_mask));
046d6b28 TL	241
046d6b28 TL	242	/* Worst case */
6b8858a9	243	tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
046d6b28 TL	244
	245	if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
	246	bypass = 1;
	247
6b8858a9	248	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
046d6b28 TL	249
	250	/* Force dll lock mode */
	251	omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
	252	bypass);
	253
	254	/* Errata: ret dll entry state */
	255	omap2_init_memory_params(omap2_dll_force_needed());
	256	omap2_reprogram_sdrc(done_rate, 0);
	257	}
88b8ba90	258	omap2_dpllcore_recalc(&dpll_ck);
046d6b28 TL	259	ret = 0;
	260
	261	dpll_exit:
	262	local_irq_restore(flags);
	263	return(ret);
	264	}
	265
6b8858a9 PW	266	/**
	267	* omap2_table_mpu_recalc - just return the MPU speed
	268	* @clk: virt_prcm_set struct clk
	269	*
	270	* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
	271	*/
	272	static void omap2_table_mpu_recalc(struct clk *clk)
046d6b28 TL	273	{
	274	clk->rate = curr_prcm_set->mpu_speed;
	275	}
	276
	277	/*
	278	* Look for a rate equal or less than the target rate given a configuration set.
	279	*
	280	* What's not entirely clear is "which" field represents the key field.
	281	* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
	282	* just uses the ARM rates.
	283	*/
6b8858a9	284	static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
046d6b28	285	{
6b8858a9	286	struct prcm_config *ptr;
046d6b28 TL	287	long highest_rate;
	288
	289	if (clk != &virt_prcm_set)
	290	return -EINVAL;
	291
	292	highest_rate = -EINVAL;
	293
	294	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
6b8858a9 PW	295	if (!(ptr->flags & cpu_mask))
6b8858a9 PW	296	continue;
046d6b28 TL	297	if (ptr->xtal_speed != sys_ck.rate)
	298	continue;
	299
	300	highest_rate = ptr->mpu_speed;
	301
	302	/* Can check only after xtal frequency check */
	303	if (ptr->mpu_speed <= rate)
	304	break;
	305	}
	306	return highest_rate;
	307	}
	308
046d6b28	309	/* Sets basic clocks based on the specified rate */
6b8858a9	310	static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
046d6b28	311	{
6b8858a9	312	u32 cur_rate, done_rate, bypass = 0, tmp;
046d6b28 TL	313	struct prcm_config *prcm;
046d6b28 TL	314	unsigned long found_speed = 0;
6b8858a9	315	unsigned long flags;
046d6b28 TL	316
	317	if (clk != &virt_prcm_set)
	318	return -EINVAL;
	319
046d6b28 TL	320	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
	321	if (!(prcm->flags & cpu_mask))
	322	continue;
	323
	324	if (prcm->xtal_speed != sys_ck.rate)
	325	continue;
	326
	327	if (prcm->mpu_speed <= rate) {
	328	found_speed = prcm->mpu_speed;
	329	break;
	330	}
	331	}
	332
	333	if (!found_speed) {
	334	printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
a16e9703	335	rate / 1000000);
046d6b28 TL	336	return -EINVAL;
	337	}
	338
	339	curr_prcm_set = prcm;
6b8858a9	340	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
046d6b28 TL	341
046d6b28 TL	342	if (prcm->dpll_speed == cur_rate / 2) {
6b8858a9	343	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
046d6b28	344	} else if (prcm->dpll_speed == cur_rate * 2) {
6b8858a9	345	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28 TL	346	} else if (prcm->dpll_speed != cur_rate) {
	347	local_irq_save(flags);
	348
	349	if (prcm->dpll_speed == prcm->xtal_speed)
	350	bypass = 1;
	351
6b8858a9 PW	352	if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
	353	CORE_CLK_SRC_DPLL_X2)
	354	done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28	355	else
6b8858a9	356	done_rate = CORE_CLK_SRC_DPLL;
046d6b28 TL	357
046d6b28 TL	358	/* MPU divider */
6b8858a9	359	cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
046d6b28 TL	360
046d6b28 TL	361	/* dsp + iva1 div(2420), iva2.1(2430) */
6b8858a9 PW	362	cm_write_mod_reg(prcm->cm_clksel_dsp,
6b8858a9 PW	363	OMAP24XX_DSP_MOD, CM_CLKSEL);
046d6b28	364
6b8858a9	365	cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
046d6b28 TL	366
046d6b28 TL	367	/* Major subsystem dividers */
6b8858a9 PW	368	tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
6b8858a9 PW	369	cm_write_mod_reg(prcm->cm_clksel1_core \| tmp, CORE_MOD, CM_CLKSEL1);
046d6b28	370	if (cpu_is_omap2430())
6b8858a9 PW	371	cm_write_mod_reg(prcm->cm_clksel_mdm,
6b8858a9 PW	372	OMAP2430_MDM_MOD, CM_CLKSEL);
046d6b28 TL	373
046d6b28 TL	374	/* x2 to enter init_mem */
6b8858a9	375	omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28 TL	376
	377	omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
	378	bypass);
	379
	380	omap2_init_memory_params(omap2_dll_force_needed());
	381	omap2_reprogram_sdrc(done_rate, 0);
	382
	383	local_irq_restore(flags);
	384	}
88b8ba90	385	omap2_dpllcore_recalc(&dpll_ck);
046d6b28 TL	386
	387	return 0;
	388	}
	389
046d6b28 TL	390	static struct clk_functions omap2_clk_functions = {
	391	.clk_enable = omap2_clk_enable,
	392	.clk_disable = omap2_clk_disable,
046d6b28 TL	393	.clk_round_rate = omap2_clk_round_rate,
	394	.clk_set_rate = omap2_clk_set_rate,
	395	.clk_set_parent = omap2_clk_set_parent,
90afd5cb	396	.clk_disable_unused = omap2_clk_disable_unused,
046d6b28 TL	397	};
046d6b28 TL	398
6b8858a9	399	static u32 omap2_get_apll_clkin(void)
046d6b28	400	{
6b8858a9	401	u32 aplls, sclk = 0;
046d6b28	402
6b8858a9 PW	403	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
	404	aplls &= OMAP24XX_APLLS_CLKIN_MASK;
	405	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
046d6b28	406
6b8858a9	407	if (aplls == APLLS_CLKIN_19_2MHZ)
046d6b28	408	sclk = 19200000;
6b8858a9	409	else if (aplls == APLLS_CLKIN_13MHZ)
046d6b28	410	sclk = 13000000;
6b8858a9	411	else if (aplls == APLLS_CLKIN_12MHZ)
046d6b28 TL	412	sclk = 12000000;
046d6b28 TL	413
6b8858a9 PW	414	return sclk;
	415	}
	416
	417	static u32 omap2_get_sysclkdiv(void)
	418	{
	419	u32 div;
	420
	421	div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
	422	div &= OMAP_SYSCLKDIV_MASK;
	423	div >>= OMAP_SYSCLKDIV_SHIFT;
046d6b28	424
6b8858a9 PW	425	return div;
	426	}
	427
	428	static void omap2_osc_clk_recalc(struct clk *clk)
	429	{
	430	clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
	431	propagate_rate(clk);
	432	}
	433
	434	static void omap2_sys_clk_recalc(struct clk *clk)
	435	{
	436	clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
	437	propagate_rate(clk);
046d6b28 TL	438	}
046d6b28 TL	439
ae78dcf7 TL	440	/*
	441	* Set clocks for bypass mode for reboot to work.
	442	*/
	443	void omap2_clk_prepare_for_reboot(void)
	444	{
	445	u32 rate;
	446
	447	if (vclk == NULL \|\| sclk == NULL)
	448	return;
	449
	450	rate = clk_get_rate(sclk);
	451	clk_set_rate(vclk, rate);
	452	}
	453
046d6b28 TL	454	/*
	455	* Switch the MPU rate if specified on cmdline.
	456	* We cannot do this early until cmdline is parsed.
	457	*/
	458	static int __init omap2_clk_arch_init(void)
	459	{
	460	if (!mpurate)
	461	return -EINVAL;
	462
	463	if (omap2_select_table_rate(&virt_prcm_set, mpurate))
	464	printk(KERN_ERR "Could not find matching MPU rate\n");
	465
6b8858a9	466	recalculate_root_clocks();
046d6b28 TL	467
	468	printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
	469	"%ld.%01ld/%ld/%ld MHz\n",
	470	(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
	471	(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
	472
	473	return 0;
	474	}
	475	arch_initcall(omap2_clk_arch_init);
	476
	477	int __init omap2_clk_init(void)
	478	{
	479	struct prcm_config *prcm;
6b8858a9	480	struct clk **clkp;
046d6b28 TL	481	u32 clkrate;
046d6b28 TL	482
6b8858a9 PW	483	if (cpu_is_omap242x())
	484	cpu_mask = RATE_IN_242X;
	485	else if (cpu_is_omap2430())
	486	cpu_mask = RATE_IN_243X;
	487
046d6b28	488	clk_init(&omap2_clk_functions);
046d6b28	489
6b8858a9 PW	490	omap2_osc_clk_recalc(&osc_ck);
	491	omap2_sys_clk_recalc(&sys_ck);
	492
	493	for (clkp = onchip_24xx_clks;
	494	clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
046d6b28 TL	495	clkp++) {
	496
	497	if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
	498	clk_register(*clkp);
	499	continue;
	500	}
	501
	502	if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
	503	clk_register(*clkp);
	504	continue;
	505	}
	506	}
	507
	508	/* Check the MPU rate set by bootloader */
6b8858a9	509	clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
046d6b28	510	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
6b8858a9 PW	511	if (!(prcm->flags & cpu_mask))
6b8858a9 PW	512	continue;
046d6b28 TL	513	if (prcm->xtal_speed != sys_ck.rate)
	514	continue;
	515	if (prcm->dpll_speed <= clkrate)
	516	break;
	517	}
	518	curr_prcm_set = prcm;
	519
6b8858a9	520	recalculate_root_clocks();
046d6b28 TL	521
	522	printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
	523	"%ld.%01ld/%ld/%ld MHz\n",
	524	(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
	525	(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
	526
	527	/*
	528	* Only enable those clocks we will need, let the drivers
	529	* enable other clocks as necessary
	530	*/
6b8858a9	531	clk_enable_init_clocks();
046d6b28	532
ae78dcf7 TL	533	/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
	534	vclk = clk_get(NULL, "virt_prcm_set");
	535	sclk = clk_get(NULL, "sys_ck");
	536
046d6b28 TL	537	return 0;
046d6b28 TL	538	}