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[ARM] omap: i2c: remove conditional ick clocks
[deliverable/linux.git] / arch / arm / mach-omap2 / clock34xx.c
CommitLineData
02e19a96
PW		 1/*
2 * OMAP3-specific clock framework functions
3 *
542313cc
PW		 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
02e19a96
PW		 6 *
7 * Written by Paul Walmsley
542313cc 8 * Testing and integration fixes by Jouni Högander
02e19a96
PW		 9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/device.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
542313cc 27#include <linux/limits.h>
fbd3bdb2 28#include <linux/bitops.h>
02e19a96 29
a09e64fb
RK		 30#include <mach/clock.h>
31#include <mach/sram.h>
02e19a96 32#include <asm/div64.h>
44dc9d02 33#include <asm/clkdev.h>
02e19a96
PW		 34
35#include "memory.h"
36#include "clock.h"
02e19a96
PW		 37#include "prm.h"
38#include "prm-regbits-34xx.h"
39#include "cm.h"
40#include "cm-regbits-34xx.h"
41
548d8495
RK		 42static const struct clkops clkops_noncore_dpll_ops;
43
44#include "clock34xx.h"
45
44dc9d02
RK		 46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
140 CLK("mmci-omap-hs.2", "mmchs_fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "mmchs_fck", &mmchs2_fck, CK_343X),
142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
143 CLK("mmci-omap-hs.0", "mmchs_fck", &mmchs1_fck, CK_343X),
1d14de08
RK		 144 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
b820ce4e
RK		 147 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
44dc9d02 149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
1b5715ec
RK		 150 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
44dc9d02
RK		 154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
158 CLK(NULL, "hdq_fck", &hdq_fck, CK_343X),
159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
169 CLK("mmci-omap-hs.2", "mmchs_ick", &mmchs3_ick, CK_3430ES2),
170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
174 CLK("mmci-omap-hs.1", "mmchs_ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "mmchs_ick", &mmchs1_ick, CK_343X),
176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
177 CLK(NULL, "hdq_ick", &hdq_ick, CK_343X),
1b5715ec
RK		 178 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
1d14de08
RK		 182 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
44dc9d02
RK		 185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
b820ce4e
RK		 189 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
44dc9d02
RK		 191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
199 CLK(NULL, "rng_ick", &rng_ick, CK_343X),
200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
209 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
212 CLK(NULL, "usbhost_sar_fck", &usbhost_sar_fck, CK_3430ES2),
213 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
214 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
215 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
216 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
39a80c7f 217 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
44dc9d02
RK		 218 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
219 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
39a80c7f 220 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
44dc9d02
RK		 221 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
222 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
223 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
224 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
225 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
226 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
227 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
228 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
229 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
230 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
231 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
232 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
233 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
234 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
235 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
236 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
237 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
238 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
239 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
240 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
241 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
242 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
243 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
244 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
245 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
246 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
247 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
248 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
249 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
250 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
251 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
252 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
253 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
254 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
255 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
256 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
257 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
258 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
259 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
b820ce4e
RK		 260 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
261 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
262 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
263 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
264 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
265 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
44dc9d02
RK		 266 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
267 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
268 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
269 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
270 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
271 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
272 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
273 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
274 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
275 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
276 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
277 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
278};
279
542313cc
PW		 280/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
281#define DPLL_AUTOIDLE_DISABLE 0x0
282#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
283
284#define MAX_DPLL_WAIT_TRIES 1000000
02e19a96
PW		 285
286/**
287 * omap3_dpll_recalc - recalculate DPLL rate
288 * @clk: DPLL struct clk
289 *
290 * Recalculate and propagate the DPLL rate.
291 */
292static void omap3_dpll_recalc(struct clk *clk)
293{
294 clk->rate = omap2_get_dpll_rate(clk);
02e19a96
PW		 295}
296
542313cc
PW		 297/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
298static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
299{
300 const struct dpll_data *dd;
ad67ef68 301 u32 v;
542313cc
PW		 302
303 dd = clk->dpll_data;
304
ad67ef68
PW		 305 v = __raw_readl(dd->control_reg);
306 v &= ~dd->enable_mask;
307 v |= clken_bits << __ffs(dd->enable_mask);
308 __raw_writel(v, dd->control_reg);
542313cc
PW		 309}
310
311/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
312static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
313{
314 const struct dpll_data *dd;
315 int i = 0;
316 int ret = -EINVAL;
317 u32 idlest_mask;
318
319 dd = clk->dpll_data;
320
321 state <<= dd->idlest_bit;
322 idlest_mask = 1 << dd->idlest_bit;
323
ad67ef68 324 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
542313cc
PW		 325 i < MAX_DPLL_WAIT_TRIES) {
326 i++;
327 udelay(1);
328 }
329
330 if (i == MAX_DPLL_WAIT_TRIES) {
331 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
332 clk->name, (state) ? "locked" : "bypassed");
333 } else {
334 pr_debug("clock: %s transition to '%s' in %d loops\n",
335 clk->name, (state) ? "locked" : "bypassed", i);
336
337 ret = 0;
338 }
339
340 return ret;
341}
342
343/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
344
345/*
346 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
347 * @clk: pointer to a DPLL struct clk
348 *
349 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
350 * readiness before returning. Will save and restore the DPLL's
351 * autoidle state across the enable, per the CDP code. If the DPLL
352 * locked successfully, return 0; if the DPLL did not lock in the time
353 * allotted, or DPLL3 was passed in, return -EINVAL.
354 */
355static int _omap3_noncore_dpll_lock(struct clk *clk)
356{
357 u8 ai;
358 int r;
359
360 if (clk == &dpll3_ck)
361 return -EINVAL;
362
363 pr_debug("clock: locking DPLL %s\n", clk->name);
364
365 ai = omap3_dpll_autoidle_read(clk);
366
367 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
368
369 if (ai) {
370 /*
371 * If no downstream clocks are enabled, CM_IDLEST bit
372 * may never become active, so don't wait for DPLL to lock.
373 */
374 r = 0;
375 omap3_dpll_allow_idle(clk);
376 } else {
377 r = _omap3_wait_dpll_status(clk, 1);
378 omap3_dpll_deny_idle(clk);
379 };
380
381 return r;
382}
383
384/*
385 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
386 * @clk: pointer to a DPLL struct clk
387 *
388 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
389 * bypass mode, the DPLL's rate is set equal to its parent clock's
390 * rate. Waits for the DPLL to report readiness before returning.
391 * Will save and restore the DPLL's autoidle state across the enable,
392 * per the CDP code. If the DPLL entered bypass mode successfully,
393 * return 0; if the DPLL did not enter bypass in the time allotted, or
394 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
395 * return -EINVAL.
396 */
397static int _omap3_noncore_dpll_bypass(struct clk *clk)
398{
399 int r;
400 u8 ai;
401
402 if (clk == &dpll3_ck)
403 return -EINVAL;
404
405 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
406 return -EINVAL;
407
408 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
409 clk->name);
410
411 ai = omap3_dpll_autoidle_read(clk);
412
413 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
414
415 r = _omap3_wait_dpll_status(clk, 0);
416
417 if (ai)
418 omap3_dpll_allow_idle(clk);
419 else
420 omap3_dpll_deny_idle(clk);
421
422 return r;
423}
424
425/*
426 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
427 * @clk: pointer to a DPLL struct clk
428 *
429 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
430 * restore the DPLL's autoidle state across the stop, per the CDP
431 * code. If DPLL3 was passed in, or the DPLL does not support
432 * low-power stop, return -EINVAL; otherwise, return 0.
433 */
434static int _omap3_noncore_dpll_stop(struct clk *clk)
435{
436 u8 ai;
437
438 if (clk == &dpll3_ck)
439 return -EINVAL;
440
441 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
442 return -EINVAL;
443
444 pr_debug("clock: stopping DPLL %s\n", clk->name);
445
446 ai = omap3_dpll_autoidle_read(clk);
447
448 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
449
450 if (ai)
451 omap3_dpll_allow_idle(clk);
452 else
453 omap3_dpll_deny_idle(clk);
454
455 return 0;
456}
457
458/**
459 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
460 * @clk: pointer to a DPLL struct clk
461 *
462 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
463 * The choice of modes depends on the DPLL's programmed rate: if it is
464 * the same as the DPLL's parent clock, it will enter bypass;
465 * otherwise, it will enter lock. This code will wait for the DPLL to
466 * indicate readiness before returning, unless the DPLL takes too long
467 * to enter the target state. Intended to be used as the struct clk's
468 * enable function. If DPLL3 was passed in, or the DPLL does not
469 * support low-power stop, or if the DPLL took too long to enter
470 * bypass or lock, return -EINVAL; otherwise, return 0.
471 */
472static int omap3_noncore_dpll_enable(struct clk *clk)
473{
474 int r;
475
476 if (clk == &dpll3_ck)
477 return -EINVAL;
478
479 if (clk->parent->rate == clk_get_rate(clk))
480 r = _omap3_noncore_dpll_bypass(clk);
481 else
482 r = _omap3_noncore_dpll_lock(clk);
483
484 return r;
485}
486
487/**
488 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
489 * @clk: pointer to a DPLL struct clk
490 *
491 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
492 * The choice of modes depends on the DPLL's programmed rate: if it is
493 * the same as the DPLL's parent clock, it will enter bypass;
494 * otherwise, it will enter lock. This code will wait for the DPLL to
495 * indicate readiness before returning, unless the DPLL takes too long
496 * to enter the target state. Intended to be used as the struct clk's
497 * enable function. If DPLL3 was passed in, or the DPLL does not
498 * support low-power stop, or if the DPLL took too long to enter
499 * bypass or lock, return -EINVAL; otherwise, return 0.
500 */
501static void omap3_noncore_dpll_disable(struct clk *clk)
502{
503 if (clk == &dpll3_ck)
504 return;
505
506 _omap3_noncore_dpll_stop(clk);
507}
508
548d8495
RK		 509static const struct clkops clkops_noncore_dpll_ops = {
510 .enable = &omap3_noncore_dpll_enable,
511 .disable = &omap3_noncore_dpll_disable,
512};
513
542313cc
PW		 514/**
515 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
516 * @clk: struct clk * of the DPLL to read
517 *
518 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
519 * -EINVAL if passed a null pointer or if the struct clk does not
520 * appear to refer to a DPLL.
521 */
522static u32 omap3_dpll_autoidle_read(struct clk *clk)
523{
524 const struct dpll_data *dd;
525 u32 v;
526
527 if (!clk || !clk->dpll_data)
528 return -EINVAL;
529
530 dd = clk->dpll_data;
531
ad67ef68 532 v = __raw_readl(dd->autoidle_reg);
542313cc
PW		 533 v &= dd->autoidle_mask;
534 v >>= __ffs(dd->autoidle_mask);
535
536 return v;
537}
538
539/**
540 * omap3_dpll_allow_idle - enable DPLL autoidle bits
541 * @clk: struct clk * of the DPLL to operate on
542 *
543 * Enable DPLL automatic idle control. This automatic idle mode
544 * switching takes effect only when the DPLL is locked, at least on
545 * OMAP3430. The DPLL will enter low-power stop when its downstream
546 * clocks are gated. No return value.
547 */
548static void omap3_dpll_allow_idle(struct clk *clk)
549{
550 const struct dpll_data *dd;
ad67ef68 551 u32 v;
542313cc
PW		 552
553 if (!clk || !clk->dpll_data)
554 return;
555
556 dd = clk->dpll_data;
557
558 /*
559 * REVISIT: CORE DPLL can optionally enter low-power bypass
560 * by writing 0x5 instead of 0x1. Add some mechanism to
561 * optionally enter this mode.
562 */
ad67ef68
PW		 563 v = __raw_readl(dd->autoidle_reg);
564 v &= ~dd->autoidle_mask;
565 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
566 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 567}
568
569/**
570 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
571 * @clk: struct clk * of the DPLL to operate on
572 *
573 * Disable DPLL automatic idle control. No return value.
574 */
575static void omap3_dpll_deny_idle(struct clk *clk)
576{
577 const struct dpll_data *dd;
ad67ef68 578 u32 v;
542313cc
PW		 579
580 if (!clk || !clk->dpll_data)
581 return;
582
583 dd = clk->dpll_data;
584
ad67ef68
PW		 585 v = __raw_readl(dd->autoidle_reg);
586 v &= ~dd->autoidle_mask;
587 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
588 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 589}
590
591/* Clock control for DPLL outputs */
592
02e19a96
PW		 593/**
594 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
595 * @clk: DPLL output struct clk
596 *
597 * Using parent clock DPLL data, look up DPLL state. If locked, set our
598 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
599 */
600static void omap3_clkoutx2_recalc(struct clk *clk)
601{
602 const struct dpll_data *dd;
603 u32 v;
604 struct clk *pclk;
605
606 /* Walk up the parents of clk, looking for a DPLL */
607 pclk = clk->parent;
608 while (pclk && !pclk->dpll_data)
609 pclk = pclk->parent;
610
611 /* clk does not have a DPLL as a parent? */
612 WARN_ON(!pclk);
613
614 dd = pclk->dpll_data;
615
616 WARN_ON(!dd->control_reg || !dd->enable_mask);
617
618 v = __raw_readl(dd->control_reg) & dd->enable_mask;
619 v >>= __ffs(dd->enable_mask);
620 if (v != DPLL_LOCKED)
621 clk->rate = clk->parent->rate;
622 else
623 clk->rate = clk->parent->rate * 2;
02e19a96
PW		 624}
625
542313cc
PW		 626/* Common clock code */
627
02e19a96
PW		 628/*
629 * As it is structured now, this will prevent an OMAP2/3 multiboot
630 * kernel from compiling. This will need further attention.
631 */
632#if defined(CONFIG_ARCH_OMAP3)
633
634static struct clk_functions omap2_clk_functions = {
635 .clk_enable = omap2_clk_enable,
636 .clk_disable = omap2_clk_disable,
637 .clk_round_rate = omap2_clk_round_rate,
638 .clk_set_rate = omap2_clk_set_rate,
639 .clk_set_parent = omap2_clk_set_parent,
640 .clk_disable_unused = omap2_clk_disable_unused,
641};
642
643/*
644 * Set clocks for bypass mode for reboot to work.
645 */
646void omap2_clk_prepare_for_reboot(void)
647{
648 /* REVISIT: Not ready for 343x */
649#if 0
650 u32 rate;
651
652 if (vclk == NULL || sclk == NULL)
653 return;
654
655 rate = clk_get_rate(sclk);
656 clk_set_rate(vclk, rate);
657#endif
658}
659
660/* REVISIT: Move this init stuff out into clock.c */
661
662/*
663 * Switch the MPU rate if specified on cmdline.
664 * We cannot do this early until cmdline is parsed.
665 */
666static int __init omap2_clk_arch_init(void)
667{
668 if (!mpurate)
669 return -EINVAL;
670
671 /* REVISIT: not yet ready for 343x */
672#if 0
673 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
674 printk(KERN_ERR "Could not find matching MPU rate\n");
675#endif
676
677 recalculate_root_clocks();
678
679 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
680 "%ld.%01ld/%ld/%ld MHz\n",
681 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
682 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
683
684 return 0;
685}
686arch_initcall(omap2_clk_arch_init);
687
688int __init omap2_clk_init(void)
689{
690 /* struct prcm_config *prcm; */
44dc9d02 691 struct omap_clk *c;
02e19a96
PW		 692 /* u32 clkrate; */
693 u32 cpu_clkflg;
694
02e19a96
PW		 695 if (cpu_is_omap34xx()) {
696 cpu_mask = RATE_IN_343X;
44dc9d02 697 cpu_clkflg = CK_343X;
02e19a96
PW		 698
699 /*
700 * Update this if there are further clock changes between ES2
701 * and production parts
702 */
84a34344 703 if (omap_rev() == OMAP3430_REV_ES1_0) {
02e19a96 704 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
44dc9d02 705 cpu_clkflg |= CK_3430ES1;
02e19a96
PW		 706 } else {
707 cpu_mask |= RATE_IN_3430ES2;
44dc9d02 708 cpu_clkflg |= CK_3430ES2;
02e19a96
PW		 709 }
710 }
711
712 clk_init(&omap2_clk_functions);
713
44dc9d02
RK		 714 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
715 if (c->cpu & cpu_clkflg) {
716 clkdev_add(&c->lk);
717 clk_register(c->lk.clk);
718 omap2_init_clk_clkdm(c->lk.clk);
333943ba 719 }
02e19a96
PW		 720
721 /* REVISIT: Not yet ready for OMAP3 */
722#if 0
723 /* Check the MPU rate set by bootloader */
724 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
725 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
726 if (!(prcm->flags & cpu_mask))
727 continue;
728 if (prcm->xtal_speed != sys_ck.rate)
729 continue;
730 if (prcm->dpll_speed <= clkrate)
731 break;
732 }
733 curr_prcm_set = prcm;
734#endif
735
736 recalculate_root_clocks();
737
3760d31f 738 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
02e19a96
PW		 739 "%ld.%01ld/%ld/%ld MHz\n",
740 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3760d31f 741 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
02e19a96
PW		 742
743 /*
744 * Only enable those clocks we will need, let the drivers
745 * enable other clocks as necessary
746 */
747 clk_enable_init_clocks();
748
749 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
750 /* REVISIT: not yet ready for 343x */
751#if 0
752 vclk = clk_get(NULL, "virt_prcm_set");
753 sclk = clk_get(NULL, "sys_ck");
754#endif
755 return 0;
756}
757
758#endif
Linux kernel - Deliverables
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