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02e19a96 PW |
1 | /* |
2 | * OMAP3-specific clock framework functions | |
3 | * | |
542313cc | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
3c82e229 | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
02e19a96 PW |
6 | * |
7 | * Written by Paul Walmsley | |
542313cc | 8 | * Testing and integration fixes by Jouni Högander |
02e19a96 PW |
9 | * |
10 | * Parts of this code are based on code written by | |
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | #undef DEBUG | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/io.h> | |
542313cc | 27 | #include <linux/limits.h> |
fbd3bdb2 | 28 | #include <linux/bitops.h> |
02e19a96 | 29 | |
ce491cf8 TL |
30 | #include <plat/cpu.h> |
31 | #include <plat/clock.h> | |
32 | #include <plat/sram.h> | |
02e19a96 | 33 | #include <asm/div64.h> |
44dc9d02 | 34 | #include <asm/clkdev.h> |
02e19a96 | 35 | |
ce491cf8 | 36 | #include <plat/sdrc.h> |
02e19a96 | 37 | #include "clock.h" |
02e19a96 PW |
38 | #include "prm.h" |
39 | #include "prm-regbits-34xx.h" | |
40 | #include "cm.h" | |
41 | #include "cm-regbits-34xx.h" | |
42 | ||
548d8495 RK |
43 | static const struct clkops clkops_noncore_dpll_ops; |
44 | ||
3c82e229 PW |
45 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, |
46 | void __iomem **idlest_reg, | |
47 | u8 *idlest_bit); | |
48 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | |
49 | void __iomem **idlest_reg, | |
50 | u8 *idlest_bit); | |
51 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |
52 | void __iomem **idlest_reg, | |
53 | u8 *idlest_bit); | |
54 | ||
55 | static const struct clkops clkops_omap3430es2_ssi_wait = { | |
56 | .enable = omap2_dflt_clk_enable, | |
57 | .disable = omap2_dflt_clk_disable, | |
58 | .find_idlest = omap3430es2_clk_ssi_find_idlest, | |
59 | .find_companion = omap2_clk_dflt_find_companion, | |
60 | }; | |
61 | ||
62 | static const struct clkops clkops_omap3430es2_hsotgusb_wait = { | |
63 | .enable = omap2_dflt_clk_enable, | |
64 | .disable = omap2_dflt_clk_disable, | |
65 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | |
66 | .find_companion = omap2_clk_dflt_find_companion, | |
67 | }; | |
68 | ||
69 | static const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | |
70 | .enable = omap2_dflt_clk_enable, | |
71 | .disable = omap2_dflt_clk_disable, | |
72 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, | |
73 | .find_companion = omap2_clk_dflt_find_companion, | |
74 | }; | |
75 | ||
548d8495 RK |
76 | #include "clock34xx.h" |
77 | ||
44dc9d02 RK |
78 | struct omap_clk { |
79 | u32 cpu; | |
80 | struct clk_lookup lk; | |
81 | }; | |
82 | ||
83 | #define CLK(dev, con, ck, cp) \ | |
84 | { \ | |
85 | .cpu = cp, \ | |
86 | .lk = { \ | |
87 | .dev_id = dev, \ | |
88 | .con_id = con, \ | |
89 | .clk = ck, \ | |
90 | }, \ | |
91 | } | |
92 | ||
93 | #define CK_343X (1 << 0) | |
94 | #define CK_3430ES1 (1 << 1) | |
95 | #define CK_3430ES2 (1 << 2) | |
96 | ||
97 | static struct omap_clk omap34xx_clks[] = { | |
98 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | |
99 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | |
100 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | |
101 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | |
102 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | |
103 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | |
104 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | |
105 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | |
106 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | |
107 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | |
108 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | |
109 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | |
110 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | |
111 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | |
112 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | |
113 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | |
114 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | |
115 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | |
116 | CLK(NULL, "core_ck", &core_ck, CK_343X), | |
117 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | |
118 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | |
119 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | |
120 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | |
121 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | |
183bd50f | 122 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), |
44dc9d02 RK |
123 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), |
124 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | |
125 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | |
126 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | |
127 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | |
44dc9d02 RK |
128 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), |
129 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | |
130 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | |
131 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | |
132 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | |
133 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | |
134 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | |
135 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | |
136 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | |
137 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | |
138 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | |
139 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | |
140 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | |
183bd50f | 141 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), |
44dc9d02 RK |
142 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), |
143 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | |
44dc9d02 RK |
144 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), |
145 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | |
146 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | |
147 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | |
148 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | |
149 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | |
183bd50f | 150 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), |
44dc9d02 RK |
151 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), |
152 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | |
153 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | |
154 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | |
155 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | |
156 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | |
157 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | |
158 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | |
159 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | |
160 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | |
161 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | |
162 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | |
163 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | |
8111b221 KH |
164 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), |
165 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | |
166 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | |
44dc9d02 RK |
167 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), |
168 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | |
169 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | |
170 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | |
171 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | |
172 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | |
6f7607cc RK |
173 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), |
174 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | |
44dc9d02 | 175 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), |
6f7607cc | 176 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), |
1d14de08 RK |
177 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), |
178 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | |
179 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | |
b820ce4e RK |
180 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), |
181 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | |
44dc9d02 | 182 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), |
1b5715ec RK |
183 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), |
184 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | |
185 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | |
186 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | |
44dc9d02 RK |
187 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), |
188 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | |
189 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | |
190 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | |
cc51c9d4 | 191 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), |
3c82e229 PW |
192 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), |
193 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | |
194 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | |
195 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | |
44dc9d02 | 196 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), |
3c82e229 PW |
197 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
198 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | |
44dc9d02 RK |
199 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), |
200 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | |
201 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | |
202 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | |
203 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | |
204 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | |
6f7607cc | 205 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), |
44dc9d02 RK |
206 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), |
207 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | |
208 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | |
209 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | |
6f7607cc RK |
210 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), |
211 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | |
44dc9d02 | 212 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), |
cc51c9d4 | 213 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), |
1b5715ec RK |
214 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), |
215 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | |
216 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | |
217 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | |
1d14de08 RK |
218 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), |
219 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | |
220 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | |
44dc9d02 RK |
221 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), |
222 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | |
223 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | |
224 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | |
b820ce4e RK |
225 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), |
226 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | |
44dc9d02 RK |
227 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), |
228 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | |
229 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | |
230 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | |
3c82e229 PW |
231 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), |
232 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | |
44dc9d02 RK |
233 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), |
234 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | |
235 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | |
eeec7c8d | 236 | CLK("omap_rng", "ick", &rng_ick, CK_343X), |
44dc9d02 RK |
237 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), |
238 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | |
dadd2bb9 TV |
239 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), |
240 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | |
241 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | |
242 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | |
243 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | |
244 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | |
245 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | |
44dc9d02 RK |
246 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), |
247 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | |
6c8fe0b9 | 248 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), |
44dc9d02 RK |
249 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), |
250 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | |
251 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | |
44dc9d02 RK |
252 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), |
253 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | |
254 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | |
255 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | |
39a80c7f | 256 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), |
44dc9d02 RK |
257 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), |
258 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | |
39a80c7f | 259 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), |
44dc9d02 RK |
260 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), |
261 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | |
262 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | |
263 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | |
264 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | |
265 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | |
266 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | |
267 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | |
268 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | |
269 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | |
270 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | |
271 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | |
272 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | |
273 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | |
274 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | |
275 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | |
276 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | |
277 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | |
278 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | |
279 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | |
280 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | |
281 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | |
282 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | |
283 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | |
284 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | |
285 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | |
286 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | |
287 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | |
288 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | |
289 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | |
290 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | |
291 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | |
292 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | |
293 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | |
294 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | |
295 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | |
296 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | |
297 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | |
298 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | |
b820ce4e RK |
299 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), |
300 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | |
301 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | |
302 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | |
303 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | |
304 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | |
183bd50f | 305 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), |
44dc9d02 RK |
306 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), |
307 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | |
308 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | |
309 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | |
310 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | |
311 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | |
312 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | |
313 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | |
314 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | |
315 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | |
316 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | |
317 | }; | |
318 | ||
542313cc PW |
319 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
320 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
321 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
322 | ||
323 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
02e19a96 | 324 | |
c9812d04 PW |
325 | #define CYCLES_PER_MHZ 1000000 |
326 | ||
7a66a39b RN |
327 | /* |
328 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | |
329 | * that are sourced by DPLL5, and both of these require this clock | |
330 | * to be at 120 MHz for proper operation. | |
331 | */ | |
332 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | |
333 | ||
3c82e229 PW |
334 | /** |
335 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI | |
336 | * @clk: struct clk * being enabled | |
337 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | |
338 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | |
339 | * | |
340 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift | |
341 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via | |
342 | * @idlest_reg and @idlest_bit. No return value. | |
343 | */ | |
344 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | |
345 | void __iomem **idlest_reg, | |
346 | u8 *idlest_bit) | |
347 | { | |
348 | u32 r; | |
349 | ||
350 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | |
351 | *idlest_reg = (__force void __iomem *)r; | |
352 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; | |
353 | } | |
354 | ||
355 | /** | |
356 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST | |
357 | * @clk: struct clk * being enabled | |
358 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | |
359 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | |
360 | * | |
361 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and | |
362 | * target IDLEST bits. For our purposes, we are concerned with the | |
363 | * target IDLEST bits, which exist at a different bit position than | |
364 | * the *CLKEN bit position for these modules (DSS and USBHOST) (The | |
365 | * default find_idlest code assumes that they are at the same | |
366 | * position.) No return value. | |
367 | */ | |
368 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |
369 | void __iomem **idlest_reg, | |
370 | u8 *idlest_bit) | |
371 | { | |
372 | u32 r; | |
373 | ||
374 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | |
375 | *idlest_reg = (__force void __iomem *)r; | |
376 | /* USBHOST_IDLE has same shift */ | |
377 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; | |
378 | } | |
379 | ||
380 | /** | |
381 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB | |
382 | * @clk: struct clk * being enabled | |
383 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | |
384 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | |
385 | * | |
386 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different | |
387 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via | |
388 | * @idlest_reg and @idlest_bit. No return value. | |
389 | */ | |
390 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | |
391 | void __iomem **idlest_reg, | |
392 | u8 *idlest_bit) | |
393 | { | |
394 | u32 r; | |
395 | ||
396 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | |
397 | *idlest_reg = (__force void __iomem *)r; | |
398 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; | |
399 | } | |
400 | ||
02e19a96 PW |
401 | /** |
402 | * omap3_dpll_recalc - recalculate DPLL rate | |
403 | * @clk: DPLL struct clk | |
404 | * | |
405 | * Recalculate and propagate the DPLL rate. | |
406 | */ | |
8b9dbc16 | 407 | static unsigned long omap3_dpll_recalc(struct clk *clk) |
02e19a96 | 408 | { |
8b9dbc16 | 409 | return omap2_get_dpll_rate(clk); |
02e19a96 PW |
410 | } |
411 | ||
542313cc PW |
412 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ |
413 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | |
414 | { | |
415 | const struct dpll_data *dd; | |
ad67ef68 | 416 | u32 v; |
542313cc PW |
417 | |
418 | dd = clk->dpll_data; | |
419 | ||
ad67ef68 PW |
420 | v = __raw_readl(dd->control_reg); |
421 | v &= ~dd->enable_mask; | |
422 | v |= clken_bits << __ffs(dd->enable_mask); | |
423 | __raw_writel(v, dd->control_reg); | |
542313cc PW |
424 | } |
425 | ||
426 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
427 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |
428 | { | |
429 | const struct dpll_data *dd; | |
430 | int i = 0; | |
431 | int ret = -EINVAL; | |
542313cc PW |
432 | |
433 | dd = clk->dpll_data; | |
434 | ||
c1bd7aaf | 435 | state <<= __ffs(dd->idlest_mask); |
542313cc | 436 | |
c1bd7aaf | 437 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && |
542313cc PW |
438 | i < MAX_DPLL_WAIT_TRIES) { |
439 | i++; | |
440 | udelay(1); | |
441 | } | |
442 | ||
443 | if (i == MAX_DPLL_WAIT_TRIES) { | |
444 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
445 | clk->name, (state) ? "locked" : "bypassed"); | |
446 | } else { | |
447 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
448 | clk->name, (state) ? "locked" : "bypassed", i); | |
449 | ||
450 | ret = 0; | |
451 | } | |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
16c90f02 PW |
456 | /* From 3430 TRM ES2 4.7.6.2 */ |
457 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |
458 | { | |
459 | unsigned long fint; | |
460 | u16 f = 0; | |
461 | ||
9346f48b | 462 | fint = clk->dpll_data->clk_ref->rate / n; |
16c90f02 PW |
463 | |
464 | pr_debug("clock: fint is %lu\n", fint); | |
465 | ||
466 | if (fint >= 750000 && fint <= 1000000) | |
467 | f = 0x3; | |
468 | else if (fint > 1000000 && fint <= 1250000) | |
469 | f = 0x4; | |
470 | else if (fint > 1250000 && fint <= 1500000) | |
471 | f = 0x5; | |
472 | else if (fint > 1500000 && fint <= 1750000) | |
473 | f = 0x6; | |
474 | else if (fint > 1750000 && fint <= 2100000) | |
475 | f = 0x7; | |
476 | else if (fint > 7500000 && fint <= 10000000) | |
477 | f = 0xB; | |
478 | else if (fint > 10000000 && fint <= 12500000) | |
479 | f = 0xC; | |
480 | else if (fint > 12500000 && fint <= 15000000) | |
481 | f = 0xD; | |
482 | else if (fint > 15000000 && fint <= 17500000) | |
483 | f = 0xE; | |
484 | else if (fint > 17500000 && fint <= 21000000) | |
485 | f = 0xF; | |
486 | else | |
487 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
488 | ||
489 | return f; | |
490 | } | |
491 | ||
542313cc PW |
492 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ |
493 | ||
494 | /* | |
495 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
496 | * @clk: pointer to a DPLL struct clk | |
497 | * | |
498 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
499 | * readiness before returning. Will save and restore the DPLL's | |
500 | * autoidle state across the enable, per the CDP code. If the DPLL | |
501 | * locked successfully, return 0; if the DPLL did not lock in the time | |
502 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
503 | */ | |
504 | static int _omap3_noncore_dpll_lock(struct clk *clk) | |
505 | { | |
506 | u8 ai; | |
507 | int r; | |
508 | ||
542313cc PW |
509 | pr_debug("clock: locking DPLL %s\n", clk->name); |
510 | ||
511 | ai = omap3_dpll_autoidle_read(clk); | |
512 | ||
416db864 PW |
513 | omap3_dpll_deny_idle(clk); |
514 | ||
542313cc PW |
515 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); |
516 | ||
416db864 PW |
517 | r = _omap3_wait_dpll_status(clk, 1); |
518 | ||
519 | if (ai) | |
542313cc | 520 | omap3_dpll_allow_idle(clk); |
542313cc PW |
521 | |
522 | return r; | |
523 | } | |
524 | ||
525 | /* | |
c0bf3132 | 526 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness |
542313cc PW |
527 | * @clk: pointer to a DPLL struct clk |
528 | * | |
529 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
530 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
531 | * rate. Waits for the DPLL to report readiness before returning. | |
532 | * Will save and restore the DPLL's autoidle state across the enable, | |
533 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
534 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
535 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
536 | * return -EINVAL. | |
537 | */ | |
538 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | |
539 | { | |
540 | int r; | |
541 | u8 ai; | |
542 | ||
542313cc PW |
543 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) |
544 | return -EINVAL; | |
545 | ||
546 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
547 | clk->name); | |
548 | ||
549 | ai = omap3_dpll_autoidle_read(clk); | |
550 | ||
551 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
552 | ||
553 | r = _omap3_wait_dpll_status(clk, 0); | |
554 | ||
555 | if (ai) | |
556 | omap3_dpll_allow_idle(clk); | |
557 | else | |
558 | omap3_dpll_deny_idle(clk); | |
559 | ||
560 | return r; | |
561 | } | |
562 | ||
563 | /* | |
564 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
565 | * @clk: pointer to a DPLL struct clk | |
566 | * | |
567 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
568 | * restore the DPLL's autoidle state across the stop, per the CDP | |
569 | * code. If DPLL3 was passed in, or the DPLL does not support | |
570 | * low-power stop, return -EINVAL; otherwise, return 0. | |
571 | */ | |
572 | static int _omap3_noncore_dpll_stop(struct clk *clk) | |
573 | { | |
574 | u8 ai; | |
575 | ||
542313cc PW |
576 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) |
577 | return -EINVAL; | |
578 | ||
579 | pr_debug("clock: stopping DPLL %s\n", clk->name); | |
580 | ||
581 | ai = omap3_dpll_autoidle_read(clk); | |
582 | ||
583 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
584 | ||
585 | if (ai) | |
586 | omap3_dpll_allow_idle(clk); | |
587 | else | |
588 | omap3_dpll_deny_idle(clk); | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | /** | |
594 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
595 | * @clk: pointer to a DPLL struct clk | |
596 | * | |
597 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
598 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
599 | * the same as the DPLL's parent clock, it will enter bypass; | |
600 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
601 | * indicate readiness before returning, unless the DPLL takes too long | |
602 | * to enter the target state. Intended to be used as the struct clk's | |
603 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
604 | * support low-power stop, or if the DPLL took too long to enter | |
605 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
606 | */ | |
607 | static int omap3_noncore_dpll_enable(struct clk *clk) | |
608 | { | |
609 | int r; | |
c0bf3132 | 610 | struct dpll_data *dd; |
542313cc | 611 | |
c0bf3132 RK |
612 | dd = clk->dpll_data; |
613 | if (!dd) | |
614 | return -EINVAL; | |
615 | ||
616 | if (clk->rate == dd->clk_bypass->rate) { | |
617 | WARN_ON(clk->parent != dd->clk_bypass); | |
542313cc | 618 | r = _omap3_noncore_dpll_bypass(clk); |
c0bf3132 RK |
619 | } else { |
620 | WARN_ON(clk->parent != dd->clk_ref); | |
542313cc | 621 | r = _omap3_noncore_dpll_lock(clk); |
c0bf3132 RK |
622 | } |
623 | /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ | |
624 | if (!r) | |
625 | clk->rate = omap2_get_dpll_rate(clk); | |
542313cc PW |
626 | |
627 | return r; | |
628 | } | |
629 | ||
630 | /** | |
631 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
632 | * @clk: pointer to a DPLL struct clk | |
633 | * | |
634 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
635 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
636 | * the same as the DPLL's parent clock, it will enter bypass; | |
637 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
638 | * indicate readiness before returning, unless the DPLL takes too long | |
639 | * to enter the target state. Intended to be used as the struct clk's | |
640 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
641 | * support low-power stop, or if the DPLL took too long to enter | |
642 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
643 | */ | |
644 | static void omap3_noncore_dpll_disable(struct clk *clk) | |
645 | { | |
542313cc PW |
646 | _omap3_noncore_dpll_stop(clk); |
647 | } | |
648 | ||
16c90f02 PW |
649 | |
650 | /* Non-CORE DPLL rate set code */ | |
651 | ||
652 | /* | |
653 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
654 | * @clk: struct clk * of DPLL to set | |
655 | * @m: DPLL multiplier to set | |
656 | * @n: DPLL divider to set | |
657 | * @freqsel: FREQSEL value to set | |
658 | * | |
659 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | |
660 | * lock.. Returns -EINVAL upon error, or 0 upon success. | |
661 | */ | |
662 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |
663 | { | |
664 | struct dpll_data *dd = clk->dpll_data; | |
665 | u32 v; | |
666 | ||
667 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
668 | _omap3_noncore_dpll_bypass(clk); | |
669 | ||
f0587b63 PW |
670 | /* Set jitter correction */ |
671 | v = __raw_readl(dd->control_reg); | |
672 | v &= ~dd->freqsel_mask; | |
673 | v |= freqsel << __ffs(dd->freqsel_mask); | |
674 | __raw_writel(v, dd->control_reg); | |
675 | ||
676 | /* Set DPLL multiplier, divider */ | |
16c90f02 PW |
677 | v = __raw_readl(dd->mult_div1_reg); |
678 | v &= ~(dd->mult_mask | dd->div1_mask); | |
16c90f02 | 679 | v |= m << __ffs(dd->mult_mask); |
f0587b63 | 680 | v |= (n - 1) << __ffs(dd->div1_mask); |
16c90f02 PW |
681 | __raw_writel(v, dd->mult_div1_reg); |
682 | ||
683 | /* We let the clock framework set the other output dividers later */ | |
684 | ||
685 | /* REVISIT: Set ramp-up delay? */ | |
686 | ||
687 | _omap3_noncore_dpll_lock(clk); | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | /** | |
693 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
694 | * @clk: struct clk * of DPLL to set | |
695 | * @rate: rounded target rate | |
696 | * | |
c0bf3132 RK |
697 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter |
698 | * low-power bypass, and the target rate is the bypass source clock | |
699 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
700 | * target rate if it hasn't been done already, then program and lock | |
701 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
16c90f02 PW |
702 | */ |
703 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |
704 | { | |
c0bf3132 | 705 | struct clk *new_parent = NULL; |
16c90f02 PW |
706 | u16 freqsel; |
707 | struct dpll_data *dd; | |
c0bf3132 | 708 | int ret; |
16c90f02 PW |
709 | |
710 | if (!clk || !rate) | |
711 | return -EINVAL; | |
712 | ||
713 | dd = clk->dpll_data; | |
714 | if (!dd) | |
715 | return -EINVAL; | |
716 | ||
717 | if (rate == omap2_get_dpll_rate(clk)) | |
718 | return 0; | |
719 | ||
c0bf3132 RK |
720 | /* |
721 | * Ensure both the bypass and ref clocks are enabled prior to | |
722 | * doing anything; we need the bypass clock running to reprogram | |
723 | * the DPLL. | |
724 | */ | |
725 | omap2_clk_enable(dd->clk_bypass); | |
726 | omap2_clk_enable(dd->clk_ref); | |
16c90f02 | 727 | |
c0bf3132 RK |
728 | if (dd->clk_bypass->rate == rate && |
729 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | |
730 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | |
731 | ||
732 | ret = _omap3_noncore_dpll_bypass(clk); | |
733 | if (!ret) | |
734 | new_parent = dd->clk_bypass; | |
735 | } else { | |
736 | if (dd->last_rounded_rate != rate) | |
737 | omap2_dpll_round_rate(clk, rate); | |
16c90f02 | 738 | |
c0bf3132 RK |
739 | if (dd->last_rounded_rate == 0) |
740 | return -EINVAL; | |
16c90f02 | 741 | |
c0bf3132 RK |
742 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); |
743 | if (!freqsel) | |
744 | WARN_ON(1); | |
745 | ||
746 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | |
747 | clk->name, rate); | |
748 | ||
749 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | |
750 | dd->last_rounded_n, freqsel); | |
751 | if (!ret) | |
752 | new_parent = dd->clk_ref; | |
753 | } | |
754 | if (!ret) { | |
755 | /* | |
756 | * Switch the parent clock in the heirarchy, and make sure | |
757 | * that the new parent's usecount is correct. Note: we | |
758 | * enable the new parent before disabling the old to avoid | |
759 | * any unnecessary hardware disable->enable transitions. | |
760 | */ | |
761 | if (clk->usecount) { | |
762 | omap2_clk_enable(new_parent); | |
763 | omap2_clk_disable(clk->parent); | |
764 | } | |
765 | clk_reparent(clk, new_parent); | |
766 | clk->rate = rate; | |
767 | } | |
768 | omap2_clk_disable(dd->clk_ref); | |
769 | omap2_clk_disable(dd->clk_bypass); | |
16c90f02 | 770 | |
16c90f02 PW |
771 | return 0; |
772 | } | |
773 | ||
774 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |
775 | { | |
776 | /* | |
777 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | |
778 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | |
779 | * on DPLL4. | |
780 | */ | |
781 | if (omap_rev() == OMAP3430_REV_ES1_0) { | |
782 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " | |
783 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | |
784 | return -EINVAL; | |
785 | } | |
786 | return omap3_noncore_dpll_set_rate(clk, rate); | |
787 | } | |
788 | ||
0eafd472 PW |
789 | |
790 | /* | |
791 | * CORE DPLL (DPLL3) rate programming functions | |
792 | * | |
793 | * These call into SRAM code to do the actual CM writes, since the SDRAM | |
794 | * is clocked from DPLL3. | |
795 | */ | |
796 | ||
797 | /** | |
798 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | |
799 | * @clk: struct clk * of DPLL to set | |
800 | * @rate: rounded target rate | |
801 | * | |
802 | * Program the DPLL M2 divider with the rounded target rate. Returns | |
803 | * -EINVAL upon error, or 0 upon success. | |
804 | */ | |
805 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |
806 | { | |
807 | u32 new_div = 0; | |
4519c2bf | 808 | u32 unlock_dll = 0; |
c9812d04 PW |
809 | u32 c; |
810 | unsigned long validrate, sdrcrate, mpurate; | |
58cda884 JP |
811 | struct omap_sdrc_params *sdrc_cs0; |
812 | struct omap_sdrc_params *sdrc_cs1; | |
813 | int ret; | |
0eafd472 PW |
814 | |
815 | if (!clk || !rate) | |
816 | return -EINVAL; | |
817 | ||
0eafd472 PW |
818 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
819 | if (validrate != rate) | |
820 | return -EINVAL; | |
821 | ||
822 | sdrcrate = sdrc_ick.rate; | |
823 | if (rate > clk->rate) | |
3afec633 | 824 | sdrcrate <<= ((rate / clk->rate) >> 1); |
0eafd472 | 825 | else |
3afec633 | 826 | sdrcrate >>= ((clk->rate / rate) >> 1); |
0eafd472 | 827 | |
58cda884 JP |
828 | ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); |
829 | if (ret) | |
0eafd472 PW |
830 | return -EINVAL; |
831 | ||
4519c2bf PW |
832 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { |
833 | pr_debug("clock: will unlock SDRC DLL\n"); | |
834 | unlock_dll = 1; | |
835 | } | |
836 | ||
c9812d04 PW |
837 | /* |
838 | * XXX This only needs to be done when the CPU frequency changes | |
839 | */ | |
840 | mpurate = arm_fck.rate / CYCLES_PER_MHZ; | |
841 | c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | |
842 | c += 1; /* for safety */ | |
843 | c *= SDRC_MPURATE_LOOPS; | |
844 | c >>= SDRC_MPURATE_SCALE; | |
845 | if (c == 0) | |
846 | c = 1; | |
847 | ||
b7aee4bf PW |
848 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, |
849 | validrate); | |
58cda884 JP |
850 | pr_debug("clock: SDRC CS0 timing params used:" |
851 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | |
852 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
853 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); | |
854 | if (sdrc_cs1) | |
855 | pr_debug("clock: SDRC CS1 timing params used: " | |
856 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | |
857 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | |
858 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | |
859 | ||
860 | if (sdrc_cs1) | |
861 | omap3_configure_core_dpll( | |
862 | new_div, unlock_dll, c, rate > clk->rate, | |
863 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
864 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | |
865 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | |
866 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | |
867 | else | |
868 | omap3_configure_core_dpll( | |
869 | new_div, unlock_dll, c, rate > clk->rate, | |
870 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
871 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | |
872 | 0, 0, 0, 0); | |
0eafd472 | 873 | |
0eafd472 PW |
874 | return 0; |
875 | } | |
876 | ||
877 | ||
548d8495 RK |
878 | static const struct clkops clkops_noncore_dpll_ops = { |
879 | .enable = &omap3_noncore_dpll_enable, | |
880 | .disable = &omap3_noncore_dpll_disable, | |
881 | }; | |
882 | ||
16c90f02 PW |
883 | /* DPLL autoidle read/set code */ |
884 | ||
885 | ||
542313cc PW |
886 | /** |
887 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
888 | * @clk: struct clk * of the DPLL to read | |
889 | * | |
890 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
891 | * -EINVAL if passed a null pointer or if the struct clk does not | |
892 | * appear to refer to a DPLL. | |
893 | */ | |
894 | static u32 omap3_dpll_autoidle_read(struct clk *clk) | |
895 | { | |
896 | const struct dpll_data *dd; | |
897 | u32 v; | |
898 | ||
899 | if (!clk || !clk->dpll_data) | |
900 | return -EINVAL; | |
901 | ||
902 | dd = clk->dpll_data; | |
903 | ||
ad67ef68 | 904 | v = __raw_readl(dd->autoidle_reg); |
542313cc PW |
905 | v &= dd->autoidle_mask; |
906 | v >>= __ffs(dd->autoidle_mask); | |
907 | ||
908 | return v; | |
909 | } | |
910 | ||
911 | /** | |
912 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
913 | * @clk: struct clk * of the DPLL to operate on | |
914 | * | |
915 | * Enable DPLL automatic idle control. This automatic idle mode | |
916 | * switching takes effect only when the DPLL is locked, at least on | |
917 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
918 | * clocks are gated. No return value. | |
919 | */ | |
920 | static void omap3_dpll_allow_idle(struct clk *clk) | |
921 | { | |
922 | const struct dpll_data *dd; | |
ad67ef68 | 923 | u32 v; |
542313cc PW |
924 | |
925 | if (!clk || !clk->dpll_data) | |
926 | return; | |
927 | ||
928 | dd = clk->dpll_data; | |
929 | ||
930 | /* | |
931 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
932 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
933 | * optionally enter this mode. | |
934 | */ | |
ad67ef68 PW |
935 | v = __raw_readl(dd->autoidle_reg); |
936 | v &= ~dd->autoidle_mask; | |
937 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
938 | __raw_writel(v, dd->autoidle_reg); | |
542313cc PW |
939 | } |
940 | ||
941 | /** | |
942 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
943 | * @clk: struct clk * of the DPLL to operate on | |
944 | * | |
945 | * Disable DPLL automatic idle control. No return value. | |
946 | */ | |
947 | static void omap3_dpll_deny_idle(struct clk *clk) | |
948 | { | |
949 | const struct dpll_data *dd; | |
ad67ef68 | 950 | u32 v; |
542313cc PW |
951 | |
952 | if (!clk || !clk->dpll_data) | |
953 | return; | |
954 | ||
955 | dd = clk->dpll_data; | |
956 | ||
ad67ef68 PW |
957 | v = __raw_readl(dd->autoidle_reg); |
958 | v &= ~dd->autoidle_mask; | |
959 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
960 | __raw_writel(v, dd->autoidle_reg); | |
542313cc PW |
961 | } |
962 | ||
963 | /* Clock control for DPLL outputs */ | |
964 | ||
02e19a96 PW |
965 | /** |
966 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
967 | * @clk: DPLL output struct clk | |
968 | * | |
969 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
970 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
971 | */ | |
8b9dbc16 | 972 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk) |
02e19a96 PW |
973 | { |
974 | const struct dpll_data *dd; | |
8b9dbc16 | 975 | unsigned long rate; |
02e19a96 PW |
976 | u32 v; |
977 | struct clk *pclk; | |
978 | ||
979 | /* Walk up the parents of clk, looking for a DPLL */ | |
980 | pclk = clk->parent; | |
981 | while (pclk && !pclk->dpll_data) | |
982 | pclk = pclk->parent; | |
983 | ||
984 | /* clk does not have a DPLL as a parent? */ | |
985 | WARN_ON(!pclk); | |
986 | ||
987 | dd = pclk->dpll_data; | |
988 | ||
c0bf3132 | 989 | WARN_ON(!dd->enable_mask); |
02e19a96 PW |
990 | |
991 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | |
992 | v >>= __ffs(dd->enable_mask); | |
c0bf3132 | 993 | if (v != OMAP3XXX_EN_DPLL_LOCKED) |
8b9dbc16 | 994 | rate = clk->parent->rate; |
02e19a96 | 995 | else |
8b9dbc16 RK |
996 | rate = clk->parent->rate * 2; |
997 | return rate; | |
02e19a96 PW |
998 | } |
999 | ||
542313cc PW |
1000 | /* Common clock code */ |
1001 | ||
02e19a96 PW |
1002 | /* |
1003 | * As it is structured now, this will prevent an OMAP2/3 multiboot | |
1004 | * kernel from compiling. This will need further attention. | |
1005 | */ | |
1006 | #if defined(CONFIG_ARCH_OMAP3) | |
1007 | ||
1008 | static struct clk_functions omap2_clk_functions = { | |
1009 | .clk_enable = omap2_clk_enable, | |
1010 | .clk_disable = omap2_clk_disable, | |
1011 | .clk_round_rate = omap2_clk_round_rate, | |
1012 | .clk_set_rate = omap2_clk_set_rate, | |
1013 | .clk_set_parent = omap2_clk_set_parent, | |
1014 | .clk_disable_unused = omap2_clk_disable_unused, | |
1015 | }; | |
1016 | ||
1017 | /* | |
1018 | * Set clocks for bypass mode for reboot to work. | |
1019 | */ | |
1020 | void omap2_clk_prepare_for_reboot(void) | |
1021 | { | |
1022 | /* REVISIT: Not ready for 343x */ | |
1023 | #if 0 | |
1024 | u32 rate; | |
1025 | ||
1026 | if (vclk == NULL || sclk == NULL) | |
1027 | return; | |
1028 | ||
1029 | rate = clk_get_rate(sclk); | |
1030 | clk_set_rate(vclk, rate); | |
1031 | #endif | |
1032 | } | |
1033 | ||
7a66a39b RN |
1034 | static void omap3_clk_lock_dpll5(void) |
1035 | { | |
1036 | struct clk *dpll5_clk; | |
1037 | struct clk *dpll5_m2_clk; | |
1038 | ||
1039 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | |
1040 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | |
1041 | clk_enable(dpll5_clk); | |
1042 | ||
1043 | /* Enable autoidle to allow it to enter low power bypass */ | |
1044 | omap3_dpll_allow_idle(dpll5_clk); | |
1045 | ||
1046 | /* Program dpll5_m2_clk divider for no division */ | |
1047 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | |
1048 | clk_enable(dpll5_m2_clk); | |
1049 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); | |
1050 | ||
1051 | clk_disable(dpll5_m2_clk); | |
1052 | clk_disable(dpll5_clk); | |
1053 | return; | |
1054 | } | |
1055 | ||
02e19a96 PW |
1056 | /* REVISIT: Move this init stuff out into clock.c */ |
1057 | ||
1058 | /* | |
1059 | * Switch the MPU rate if specified on cmdline. | |
1060 | * We cannot do this early until cmdline is parsed. | |
1061 | */ | |
1062 | static int __init omap2_clk_arch_init(void) | |
1063 | { | |
1064 | if (!mpurate) | |
1065 | return -EINVAL; | |
1066 | ||
1067 | /* REVISIT: not yet ready for 343x */ | |
11b66383 SP |
1068 | if (clk_set_rate(&dpll1_ck, mpurate)) |
1069 | printk(KERN_ERR "*** Unable to set MPU rate\n"); | |
02e19a96 PW |
1070 | |
1071 | recalculate_root_clocks(); | |
1072 | ||
11b66383 | 1073 | printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " |
02e19a96 | 1074 | "%ld.%01ld/%ld/%ld MHz\n", |
11b66383 SP |
1075 | (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), |
1076 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; | |
1077 | ||
1078 | calibrate_delay(); | |
02e19a96 PW |
1079 | |
1080 | return 0; | |
1081 | } | |
1082 | arch_initcall(omap2_clk_arch_init); | |
1083 | ||
1084 | int __init omap2_clk_init(void) | |
1085 | { | |
1086 | /* struct prcm_config *prcm; */ | |
44dc9d02 | 1087 | struct omap_clk *c; |
02e19a96 PW |
1088 | /* u32 clkrate; */ |
1089 | u32 cpu_clkflg; | |
1090 | ||
02e19a96 PW |
1091 | if (cpu_is_omap34xx()) { |
1092 | cpu_mask = RATE_IN_343X; | |
44dc9d02 | 1093 | cpu_clkflg = CK_343X; |
02e19a96 PW |
1094 | |
1095 | /* | |
1096 | * Update this if there are further clock changes between ES2 | |
1097 | * and production parts | |
1098 | */ | |
84a34344 | 1099 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
02e19a96 | 1100 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ |
44dc9d02 | 1101 | cpu_clkflg |= CK_3430ES1; |
02e19a96 PW |
1102 | } else { |
1103 | cpu_mask |= RATE_IN_3430ES2; | |
44dc9d02 | 1104 | cpu_clkflg |= CK_3430ES2; |
02e19a96 PW |
1105 | } |
1106 | } | |
1107 | ||
1108 | clk_init(&omap2_clk_functions); | |
1109 | ||
3f0a820c | 1110 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
79716870 | 1111 | clk_preinit(c->lk.clk); |
3f0a820c | 1112 | |
44dc9d02 RK |
1113 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
1114 | if (c->cpu & cpu_clkflg) { | |
1115 | clkdev_add(&c->lk); | |
1116 | clk_register(c->lk.clk); | |
1117 | omap2_init_clk_clkdm(c->lk.clk); | |
333943ba | 1118 | } |
02e19a96 PW |
1119 | |
1120 | /* REVISIT: Not yet ready for OMAP3 */ | |
1121 | #if 0 | |
1122 | /* Check the MPU rate set by bootloader */ | |
1123 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | |
1124 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
1125 | if (!(prcm->flags & cpu_mask)) | |
1126 | continue; | |
1127 | if (prcm->xtal_speed != sys_ck.rate) | |
1128 | continue; | |
1129 | if (prcm->dpll_speed <= clkrate) | |
1130 | break; | |
1131 | } | |
1132 | curr_prcm_set = prcm; | |
1133 | #endif | |
1134 | ||
1135 | recalculate_root_clocks(); | |
1136 | ||
11b66383 | 1137 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " |
02e19a96 PW |
1138 | "%ld.%01ld/%ld/%ld MHz\n", |
1139 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | |
3760d31f | 1140 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); |
02e19a96 PW |
1141 | |
1142 | /* | |
1143 | * Only enable those clocks we will need, let the drivers | |
1144 | * enable other clocks as necessary | |
1145 | */ | |
1146 | clk_enable_init_clocks(); | |
1147 | ||
7a66a39b RN |
1148 | /* |
1149 | * Lock DPLL5 and put it in autoidle. | |
1150 | */ | |
1151 | if (omap_rev() >= OMAP3430_REV_ES2_0) | |
1152 | omap3_clk_lock_dpll5(); | |
1153 | ||
02e19a96 PW |
1154 | /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ |
1155 | /* REVISIT: not yet ready for 343x */ | |
1156 | #if 0 | |
1157 | vclk = clk_get(NULL, "virt_prcm_set"); | |
1158 | sclk = clk_get(NULL, "sys_ck"); | |
1159 | #endif | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | #endif |