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[ARM] OMAP2/3 clock: don't tinker with hardirqs when they are supposed to be disabled
[deliverable/linux.git] / arch / arm / mach-omap2 / clock34xx.c
CommitLineData
02e19a96
PW		 1/*
2 * OMAP3-specific clock framework functions
3 *
542313cc
PW		 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
02e19a96
PW		 6 *
7 * Written by Paul Walmsley
542313cc 8 * Testing and integration fixes by Jouni Högander
02e19a96
PW		 9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/device.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
542313cc 27#include <linux/limits.h>
fbd3bdb2 28#include <linux/bitops.h>
02e19a96 29
a09e64fb
RK		 30#include <mach/clock.h>
31#include <mach/sram.h>
02e19a96 32#include <asm/div64.h>
44dc9d02 33#include <asm/clkdev.h>
02e19a96 34
f8de9b2c 35#include <mach/sdrc.h>
02e19a96 36#include "clock.h"
02e19a96
PW		 37#include "prm.h"
38#include "prm-regbits-34xx.h"
39#include "cm.h"
40#include "cm-regbits-34xx.h"
41
548d8495
RK		 42static const struct clkops clkops_noncore_dpll_ops;
43
44#include "clock34xx.h"
45
44dc9d02
RK		 46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
6f7607cc
RK		 140 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
44dc9d02 142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
6f7607cc 143 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
1d14de08
RK		 144 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
b820ce4e
RK		 147 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
44dc9d02 149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
1b5715ec
RK		 150 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
44dc9d02
RK		 154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
cc51c9d4 158 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
44dc9d02
RK		 159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
6f7607cc 169 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
44dc9d02
RK		 170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
6f7607cc
RK		 174 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
44dc9d02 176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
cc51c9d4 177 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
1b5715ec
RK		 178 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
1d14de08
RK		 182 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
44dc9d02
RK		 185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
b820ce4e
RK		 189 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
44dc9d02
RK		 191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
eeec7c8d 199 CLK("omap_rng", "ick", &rng_ick, CK_343X),
44dc9d02
RK		 200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
6c8fe0b9 209 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
44dc9d02
RK		 210 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
212 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
44dc9d02
RK		 213 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
214 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
215 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
216 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
39a80c7f 217 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
44dc9d02
RK		 218 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
219 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
39a80c7f 220 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
44dc9d02
RK		 221 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
222 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
223 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
224 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
225 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
226 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
227 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
228 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
229 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
230 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
231 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
232 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
233 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
234 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
235 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
236 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
237 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
238 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
239 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
240 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
241 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
242 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
243 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
244 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
245 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
246 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
247 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
248 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
249 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
250 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
251 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
252 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
253 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
254 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
255 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
256 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
257 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
258 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
259 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
b820ce4e
RK		 260 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
261 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
262 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
263 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
264 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
265 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
44dc9d02
RK		 266 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
267 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
268 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
269 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
270 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
271 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
272 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
273 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
274 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
275 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
276 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
277 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
278};
279
542313cc
PW		 280/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
281#define DPLL_AUTOIDLE_DISABLE 0x0
282#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
283
284#define MAX_DPLL_WAIT_TRIES 1000000
02e19a96
PW		 285
286/**
287 * omap3_dpll_recalc - recalculate DPLL rate
288 * @clk: DPLL struct clk
289 *
290 * Recalculate and propagate the DPLL rate.
291 */
292static void omap3_dpll_recalc(struct clk *clk)
293{
294 clk->rate = omap2_get_dpll_rate(clk);
02e19a96
PW		 295}
296
542313cc
PW		 297/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
298static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
299{
300 const struct dpll_data *dd;
ad67ef68 301 u32 v;
542313cc
PW		 302
303 dd = clk->dpll_data;
304
ad67ef68
PW		 305 v = __raw_readl(dd->control_reg);
306 v &= ~dd->enable_mask;
307 v |= clken_bits << __ffs(dd->enable_mask);
308 __raw_writel(v, dd->control_reg);
542313cc
PW		 309}
310
311/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
312static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
313{
314 const struct dpll_data *dd;
315 int i = 0;
316 int ret = -EINVAL;
542313cc
PW		 317
318 dd = clk->dpll_data;
319
c1bd7aaf 320 state <<= __ffs(dd->idlest_mask);
542313cc 321
c1bd7aaf 322 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
542313cc
PW		 323 i < MAX_DPLL_WAIT_TRIES) {
324 i++;
325 udelay(1);
326 }
327
328 if (i == MAX_DPLL_WAIT_TRIES) {
329 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
330 clk->name, (state) ? "locked" : "bypassed");
331 } else {
332 pr_debug("clock: %s transition to '%s' in %d loops\n",
333 clk->name, (state) ? "locked" : "bypassed", i);
334
335 ret = 0;
336 }
337
338 return ret;
339}
340
16c90f02
PW		 341/* From 3430 TRM ES2 4.7.6.2 */
342static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
343{
344 unsigned long fint;
345 u16 f = 0;
346
347 fint = clk->parent->rate / (n + 1);
348
349 pr_debug("clock: fint is %lu\n", fint);
350
351 if (fint >= 750000 && fint <= 1000000)
352 f = 0x3;
353 else if (fint > 1000000 && fint <= 1250000)
354 f = 0x4;
355 else if (fint > 1250000 && fint <= 1500000)
356 f = 0x5;
357 else if (fint > 1500000 && fint <= 1750000)
358 f = 0x6;
359 else if (fint > 1750000 && fint <= 2100000)
360 f = 0x7;
361 else if (fint > 7500000 && fint <= 10000000)
362 f = 0xB;
363 else if (fint > 10000000 && fint <= 12500000)
364 f = 0xC;
365 else if (fint > 12500000 && fint <= 15000000)
366 f = 0xD;
367 else if (fint > 15000000 && fint <= 17500000)
368 f = 0xE;
369 else if (fint > 17500000 && fint <= 21000000)
370 f = 0xF;
371 else
372 pr_debug("clock: unknown freqsel setting for %d\n", n);
373
374 return f;
375}
376
542313cc
PW		 377/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
378
379/*
380 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
381 * @clk: pointer to a DPLL struct clk
382 *
383 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
384 * readiness before returning. Will save and restore the DPLL's
385 * autoidle state across the enable, per the CDP code. If the DPLL
386 * locked successfully, return 0; if the DPLL did not lock in the time
387 * allotted, or DPLL3 was passed in, return -EINVAL.
388 */
389static int _omap3_noncore_dpll_lock(struct clk *clk)
390{
391 u8 ai;
392 int r;
393
394 if (clk == &dpll3_ck)
395 return -EINVAL;
396
397 pr_debug("clock: locking DPLL %s\n", clk->name);
398
399 ai = omap3_dpll_autoidle_read(clk);
400
416db864
PW		 401 omap3_dpll_deny_idle(clk);
402
542313cc
PW		 403 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
404
416db864
PW		 405 r = _omap3_wait_dpll_status(clk, 1);
406
407 if (ai)
542313cc 408 omap3_dpll_allow_idle(clk);
542313cc
PW		 409
410 return r;
411}
412
413/*
414 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
415 * @clk: pointer to a DPLL struct clk
416 *
417 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
418 * bypass mode, the DPLL's rate is set equal to its parent clock's
419 * rate. Waits for the DPLL to report readiness before returning.
420 * Will save and restore the DPLL's autoidle state across the enable,
421 * per the CDP code. If the DPLL entered bypass mode successfully,
422 * return 0; if the DPLL did not enter bypass in the time allotted, or
423 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
424 * return -EINVAL.
425 */
426static int _omap3_noncore_dpll_bypass(struct clk *clk)
427{
428 int r;
429 u8 ai;
430
431 if (clk == &dpll3_ck)
432 return -EINVAL;
433
434 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
435 return -EINVAL;
436
437 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
438 clk->name);
439
440 ai = omap3_dpll_autoidle_read(clk);
441
442 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
443
444 r = _omap3_wait_dpll_status(clk, 0);
445
446 if (ai)
447 omap3_dpll_allow_idle(clk);
448 else
449 omap3_dpll_deny_idle(clk);
450
451 return r;
452}
453
454/*
455 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
456 * @clk: pointer to a DPLL struct clk
457 *
458 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
459 * restore the DPLL's autoidle state across the stop, per the CDP
460 * code. If DPLL3 was passed in, or the DPLL does not support
461 * low-power stop, return -EINVAL; otherwise, return 0.
462 */
463static int _omap3_noncore_dpll_stop(struct clk *clk)
464{
465 u8 ai;
466
467 if (clk == &dpll3_ck)
468 return -EINVAL;
469
470 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
471 return -EINVAL;
472
473 pr_debug("clock: stopping DPLL %s\n", clk->name);
474
475 ai = omap3_dpll_autoidle_read(clk);
476
477 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
478
479 if (ai)
480 omap3_dpll_allow_idle(clk);
481 else
482 omap3_dpll_deny_idle(clk);
483
484 return 0;
485}
486
487/**
488 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
489 * @clk: pointer to a DPLL struct clk
490 *
491 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
492 * The choice of modes depends on the DPLL's programmed rate: if it is
493 * the same as the DPLL's parent clock, it will enter bypass;
494 * otherwise, it will enter lock. This code will wait for the DPLL to
495 * indicate readiness before returning, unless the DPLL takes too long
496 * to enter the target state. Intended to be used as the struct clk's
497 * enable function. If DPLL3 was passed in, or the DPLL does not
498 * support low-power stop, or if the DPLL took too long to enter
499 * bypass or lock, return -EINVAL; otherwise, return 0.
500 */
501static int omap3_noncore_dpll_enable(struct clk *clk)
502{
503 int r;
504
505 if (clk == &dpll3_ck)
506 return -EINVAL;
507
16c90f02 508 if (clk->parent->rate == omap2_get_dpll_rate(clk))
542313cc
PW		 509 r = _omap3_noncore_dpll_bypass(clk);
510 else
511 r = _omap3_noncore_dpll_lock(clk);
512
513 return r;
514}
515
516/**
517 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
518 * @clk: pointer to a DPLL struct clk
519 *
520 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
521 * The choice of modes depends on the DPLL's programmed rate: if it is
522 * the same as the DPLL's parent clock, it will enter bypass;
523 * otherwise, it will enter lock. This code will wait for the DPLL to
524 * indicate readiness before returning, unless the DPLL takes too long
525 * to enter the target state. Intended to be used as the struct clk's
526 * enable function. If DPLL3 was passed in, or the DPLL does not
527 * support low-power stop, or if the DPLL took too long to enter
528 * bypass or lock, return -EINVAL; otherwise, return 0.
529 */
530static void omap3_noncore_dpll_disable(struct clk *clk)
531{
532 if (clk == &dpll3_ck)
533 return;
534
535 _omap3_noncore_dpll_stop(clk);
536}
537
16c90f02
PW		 538
539/* Non-CORE DPLL rate set code */
540
541/*
542 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
543 * @clk: struct clk * of DPLL to set
544 * @m: DPLL multiplier to set
545 * @n: DPLL divider to set
546 * @freqsel: FREQSEL value to set
547 *
548 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
549 * lock.. Returns -EINVAL upon error, or 0 upon success.
550 */
551static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
552{
553 struct dpll_data *dd = clk->dpll_data;
554 u32 v;
555
556 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
557 _omap3_noncore_dpll_bypass(clk);
558
f0587b63
PW		 559 /* Set jitter correction */
560 v = __raw_readl(dd->control_reg);
561 v &= ~dd->freqsel_mask;
562 v |= freqsel << __ffs(dd->freqsel_mask);
563 __raw_writel(v, dd->control_reg);
564
565 /* Set DPLL multiplier, divider */
16c90f02
PW		 566 v = __raw_readl(dd->mult_div1_reg);
567 v &= ~(dd->mult_mask | dd->div1_mask);
16c90f02 568 v |= m << __ffs(dd->mult_mask);
f0587b63 569 v |= (n - 1) << __ffs(dd->div1_mask);
16c90f02
PW		 570 __raw_writel(v, dd->mult_div1_reg);
571
572 /* We let the clock framework set the other output dividers later */
573
574 /* REVISIT: Set ramp-up delay? */
575
576 _omap3_noncore_dpll_lock(clk);
577
578 return 0;
579}
580
581/**
582 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
583 * @clk: struct clk * of DPLL to set
584 * @rate: rounded target rate
585 *
586 * Program the DPLL with the rounded target rate. Returns -EINVAL upon
587 * error, or 0 upon success.
588 */
589static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
590{
591 u16 freqsel;
592 struct dpll_data *dd;
593
594 if (!clk || !rate)
595 return -EINVAL;
596
597 dd = clk->dpll_data;
598 if (!dd)
599 return -EINVAL;
600
601 if (rate == omap2_get_dpll_rate(clk))
602 return 0;
603
604 if (dd->last_rounded_rate != rate)
605 omap2_dpll_round_rate(clk, rate);
606
607 if (dd->last_rounded_rate == 0)
608 return -EINVAL;
609
610 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
611 if (!freqsel)
612 WARN_ON(1);
613
614 omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
615 freqsel);
616
16c90f02
PW		 617 return 0;
618}
619
620static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
621{
622 /*
623 * According to the 12-5 CDP code from TI, "Limitation 2.5"
624 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
625 * on DPLL4.
626 */
627 if (omap_rev() == OMAP3430_REV_ES1_0) {
628 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
629 "silicon 'Limitation 2.5' on 3430ES1.\n");
630 return -EINVAL;
631 }
632 return omap3_noncore_dpll_set_rate(clk, rate);
633}
634
0eafd472
PW		 635
636/*
637 * CORE DPLL (DPLL3) rate programming functions
638 *
639 * These call into SRAM code to do the actual CM writes, since the SDRAM
640 * is clocked from DPLL3.
641 */
642
643/**
644 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
645 * @clk: struct clk * of DPLL to set
646 * @rate: rounded target rate
647 *
648 * Program the DPLL M2 divider with the rounded target rate. Returns
649 * -EINVAL upon error, or 0 upon success.
650 */
651static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
652{
653 u32 new_div = 0;
654 unsigned long validrate, sdrcrate;
655 struct omap_sdrc_params *sp;
656
657 if (!clk || !rate)
658 return -EINVAL;
659
660 if (clk != &dpll3_m2_ck)
661 return -EINVAL;
662
663 if (rate == clk->rate)
664 return 0;
665
666 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
667 if (validrate != rate)
668 return -EINVAL;
669
670 sdrcrate = sdrc_ick.rate;
671 if (rate > clk->rate)
672 sdrcrate <<= ((rate / clk->rate) - 1);
673 else
674 sdrcrate >>= ((clk->rate / rate) - 1);
675
676 sp = omap2_sdrc_get_params(sdrcrate);
677 if (!sp)
678 return -EINVAL;
679
680 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
681 validrate);
682 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
683 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
684
685 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
686 WARN_ON(new_div != 1 && new_div != 2);
687
688 /* REVISIT: Add SDRC_MR changing to this code also */
0eafd472
PW		 689 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
690 sp->actim_ctrlb, new_div);
0eafd472 691
0eafd472
PW		 692 return 0;
693}
694
695
548d8495
RK		 696static const struct clkops clkops_noncore_dpll_ops = {
697 .enable = &omap3_noncore_dpll_enable,
698 .disable = &omap3_noncore_dpll_disable,
699};
700
16c90f02
PW		 701/* DPLL autoidle read/set code */
702
703
542313cc
PW		 704/**
705 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
706 * @clk: struct clk * of the DPLL to read
707 *
708 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
709 * -EINVAL if passed a null pointer or if the struct clk does not
710 * appear to refer to a DPLL.
711 */
712static u32 omap3_dpll_autoidle_read(struct clk *clk)
713{
714 const struct dpll_data *dd;
715 u32 v;
716
717 if (!clk || !clk->dpll_data)
718 return -EINVAL;
719
720 dd = clk->dpll_data;
721
ad67ef68 722 v = __raw_readl(dd->autoidle_reg);
542313cc
PW		 723 v &= dd->autoidle_mask;
724 v >>= __ffs(dd->autoidle_mask);
725
726 return v;
727}
728
729/**
730 * omap3_dpll_allow_idle - enable DPLL autoidle bits
731 * @clk: struct clk * of the DPLL to operate on
732 *
733 * Enable DPLL automatic idle control. This automatic idle mode
734 * switching takes effect only when the DPLL is locked, at least on
735 * OMAP3430. The DPLL will enter low-power stop when its downstream
736 * clocks are gated. No return value.
737 */
738static void omap3_dpll_allow_idle(struct clk *clk)
739{
740 const struct dpll_data *dd;
ad67ef68 741 u32 v;
542313cc
PW		 742
743 if (!clk || !clk->dpll_data)
744 return;
745
746 dd = clk->dpll_data;
747
748 /*
749 * REVISIT: CORE DPLL can optionally enter low-power bypass
750 * by writing 0x5 instead of 0x1. Add some mechanism to
751 * optionally enter this mode.
752 */
ad67ef68
PW		 753 v = __raw_readl(dd->autoidle_reg);
754 v &= ~dd->autoidle_mask;
755 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
756 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 757}
758
759/**
760 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
761 * @clk: struct clk * of the DPLL to operate on
762 *
763 * Disable DPLL automatic idle control. No return value.
764 */
765static void omap3_dpll_deny_idle(struct clk *clk)
766{
767 const struct dpll_data *dd;
ad67ef68 768 u32 v;
542313cc
PW		 769
770 if (!clk || !clk->dpll_data)
771 return;
772
773 dd = clk->dpll_data;
774
ad67ef68
PW		 775 v = __raw_readl(dd->autoidle_reg);
776 v &= ~dd->autoidle_mask;
777 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
778 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 779}
780
781/* Clock control for DPLL outputs */
782
02e19a96
PW		 783/**
784 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
785 * @clk: DPLL output struct clk
786 *
787 * Using parent clock DPLL data, look up DPLL state. If locked, set our
788 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
789 */
790static void omap3_clkoutx2_recalc(struct clk *clk)
791{
792 const struct dpll_data *dd;
793 u32 v;
794 struct clk *pclk;
795
796 /* Walk up the parents of clk, looking for a DPLL */
797 pclk = clk->parent;
798 while (pclk && !pclk->dpll_data)
799 pclk = pclk->parent;
800
801 /* clk does not have a DPLL as a parent? */
802 WARN_ON(!pclk);
803
804 dd = pclk->dpll_data;
805
806 WARN_ON(!dd->control_reg || !dd->enable_mask);
807
808 v = __raw_readl(dd->control_reg) & dd->enable_mask;
809 v >>= __ffs(dd->enable_mask);
810 if (v != DPLL_LOCKED)
811 clk->rate = clk->parent->rate;
812 else
813 clk->rate = clk->parent->rate * 2;
02e19a96
PW		 814}
815
542313cc
PW		 816/* Common clock code */
817
02e19a96
PW		 818/*
819 * As it is structured now, this will prevent an OMAP2/3 multiboot
820 * kernel from compiling. This will need further attention.
821 */
822#if defined(CONFIG_ARCH_OMAP3)
823
824static struct clk_functions omap2_clk_functions = {
825 .clk_enable = omap2_clk_enable,
826 .clk_disable = omap2_clk_disable,
827 .clk_round_rate = omap2_clk_round_rate,
828 .clk_set_rate = omap2_clk_set_rate,
829 .clk_set_parent = omap2_clk_set_parent,
830 .clk_disable_unused = omap2_clk_disable_unused,
831};
832
833/*
834 * Set clocks for bypass mode for reboot to work.
835 */
836void omap2_clk_prepare_for_reboot(void)
837{
838 /* REVISIT: Not ready for 343x */
839#if 0
840 u32 rate;
841
842 if (vclk == NULL || sclk == NULL)
843 return;
844
845 rate = clk_get_rate(sclk);
846 clk_set_rate(vclk, rate);
847#endif
848}
849
850/* REVISIT: Move this init stuff out into clock.c */
851
852/*
853 * Switch the MPU rate if specified on cmdline.
854 * We cannot do this early until cmdline is parsed.
855 */
856static int __init omap2_clk_arch_init(void)
857{
858 if (!mpurate)
859 return -EINVAL;
860
861 /* REVISIT: not yet ready for 343x */
862#if 0
7b0f89d7 863 if (clk_set_rate(&virt_prcm_set, mpurate))
02e19a96
PW		 864 printk(KERN_ERR "Could not find matching MPU rate\n");
865#endif
866
867 recalculate_root_clocks();
868
869 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
870 "%ld.%01ld/%ld/%ld MHz\n",
871 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
872 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
873
874 return 0;
875}
876arch_initcall(omap2_clk_arch_init);
877
878int __init omap2_clk_init(void)
879{
880 /* struct prcm_config *prcm; */
44dc9d02 881 struct omap_clk *c;
02e19a96
PW		 882 /* u32 clkrate; */
883 u32 cpu_clkflg;
884
02e19a96
PW		 885 if (cpu_is_omap34xx()) {
886 cpu_mask = RATE_IN_343X;
44dc9d02 887 cpu_clkflg = CK_343X;
02e19a96
PW		 888
889 /*
890 * Update this if there are further clock changes between ES2
891 * and production parts
892 */
84a34344 893 if (omap_rev() == OMAP3430_REV_ES1_0) {
02e19a96 894 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
44dc9d02 895 cpu_clkflg |= CK_3430ES1;
02e19a96
PW		 896 } else {
897 cpu_mask |= RATE_IN_3430ES2;
44dc9d02 898 cpu_clkflg |= CK_3430ES2;
02e19a96
PW		 899 }
900 }
901
902 clk_init(&omap2_clk_functions);
903
3f0a820c
RK		 904 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
905 clk_init_one(c->lk.clk);
906
44dc9d02
RK		 907 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
908 if (c->cpu & cpu_clkflg) {
909 clkdev_add(&c->lk);
910 clk_register(c->lk.clk);
911 omap2_init_clk_clkdm(c->lk.clk);
333943ba 912 }
02e19a96
PW		 913
914 /* REVISIT: Not yet ready for OMAP3 */
915#if 0
916 /* Check the MPU rate set by bootloader */
917 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
918 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
919 if (!(prcm->flags & cpu_mask))
920 continue;
921 if (prcm->xtal_speed != sys_ck.rate)
922 continue;
923 if (prcm->dpll_speed <= clkrate)
924 break;
925 }
926 curr_prcm_set = prcm;
927#endif
928
929 recalculate_root_clocks();
930
3760d31f 931 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
02e19a96
PW		 932 "%ld.%01ld/%ld/%ld MHz\n",
933 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3760d31f 934 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
02e19a96
PW		 935
936 /*
937 * Only enable those clocks we will need, let the drivers
938 * enable other clocks as necessary
939 */
940 clk_enable_init_clocks();
941
942 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
943 /* REVISIT: not yet ready for 343x */
944#if 0
945 vclk = clk_get(NULL, "virt_prcm_set");
946 sclk = clk_get(NULL, "sys_ck");
947#endif
948 return 0;
949}
950
951#endif
Linux kernel - Deliverables
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