projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d198b514 PW |
1 | /* |
| 2 | * OMAP44xx CM1 instance offset macros | |
| 3 | * | |
| ad98a18b | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
| d198b514 PW |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * | |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | * | |
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | |
| 22 | * or "OMAP4430". | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H | |
| 26 | #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H | |
| 27 | ||
| 19fa20d7 SS |
28 | #include "cm_44xx_54xx.h" |
| 29 | ||
| d198b514 PW |
30 | /* CM1 base address */ |
| 31 | #define OMAP4430_CM1_BASE 0x4a004000 | |
| 32 | ||
| cdb54c44 PW |
33 | #define OMAP44XX_CM1_REGADDR(inst, reg) \ |
| 34 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) | |
| d198b514 PW |
35 | |
| 36 | /* CM1 instances */ | |
| cdb54c44 PW |
37 | #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 |
| 38 | #define OMAP4430_CM1_CKGEN_INST 0x0100 | |
| 39 | #define OMAP4430_CM1_MPU_INST 0x0300 | |
| 40 | #define OMAP4430_CM1_TESLA_INST 0x0400 | |
| 41 | #define OMAP4430_CM1_ABE_INST 0x0500 | |
| 42 | #define OMAP4430_CM1_RESTORE_INST 0x0e00 | |
| 43 | #define OMAP4430_CM1_INSTR_INST 0x0f00 | |
| d198b514 | 44 | |
| e4156ee5 | 45 | /* CM1 clockdomain register offsets (from instance start) */ |
| ad98a18b BC |
46 | #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 |
| 47 | #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 | |
| 48 | #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 | |
| e4156ee5 | 49 | |
| d198b514 PW |
50 | /* CM1 */ |
| 51 | ||
| 52 | /* CM1.OCP_SOCKET_CM1 register offsets */ | |
| 53 | #define OMAP4_REVISION_CM1_OFFSET 0x0000 | |
| cdb54c44 | 54 | #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) |
| d198b514 | 55 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 56 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) |
| d198b514 PW |
57 | |
| 58 | /* CM1.CKGEN_CM1 register offsets */ | |
| 59 | #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 | |
| cdb54c44 | 60 | #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) |
| d198b514 | 61 | #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 |
| cdb54c44 | 62 | #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) |
| d198b514 | 63 | #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 |
| cdb54c44 | 64 | #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) |
| d198b514 | 65 | #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 |
| cdb54c44 | 66 | #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) |
| d198b514 | 67 | #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 |
| cdb54c44 | 68 | #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) |
| d198b514 | 69 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 |
| cdb54c44 | 70 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) |
| d198b514 | 71 | #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c |
| cdb54c44 | 72 | #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) |
| d198b514 | 73 | #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 |
| cdb54c44 | 74 | #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) |
| d198b514 | 75 | #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 |
| cdb54c44 | 76 | #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) |
| d198b514 | 77 | #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 |
| cdb54c44 | 78 | #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) |
| d198b514 | 79 | #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c |
| cdb54c44 | 80 | #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) |
| d198b514 | 81 | #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 |
| cdb54c44 | 82 | #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) |
| d198b514 | 83 | #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 |
| cdb54c44 | 84 | #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) |
| d198b514 | 85 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 |
| cdb54c44 | 86 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) |
| ad98a18b BC |
87 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c |
| 88 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) | |
| d198b514 | 89 | #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 |
| cdb54c44 | 90 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) |
| d198b514 | 91 | #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 |
| cdb54c44 | 92 | #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) |
| d198b514 | 93 | #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 |
| cdb54c44 | 94 | #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) |
| d198b514 | 95 | #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 |
| cdb54c44 | 96 | #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) |
| d198b514 | 97 | #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c |
| cdb54c44 | 98 | #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) |
| d198b514 | 99 | #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 |
| cdb54c44 | 100 | #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) |
| d198b514 | 101 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 |
| cdb54c44 | 102 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) |
| ad98a18b BC |
103 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c |
| 104 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) | |
| d198b514 | 105 | #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c |
| cdb54c44 | 106 | #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) |
| d198b514 | 107 | #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 |
| cdb54c44 | 108 | #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) |
| d198b514 | 109 | #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 |
| cdb54c44 | 110 | #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) |
| d198b514 | 111 | #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 |
| cdb54c44 | 112 | #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) |
| d198b514 | 113 | #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac |
| cdb54c44 | 114 | #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) |
| d198b514 | 115 | #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 |
| cdb54c44 | 116 | #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) |
| d198b514 | 117 | #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc |
| cdb54c44 | 118 | #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) |
| d198b514 | 119 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 |
| cdb54c44 | 120 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) |
| ad98a18b BC |
121 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc |
| 122 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) | |
| d198b514 | 123 | #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc |
| cdb54c44 | 124 | #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) |
| d198b514 | 125 | #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 |
| cdb54c44 | 126 | #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) |
| d198b514 | 127 | #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 |
| cdb54c44 | 128 | #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) |
| d198b514 | 129 | #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 |
| cdb54c44 | 130 | #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) |
| d198b514 | 131 | #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec |
| cdb54c44 | 132 | #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) |
| d198b514 | 133 | #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 |
| cdb54c44 | 134 | #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) |
| d198b514 | 135 | #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 |
| cdb54c44 | 136 | #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) |
| d198b514 | 137 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 |
| cdb54c44 | 138 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) |
| ad98a18b BC |
139 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c |
| 140 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) | |
| d198b514 | 141 | #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 |
| cdb54c44 | 142 | #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) |
| d198b514 | 143 | #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 |
| cdb54c44 | 144 | #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) |
| d198b514 | 145 | #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 |
| cdb54c44 | 146 | #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) |
| d198b514 | 147 | #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c |
| cdb54c44 | 148 | #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) |
| d198b514 | 149 | #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 |
| cdb54c44 | 150 | #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) |
| d198b514 | 151 | #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 |
| cdb54c44 | 152 | #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) |
| d198b514 | 153 | #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c |
| cdb54c44 | 154 | #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) |
| d198b514 | 155 | #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 |
| cdb54c44 | 156 | #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) |
| d198b514 | 157 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 |
| cdb54c44 | 158 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) |
| ad98a18b BC |
159 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c |
| 160 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) | |
| d198b514 | 161 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 |
| cdb54c44 | 162 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) |
| d198b514 | 163 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 |
| cdb54c44 | 164 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) |
| d198b514 | 165 | #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 |
| cdb54c44 | 166 | #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) |
| d198b514 | 167 | #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 |
| cdb54c44 | 168 | #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) |
| d198b514 PW |
169 | |
| 170 | /* CM1.MPU_CM1 register offsets */ | |
| 171 | #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 172 | #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) |
| d198b514 | 173 | #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 174 | #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) |
| d198b514 | 175 | #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 176 | #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) |
| d198b514 | 177 | #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 178 | #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) |
| d198b514 PW |
179 | |
| 180 | /* CM1.TESLA_CM1 register offsets */ | |
| 181 | #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 182 | #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) |
| d198b514 | 183 | #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 184 | #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) |
| d198b514 | 185 | #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 186 | #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) |
| d198b514 | 187 | #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 188 | #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) |
| d198b514 PW |
189 | |
| 190 | /* CM1.ABE_CM1 register offsets */ | |
| 191 | #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 192 | #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) |
| d198b514 | 193 | #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 194 | #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) |
| d198b514 | 195 | #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 196 | #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) |
| d198b514 | 197 | #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 |
| cdb54c44 | 198 | #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) |
| d198b514 | 199 | #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 |
| cdb54c44 | 200 | #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) |
| d198b514 | 201 | #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 202 | #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) |
| d198b514 | 203 | #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 |
| cdb54c44 | 204 | #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) |
| d198b514 | 205 | #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 |
| cdb54c44 | 206 | #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) |
| d198b514 | 207 | #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 |
| cdb54c44 | 208 | #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) |
| d198b514 | 209 | #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 |
| cdb54c44 | 210 | #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) |
| d198b514 | 211 | #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 |
| cdb54c44 | 212 | #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) |
| d198b514 | 213 | #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 |
| cdb54c44 | 214 | #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) |
| d198b514 | 215 | #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 |
| cdb54c44 | 216 | #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) |
| d198b514 | 217 | #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 |
| cdb54c44 | 218 | #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) |
| d198b514 | 219 | #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 |
| cdb54c44 | 220 | #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) |
| d198b514 | 221 | |
| d198b514 | 222 | #endif |