projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d198b514 PW |
1 | /* |
| 2 | * OMAP44xx CM2 instance offset macros | |
| 3 | * | |
| ad98a18b | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
| d198b514 PW |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * | |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | * | |
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | |
| 22 | * or "OMAP4430". | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H | |
| 26 | #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H | |
| 27 | ||
| 28 | /* CM2 base address */ | |
| 29 | #define OMAP4430_CM2_BASE 0x4a008000 | |
| 30 | ||
| cdb54c44 PW |
31 | #define OMAP44XX_CM2_REGADDR(inst, reg) \ |
| 32 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) | |
| d198b514 PW |
33 | |
| 34 | /* CM2 instances */ | |
| cdb54c44 PW |
35 | #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 |
| 36 | #define OMAP4430_CM2_CKGEN_INST 0x0100 | |
| 37 | #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 | |
| 38 | #define OMAP4430_CM2_CORE_INST 0x0700 | |
| 39 | #define OMAP4430_CM2_IVAHD_INST 0x0f00 | |
| 40 | #define OMAP4430_CM2_CAM_INST 0x1000 | |
| 41 | #define OMAP4430_CM2_DSS_INST 0x1100 | |
| 42 | #define OMAP4430_CM2_GFX_INST 0x1200 | |
| ad98a18b | 43 | #define OMAP4430_CM2_L3INIT_INST 0x1300 |
| cdb54c44 | 44 | #define OMAP4430_CM2_L4PER_INST 0x1400 |
| ad98a18b | 45 | #define OMAP4430_CM2_CEFUSE_INST 0x1600 |
| cdb54c44 PW |
46 | #define OMAP4430_CM2_RESTORE_INST 0x1e00 |
| 47 | #define OMAP4430_CM2_INSTR_INST 0x1f00 | |
| d198b514 | 48 | |
| e4156ee5 PW |
49 | /* CM2 clockdomain register offsets (from instance start) */ |
| 50 | #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 | |
| 51 | #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 | |
| 52 | #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 | |
| 53 | #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 | |
| 54 | #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 | |
| 55 | #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 | |
| 56 | #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 | |
| 57 | #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 | |
| 58 | #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 | |
| 59 | #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 | |
| 60 | #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 | |
| 61 | #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 | |
| 62 | #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 | |
| 63 | #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 | |
| 64 | #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 | |
| 65 | #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 | |
| 66 | #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 | |
| 67 | ||
| d198b514 PW |
68 | /* CM2 */ |
| 69 | ||
| 70 | /* CM2.OCP_SOCKET_CM2 register offsets */ | |
| 71 | #define OMAP4_REVISION_CM2_OFFSET 0x0000 | |
| cdb54c44 | 72 | #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) |
| d198b514 | 73 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 74 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) |
| d198b514 PW |
75 | |
| 76 | /* CM2.CKGEN_CM2 register offsets */ | |
| 77 | #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 | |
| cdb54c44 | 78 | #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) |
| d198b514 | 79 | #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 |
| cdb54c44 | 80 | #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) |
| d198b514 | 81 | #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 |
| cdb54c44 | 82 | #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) |
| d198b514 | 83 | #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 |
| cdb54c44 | 84 | #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) |
| d198b514 | 85 | #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 |
| cdb54c44 | 86 | #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) |
| d198b514 | 87 | #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 |
| cdb54c44 | 88 | #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) |
| d198b514 | 89 | #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c |
| cdb54c44 | 90 | #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) |
| d198b514 | 91 | #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 |
| cdb54c44 | 92 | #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) |
| d198b514 | 93 | #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 |
| cdb54c44 | 94 | #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) |
| d198b514 | 95 | #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c |
| cdb54c44 | 96 | #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) |
| d198b514 | 97 | #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 |
| cdb54c44 | 98 | #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) |
| d198b514 | 99 | #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 |
| cdb54c44 | 100 | #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) |
| d198b514 | 101 | #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 |
| cdb54c44 | 102 | #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) |
| d198b514 | 103 | #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 |
| cdb54c44 | 104 | #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) |
| d198b514 | 105 | #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 |
| cdb54c44 | 106 | #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) |
| d198b514 | 107 | #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c |
| cdb54c44 | 108 | #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) |
| d198b514 | 109 | #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 |
| cdb54c44 | 110 | #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) |
| d198b514 | 111 | #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 |
| cdb54c44 | 112 | #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) |
| d198b514 | 113 | #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 |
| cdb54c44 | 114 | #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) |
| d198b514 | 115 | #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c |
| cdb54c44 | 116 | #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) |
| d198b514 | 117 | #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 |
| cdb54c44 | 118 | #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) |
| d198b514 | 119 | #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 |
| cdb54c44 | 120 | #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) |
| d198b514 | 121 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 |
| cdb54c44 | 122 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) |
| ad98a18b BC |
123 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c |
| 124 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) | |
| d198b514 | 125 | #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 |
| cdb54c44 | 126 | #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) |
| d198b514 | 127 | #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 |
| cdb54c44 | 128 | #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) |
| d198b514 | 129 | #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 |
| cdb54c44 | 130 | #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) |
| d198b514 | 131 | #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c |
| cdb54c44 | 132 | #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) |
| d198b514 | 133 | #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 |
| cdb54c44 | 134 | #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) |
| d198b514 | 135 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 |
| cdb54c44 | 136 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) |
| ad98a18b BC |
137 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac |
| 138 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) | |
| d198b514 | 139 | #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 |
| cdb54c44 | 140 | #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) |
| d198b514 | 141 | #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 |
| cdb54c44 | 142 | #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) |
| d198b514 | 143 | #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 |
| cdb54c44 | 144 | #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) |
| d198b514 | 145 | #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 |
| cdb54c44 | 146 | #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) |
| d198b514 | 147 | #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc |
| cdb54c44 | 148 | #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) |
| d198b514 | 149 | #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 |
| cdb54c44 | 150 | #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) |
| d198b514 | 151 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 |
| cdb54c44 | 152 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) |
| ad98a18b BC |
153 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec |
| 154 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) | |
| d198b514 PW |
155 | |
| 156 | /* CM2.ALWAYS_ON_CM2 register offsets */ | |
| 157 | #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 158 | #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) |
| d198b514 | 159 | #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 160 | #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) |
| d198b514 | 161 | #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 162 | #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) |
| d198b514 | 163 | #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 |
| cdb54c44 | 164 | #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) |
| d198b514 | 165 | #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 |
| cdb54c44 | 166 | #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) |
| d198b514 | 167 | #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 168 | #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) |
| d198b514 PW |
169 | |
| 170 | /* CM2.CORE_CM2 register offsets */ | |
| 171 | #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 172 | #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) |
| d198b514 | 173 | #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 174 | #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) |
| d198b514 | 175 | #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 176 | #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) |
| d198b514 | 177 | #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 |
| cdb54c44 | 178 | #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) |
| d198b514 | 179 | #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 |
| cdb54c44 | 180 | #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) |
| d198b514 | 181 | #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 |
| cdb54c44 | 182 | #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) |
| d198b514 | 183 | #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 |
| cdb54c44 | 184 | #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) |
| d198b514 | 185 | #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 |
| cdb54c44 | 186 | #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) |
| d198b514 | 187 | #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 |
| cdb54c44 | 188 | #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) |
| d198b514 | 189 | #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 |
| cdb54c44 | 190 | #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) |
| d198b514 | 191 | #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 |
| cdb54c44 | 192 | #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) |
| d198b514 | 193 | #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 |
| cdb54c44 | 194 | #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) |
| d198b514 | 195 | #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 |
| cdb54c44 | 196 | #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) |
| d198b514 | 197 | #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 |
| cdb54c44 | 198 | #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) |
| d198b514 | 199 | #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 |
| cdb54c44 | 200 | #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) |
| d198b514 | 201 | #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 |
| cdb54c44 | 202 | #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) |
| d198b514 | 203 | #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 |
| cdb54c44 | 204 | #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) |
| d198b514 | 205 | #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 |
| cdb54c44 | 206 | #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) |
| d198b514 | 207 | #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 |
| cdb54c44 | 208 | #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) |
| d198b514 | 209 | #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 |
| cdb54c44 | 210 | #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) |
| d198b514 | 211 | #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 |
| cdb54c44 | 212 | #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) |
| d198b514 | 213 | #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 |
| cdb54c44 | 214 | #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) |
| d198b514 | 215 | #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 |
| cdb54c44 | 216 | #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) |
| d198b514 | 217 | #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 |
| cdb54c44 | 218 | #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) |
| d198b514 | 219 | #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 |
| cdb54c44 | 220 | #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) |
| d198b514 | 221 | #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 |
| cdb54c44 | 222 | #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) |
| d198b514 | 223 | #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 |
| cdb54c44 | 224 | #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) |
| d198b514 | 225 | #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 |
| cdb54c44 | 226 | #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) |
| d198b514 | 227 | #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 |
| cdb54c44 | 228 | #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) |
| ad98a18b BC |
229 | #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 |
| 230 | #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) | |
| d198b514 | 231 | #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 |
| cdb54c44 | 232 | #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) |
| d198b514 | 233 | #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 |
| cdb54c44 | 234 | #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) |
| d198b514 | 235 | #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 |
| cdb54c44 | 236 | #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) |
| d198b514 | 237 | #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 |
| cdb54c44 | 238 | #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) |
| d198b514 | 239 | #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 |
| cdb54c44 | 240 | #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) |
| d198b514 | 241 | #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 |
| cdb54c44 | 242 | #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) |
| d198b514 | 243 | #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 |
| cdb54c44 | 244 | #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) |
| d198b514 | 245 | #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 |
| cdb54c44 | 246 | #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) |
| d198b514 | 247 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 |
| cdb54c44 | 248 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) |
| d198b514 | 249 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 |
| cdb54c44 | 250 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) |
| d198b514 | 251 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 |
| cdb54c44 | 252 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) |
| d198b514 PW |
253 | |
| 254 | /* CM2.IVAHD_CM2 register offsets */ | |
| 255 | #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 256 | #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) |
| d198b514 | 257 | #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 258 | #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) |
| d198b514 | 259 | #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 260 | #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) |
| d198b514 | 261 | #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 262 | #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) |
| d198b514 | 263 | #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 264 | #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) |
| d198b514 PW |
265 | |
| 266 | /* CM2.CAM_CM2 register offsets */ | |
| 267 | #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 268 | #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) |
| d198b514 | 269 | #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 270 | #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) |
| d198b514 | 271 | #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 272 | #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) |
| d198b514 | 273 | #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 274 | #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) |
| d198b514 | 275 | #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 276 | #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) |
| d198b514 PW |
277 | |
| 278 | /* CM2.DSS_CM2 register offsets */ | |
| 279 | #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 280 | #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) |
| d198b514 | 281 | #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 282 | #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) |
| d198b514 | 283 | #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 284 | #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) |
| d198b514 | 285 | #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 286 | #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) |
| d198b514 | 287 | #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 288 | #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) |
| d198b514 PW |
289 | |
| 290 | /* CM2.GFX_CM2 register offsets */ | |
| 291 | #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 292 | #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) |
| d198b514 | 293 | #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 294 | #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) |
| d198b514 | 295 | #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 296 | #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) |
| d198b514 | 297 | #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 298 | #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) |
| d198b514 PW |
299 | |
| 300 | /* CM2.L3INIT_CM2 register offsets */ | |
| 301 | #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 302 | #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) |
| d198b514 | 303 | #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 |
| cdb54c44 | 304 | #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) |
| d198b514 | 305 | #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 306 | #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) |
| d198b514 | 307 | #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 308 | #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) |
| d198b514 | 309 | #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 |
| cdb54c44 | 310 | #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) |
| d198b514 | 311 | #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 |
| cdb54c44 | 312 | #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) |
| d198b514 | 313 | #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 314 | #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) |
| d198b514 | 315 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 |
| cdb54c44 | 316 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) |
| d198b514 | 317 | #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 |
| cdb54c44 | 318 | #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) |
| d198b514 | 319 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 |
| cdb54c44 | 320 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) |
| d198b514 | 321 | #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 |
| cdb54c44 | 322 | #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) |
| d198b514 | 323 | #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 |
| cdb54c44 | 324 | #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) |
| d198b514 | 325 | #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 |
| cdb54c44 | 326 | #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) |
| d198b514 | 327 | #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 |
| cdb54c44 | 328 | #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) |
| d198b514 | 329 | #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 |
| cdb54c44 | 330 | #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) |
| d198b514 | 331 | #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 |
| cdb54c44 | 332 | #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) |
| d198b514 | 333 | #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 |
| cdb54c44 | 334 | #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) |
| d198b514 | 335 | #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 |
| cdb54c44 | 336 | #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) |
| d198b514 | 337 | #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 |
| cdb54c44 | 338 | #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) |
| d198b514 | 339 | #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 |
| cdb54c44 | 340 | #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) |
| d198b514 PW |
341 | |
| 342 | /* CM2.L4PER_CM2 register offsets */ | |
| 343 | #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 344 | #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) |
| d198b514 | 345 | #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 |
| cdb54c44 | 346 | #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) |
| d198b514 | 347 | #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 348 | #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) |
| d198b514 | 349 | #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 |
| cdb54c44 | 350 | #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) |
| d198b514 | 351 | #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 |
| cdb54c44 | 352 | #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) |
| d198b514 | 353 | #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 |
| cdb54c44 | 354 | #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) |
| d198b514 | 355 | #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 |
| cdb54c44 | 356 | #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) |
| d198b514 | 357 | #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 |
| cdb54c44 | 358 | #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) |
| d198b514 | 359 | #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 |
| cdb54c44 | 360 | #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) |
| d198b514 | 361 | #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 |
| cdb54c44 | 362 | #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) |
| d198b514 | 363 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 |
| cdb54c44 | 364 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) |
| d198b514 | 365 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 |
| cdb54c44 | 366 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) |
| d198b514 | 367 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 |
| cdb54c44 | 368 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) |
| d198b514 | 369 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 |
| cdb54c44 | 370 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) |
| d198b514 | 371 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 |
| cdb54c44 | 372 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) |
| d198b514 | 373 | #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 |
| cdb54c44 | 374 | #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) |
| d198b514 | 375 | #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 |
| cdb54c44 | 376 | #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) |
| d198b514 | 377 | #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 |
| cdb54c44 | 378 | #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) |
| d198b514 | 379 | #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 |
| cdb54c44 | 380 | #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) |
| d198b514 | 381 | #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 |
| cdb54c44 | 382 | #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) |
| d198b514 | 383 | #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 |
| cdb54c44 | 384 | #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) |
| d198b514 | 385 | #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 |
| cdb54c44 | 386 | #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) |
| d198b514 | 387 | #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 |
| cdb54c44 | 388 | #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) |
| d198b514 | 389 | #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 |
| cdb54c44 | 390 | #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) |
| d198b514 | 391 | #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 |
| cdb54c44 | 392 | #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) |
| d198b514 | 393 | #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 |
| cdb54c44 | 394 | #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) |
| d198b514 | 395 | #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 |
| cdb54c44 | 396 | #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) |
| d198b514 | 397 | #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 |
| cdb54c44 | 398 | #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) |
| d198b514 | 399 | #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 |
| cdb54c44 | 400 | #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) |
| d198b514 | 401 | #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 |
| cdb54c44 | 402 | #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) |
| d198b514 | 403 | #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 |
| cdb54c44 | 404 | #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) |
| d198b514 | 405 | #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 |
| cdb54c44 | 406 | #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) |
| d198b514 | 407 | #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 |
| cdb54c44 | 408 | #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) |
| d198b514 | 409 | #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 |
| cdb54c44 | 410 | #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) |
| d198b514 | 411 | #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 |
| cdb54c44 | 412 | #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) |
| d198b514 | 413 | #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 |
| cdb54c44 | 414 | #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) |
| d198b514 | 415 | #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 |
| cdb54c44 | 416 | #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) |
| d198b514 | 417 | #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 |
| cdb54c44 | 418 | #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) |
| d198b514 | 419 | #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 |
| cdb54c44 | 420 | #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) |
| d198b514 | 421 | #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 |
| cdb54c44 | 422 | #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) |
| d198b514 | 423 | #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 |
| cdb54c44 | 424 | #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) |
| d198b514 | 425 | #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 |
| cdb54c44 | 426 | #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) |
| d198b514 | 427 | #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 |
| cdb54c44 | 428 | #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) |
| d198b514 | 429 | #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 |
| cdb54c44 | 430 | #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) |
| d198b514 | 431 | #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 |
| cdb54c44 | 432 | #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) |
| d198b514 | 433 | #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 |
| cdb54c44 | 434 | #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) |
| d198b514 | 435 | #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 |
| cdb54c44 | 436 | #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) |
| d198b514 | 437 | #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 |
| cdb54c44 | 438 | #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) |
| d198b514 | 439 | #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 |
| cdb54c44 | 440 | #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) |
| d198b514 | 441 | #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 |
| cdb54c44 | 442 | #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) |
| d198b514 | 443 | #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 |
| cdb54c44 | 444 | #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) |
| d198b514 PW |
445 | |
| 446 | /* CM2.CEFUSE_CM2 register offsets */ | |
| 447 | #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | |
| cdb54c44 | 448 | #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) |
| d198b514 | 449 | #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 |
| cdb54c44 | 450 | #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) |
| d198b514 | 451 | |
| d198b514 | 452 | #endif |