[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>

#include "pm.h"
#include "control.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
	u8 valid;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			struct cpuidle_state *state)
{
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(state);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (state == &dev->states[0]) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	/* Re-allow idle for C1 */
	if (state == &dev->states[0]) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
}

/**
 * next_valid_state - Find next valid c-state
 * @dev: cpuidle device
 * @state: Currently selected c-state
 *
 * If the current state is valid, it is returned back to the caller.
 * Else, this function searches for a lower c-state which is still
 * valid.
 */
static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
					      struct cpuidle_state *curr)
{
	struct cpuidle_state *next = NULL;
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr);

	/* Check if current state is valid */
	if (cx->valid) {
		return curr;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&dev->states[idx] == curr) {
				next = &dev->states[idx];
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next == NULL);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states[idx]);
			if (cx->valid) {
				next = &dev->states[idx];
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next==NULL' outside this loop.
		 */
	}

	return next;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_state *state)
{
	struct cpuidle_state *new_state;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	if (!omap3_can_sleep()) {
		new_state = dev->safe_state;
		goto select_state;
	}

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state = dev->safe_state;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(state);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state = next_valid_state(dev, state);

select_state:
	dev->last_state = new_state;
	ret = omap3_enter_idle(dev, new_state);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

/**
 * omap3_cpuidle_update_states() - Update the cpuidle states
 * @mpu_deepest_state:	Enable states up to and including this for mpu domain
 * @core_deepest_state:	Enable states up to and including this for core domain
 *
 * This goes through the list of states available and enables and disables the
 * validity of C states based on deepest state that can be achieved for the
 * variable domain
 */
void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
	int i;

	for (i = 0; i < OMAP3_NUM_STATES; i++) {
		struct omap3_idle_statedata *cx = &omap3_idle_data[i];

		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			cx->valid = 1;
		} else {
			cx->valid = 0;
		}
	}
}

void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
{
	int i;

	if (!cpuidle_board_params)
		return;

	for (i = 0; i < OMAP3_NUM_STATES; i++) {
		cpuidle_params_table[i].valid =	cpuidle_board_params[i].valid;
		cpuidle_params_table[i].exit_latency =
			cpuidle_board_params[i].exit_latency;
		cpuidle_params_table[i].target_residency =
			cpuidle_board_params[i].target_residency;
	}
	return;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/* Helper to fill the C-state common data and register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate(
					struct cpuidle_device *dev,
					int idx, const char *descr)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state *state = &dev->states[idx];

	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
	state->target_residency	= cpuidle_params_table[idx].target_residency;
	state->flags		= CPUIDLE_FLAG_TIME_VALID;
	state->enter		= omap3_enter_idle_bm;
	cx->valid		= cpuidle_params_table[idx].valid;
	sprintf(state->name, "C%d", idx + 1);
	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
	cpuidle_set_statedata(state, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	cpuidle_register_driver(&omap3_idle_driver);
	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
	(&dev->states[0])->enter = omap3_enter_idle;
	dev->safe_state = &dev->states[0];
	cx->valid = 1;	/* C1 is always valid */
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
	/*
	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	 * enable OFF mode in a stable form for previous revisions.
	 * We disable C7 state as a result.
	 */
	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
		cx->valid = 0;
		pr_warn("%s: core off state C7 disabled due to i583\n",
			__func__);
	}
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	if (enable_off_mode)
		omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
	else
		omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);

	dev->state_count = OMAP3_NUM_STATES;
	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2 RN	26	#include <linux/cpuidle.h>
	27
	28	#include <plat/prcm.h>
20b01669	29	#include <plat/irqs.h>
72e06d08	30	#include "powerdomain.h"
1540f214	31	#include "clockdomain.h"
0f724ed9	32	#include <plat/serial.h>
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
c98e2230	36
99e6a4d2 RN	37	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	38
bb4de3df KH	39	/*
	40	* The latencies/thresholds for various C states have
	41	* to be configured from the respective board files.
	42	* These are some default values (which might not provide
	43	* the best power savings) used on boards which do not
	44	* pass these details from the board file.
	45	*/
	46	static struct cpuidle_params cpuidle_params_table[] = {
	47	/* C1 */
866ba0ef	48	{2 + 2, 5, 1},
bb4de3df	49	/* C2 */
866ba0ef	50	{10 + 10, 30, 1},
bb4de3df	51	/* C3 */
866ba0ef	52	{50 + 50, 300, 1},
bb4de3df	53	/* C4 */
866ba0ef	54	{1500 + 1800, 4000, 1},
bb4de3df	55	/* C5 */
866ba0ef	56	{2500 + 7500, 12000, 1},
bb4de3df	57	/* C6 */
866ba0ef	58	{3000 + 8500, 15000, 1},
bb4de3df	59	/* C7 */
866ba0ef	60	{10000 + 30000, 300000, 1},
bb4de3df	61	};
badc303a JP	62	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	63
	64	/* Mach specific information to be recorded in the C-state driver_data */
	65	struct omap3_idle_statedata {
	66	u32 mpu_state;
	67	u32 core_state;
	68	u8 valid;
	69	};
	70	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	71
	72	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	73
06d8f065 PDS	74	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	75	struct clockdomain *clkdm)
	76	{
5cd1937b	77	clkdm_allow_idle(clkdm);
06d8f065 PDS	78	return 0;
	79	}
	80
	81	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	82	struct clockdomain *clkdm)
	83	{
5cd1937b	84	clkdm_deny_idle(clkdm);
06d8f065 PDS	85	return 0;
	86	}
	87
99e6a4d2 RN	88	/**
	89	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	90	* @dev: cpuidle device
	91	* @state: The target state to be programmed
	92	*
	93	* Called from the CPUidle framework to program the device to the
	94	* specified target state selected by the governor.
	95	*/
	96	static int omap3_enter_idle(struct cpuidle_device *dev,
	97	struct cpuidle_state *state)
	98	{
badc303a	99	struct omap3_idle_statedata *cx = cpuidle_get_statedata(state);
99e6a4d2	100	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	101	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	102
99e6a4d2 RN	103	/* Used to keep track of the total time in idle */
	104	getnstimeofday(&ts_preidle);
	105
	106	local_irq_disable();
	107	local_fiq_disable();
	108
7139178e JH	109	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	110	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	111
cf22854c	112	if (omap_irq_pending() \|\| need_resched())
20b01669	113	goto return_sleep_time;
99e6a4d2	114
badc303a JP	115	/* Deny idle for C1 */
badc303a JP	116	if (state == &dev->states[0]) {
06d8f065 PDS	117	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	118	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	119	}
	120
99e6a4d2 RN	121	/* Execute ARM wfi */
	122	omap_sram_idle();
	123
badc303a JP	124	/* Re-allow idle for C1 */
badc303a JP	125	if (state == &dev->states[0]) {
06d8f065 PDS	126	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	127	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	128	}
	129
20b01669	130	return_sleep_time:
99e6a4d2 RN	131	getnstimeofday(&ts_postidle);
	132	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	133
	134	local_irq_enable();
	135	local_fiq_enable();
	136
afbcf619	137	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
99e6a4d2 RN	138	}
99e6a4d2 RN	139
6af83b38 SP	140	/**
	141	* next_valid_state - Find next valid c-state
	142	* @dev: cpuidle device
	143	* @state: Currently selected c-state
	144	*
	145	* If the current state is valid, it is returned back to the caller.
	146	* Else, this function searches for a lower c-state which is still
badc303a	147	* valid.
6af83b38 SP	148	*/
6af83b38 SP	149	static struct cpuidle_state next_valid_state(struct cpuidle_device dev,
badc303a	150	struct cpuidle_state *curr)
6af83b38 SP	151	{
6af83b38 SP	152	struct cpuidle_state *next = NULL;
c6cd91de	153	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr);
6af83b38 SP	154
	155	/* Check if current state is valid */
	156	if (cx->valid) {
	157	return curr;
	158	} else {
badc303a	159	int idx = OMAP3_NUM_STATES - 1;
6af83b38	160
c6cd91de	161	/* Reach the current state starting at highest C-state */
badc303a	162	for (; idx >= 0; idx--) {
6af83b38 SP	163	if (&dev->states[idx] == curr) {
	164	next = &dev->states[idx];
	165	break;
	166	}
	167	}
	168
c6cd91de	169	/* Should never hit this condition */
6af83b38 SP	170	WARN_ON(next == NULL);
	171
	172	/*
	173	* Drop to next valid state.
	174	* Start search from the next (lower) state.
	175	*/
	176	idx--;
badc303a	177	for (; idx >= 0; idx--) {
6af83b38 SP	178	cx = cpuidle_get_statedata(&dev->states[idx]);
	179	if (cx->valid) {
	180	next = &dev->states[idx];
	181	break;
	182	}
	183	}
	184	/*
badc303a	185	* C1 is always valid.
6af83b38 SP	186	* So, no need to check for 'next==NULL' outside this loop.
	187	*/
	188	}
	189
	190	return next;
	191	}
	192
99e6a4d2 RN	193	/**
	194	* omap3_enter_idle_bm - Checks for any bus activity
	195	* @dev: cpuidle device
	196	* @state: The target state to be programmed
	197	*
badc303a JP	198	* This function checks for any pending activity and then programs
badc303a JP	199	* the device to the specified or a safer state.
99e6a4d2 RN	200	*/
	201	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
	202	struct cpuidle_state *state)
	203	{
c6cd91de JP	204	struct cpuidle_state *new_state;
c6cd91de JP	205	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	206	struct omap3_idle_statedata *cx;
e7410cf7	207	int ret;
0f724ed9	208
c6cd91de	209	if (!omap3_can_sleep()) {
0f724ed9	210	new_state = dev->safe_state;
e7410cf7 KH	211	goto select_state;
	212	}
	213
e7410cf7 KH	214	/*
	215	* Prevent idle completely if CAM is active.
	216	* CAM does not have wakeup capability in OMAP3.
	217	*/
	218	cam_state = pwrdm_read_pwrst(cam_pd);
	219	if (cam_state == PWRDM_POWER_ON) {
	220	new_state = dev->safe_state;
	221	goto select_state;
	222	}
	223
c6cd91de JP	224	/*
	225	* FIXME: we currently manage device-specific idle states
	226	* for PER and CORE in combination with CPU-specific
	227	* idle states. This is wrong, and device-specific
	228	* idle management needs to be separated out into
	229	* its own code.
	230	*/
	231
e7410cf7 KH	232	/*
	233	* Prevent PER off if CORE is not in retention or off as this
	234	* would disable PER wakeups completely.
	235	*/
c6cd91de JP	236	cx = cpuidle_get_statedata(state);
c6cd91de JP	237	core_next_state = cx->core_state;
e7410cf7 KH	238	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	239	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	240	(core_next_state > PWRDM_POWER_RET))
e7410cf7	241	per_next_state = PWRDM_POWER_RET;
0f724ed9	242
e7410cf7 KH	243	/* Are we changing PER target state? */
	244	if (per_next_state != per_saved_state)
	245	pwrdm_set_next_pwrst(per_pd, per_next_state);
	246
c6cd91de JP	247	new_state = next_valid_state(dev, state);
c6cd91de JP	248
e7410cf7	249	select_state:
0f724ed9	250	dev->last_state = new_state;
e7410cf7 KH	251	ret = omap3_enter_idle(dev, new_state);
	252
	253	/* Restore original PER state if it was modified */
	254	if (per_next_state != per_saved_state)
	255	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	256
	257	return ret;
99e6a4d2 RN	258	}
	259
	260	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	261
6af83b38	262	/**
80723c3f	263	* omap3_cpuidle_update_states() - Update the cpuidle states
25985edc LDM	264	* @mpu_deepest_state: Enable states up to and including this for mpu domain
25985edc LDM	265	* @core_deepest_state: Enable states up to and including this for core domain
6af83b38	266	*
80723c3f NM	267	* This goes through the list of states available and enables and disables the
	268	* validity of C states based on deepest state that can be achieved for the
	269	* variable domain
6af83b38	270	*/
80723c3f	271	void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
6af83b38 SP	272	{
	273	int i;
	274
badc303a JP	275	for (i = 0; i < OMAP3_NUM_STATES; i++) {
badc303a JP	276	struct omap3_idle_statedata *cx = &omap3_idle_data[i];
6af83b38	277
80723c3f NM	278	if ((cx->mpu_state >= mpu_deepest_state) &&
80723c3f NM	279	(cx->core_state >= core_deepest_state)) {
6af83b38 SP	280	cx->valid = 1;
6af83b38 SP	281	} else {
80723c3f	282	cx->valid = 0;
6af83b38 SP	283	}
	284	}
	285	}
	286
bb4de3df KH	287	void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
	288	{
	289	int i;
	290
	291	if (!cpuidle_board_params)
	292	return;
	293
badc303a JP	294	for (i = 0; i < OMAP3_NUM_STATES; i++) {
badc303a JP	295	cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
866ba0ef JP	296	cpuidle_params_table[i].exit_latency =
	297	cpuidle_board_params[i].exit_latency;
	298	cpuidle_params_table[i].target_residency =
	299	cpuidle_board_params[i].target_residency;
bb4de3df KH	300	}
	301	return;
	302	}
	303
99e6a4d2 RN	304	struct cpuidle_driver omap3_idle_driver = {
	305	.name = "omap3_idle",
	306	.owner = THIS_MODULE,
	307	};
	308
c6cd91de	309	/* Helper to fill the C-state common data and register the driver_data */
badc303a JP	310	static inline struct omap3_idle_statedata *_fill_cstate(
	311	struct cpuidle_device *dev,
	312	int idx, const char *descr)
	313	{
	314	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	315	struct cpuidle_state *state = &dev->states[idx];
	316
	317	state->exit_latency = cpuidle_params_table[idx].exit_latency;
	318	state->target_residency = cpuidle_params_table[idx].target_residency;
	319	state->flags = CPUIDLE_FLAG_TIME_VALID;
	320	state->enter = omap3_enter_idle_bm;
	321	cx->valid = cpuidle_params_table[idx].valid;
	322	sprintf(state->name, "C%d", idx + 1);
	323	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
	324	cpuidle_set_statedata(state, cx);
	325
	326	return cx;
	327	}
	328
99e6a4d2 RN	329	/**
	330	* omap3_idle_init - Init routine for OMAP3 idle
	331	*
badc303a	332	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	333	* framework with the valid set of states.
99e6a4d2 RN	334	*/
0343371e	335	int __init omap3_idle_init(void)
99e6a4d2	336	{
99e6a4d2	337	struct cpuidle_device *dev;
badc303a	338	struct omap3_idle_statedata *cx;
99e6a4d2 RN	339
99e6a4d2 RN	340	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	341	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	342	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	343	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	344
99e6a4d2	345	cpuidle_register_driver(&omap3_idle_driver);
99e6a4d2 RN	346	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	347
badc303a JP	348	/* C1 . MPU WFI + Core active */
	349	cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
	350	(&dev->states[0])->enter = omap3_enter_idle;
	351	dev->safe_state = &dev->states[0];
	352	cx->valid = 1; /* C1 is always valid */
	353	cx->mpu_state = PWRDM_POWER_ON;
	354	cx->core_state = PWRDM_POWER_ON;
	355
	356	/* C2 . MPU WFI + Core inactive */
	357	cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
	358	cx->mpu_state = PWRDM_POWER_ON;
	359	cx->core_state = PWRDM_POWER_ON;
	360
	361	/* C3 . MPU CSWR + Core inactive */
	362	cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
	363	cx->mpu_state = PWRDM_POWER_RET;
	364	cx->core_state = PWRDM_POWER_ON;
	365
	366	/* C4 . MPU OFF + Core inactive */
	367	cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
	368	cx->mpu_state = PWRDM_POWER_OFF;
	369	cx->core_state = PWRDM_POWER_ON;
	370
	371	/* C5 . MPU RET + Core RET */
	372	cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
	373	cx->mpu_state = PWRDM_POWER_RET;
	374	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	375
badc303a JP	376	/* C6 . MPU OFF + Core RET */
	377	cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
	378	cx->mpu_state = PWRDM_POWER_OFF;
	379	cx->core_state = PWRDM_POWER_RET;
	380
	381	/* C7 . MPU OFF + Core OFF */
	382	cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
	383	/*
	384	* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	385	* enable OFF mode in a stable form for previous revisions.
	386	* We disable C7 state as a result.
	387	*/
	388	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
	389	cx->valid = 0;
	390	pr_warn("%s: core off state C7 disabled due to i583\n",
	391	__func__);
	392	}
	393	cx->mpu_state = PWRDM_POWER_OFF;
	394	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	395
80723c3f NM	396	if (enable_off_mode)
	397	omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
	398	else
	399	omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
6af83b38	400
badc303a	401	dev->state_count = OMAP3_NUM_STATES;
99e6a4d2 RN	402	if (cpuidle_register_device(dev)) {
	403	printk(KERN_ERR "%s: CPUidle register device failed\n",
	404	__func__);
	405	return -EIO;
	406	}
	407
	408	return 0;
	409	}
0343371e KJ	410	#else
	411	int __init omap3_idle_init(void)
	412	{
	413	return 0;
	414	}
99e6a4d2	415	#endif /* CONFIG_CPU_IDLE */