[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>

#include "pm.h"
#include "control.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
	u8 valid;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
	int idle_time;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
								USEC_PER_SEC;

	/* Update cpuidle counters */
	dev->last_residency = idle_time;

	return index;
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &drv->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->valid) &&
	    (cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&drv->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->valid) &&
			    (cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	if (!omap3_can_sleep()) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
{
	int i;

	if (!cpuidle_board_params)
		return;

	for (i = 0; i < OMAP3_NUM_STATES; i++) {
		cpuidle_params_table[i].valid =	cpuidle_board_params[i].valid;
		cpuidle_params_table[i].exit_latency =
			cpuidle_board_params[i].exit_latency;
		cpuidle_params_table[i].target_residency =
			cpuidle_board_params[i].target_residency;
	}
	return;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/* Helper to fill the C-state common data*/
static inline void _fill_cstate(struct cpuidle_driver *drv,
					int idx, const char *descr)
{
	struct cpuidle_state *state = &drv->states[idx];

	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
	state->target_residency	= cpuidle_params_table[idx].target_residency;
	state->flags		= CPUIDLE_FLAG_TIME_VALID;
	state->enter		= omap3_enter_idle_bm;
	sprintf(state->name, "C%d", idx + 1);
	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);

}

/* Helper to register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cx->valid		= cpuidle_params_table[idx].valid;
	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct cpuidle_driver *drv = &omap3_idle_driver;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");


	drv->safe_state_index = -1;
	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	_fill_cstate(drv, 0, "MPU ON + CORE ON");
	(&drv->states[0])->enter = omap3_enter_idle;
	drv->safe_state_index = 0;
	cx = _fill_cstate_usage(dev, 0);
	cx->valid = 1;	/* C1 is always valid */
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	_fill_cstate(drv, 1, "MPU ON + CORE ON");
	cx = _fill_cstate_usage(dev, 1);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	_fill_cstate(drv, 2, "MPU RET + CORE ON");
	cx = _fill_cstate_usage(dev, 2);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	_fill_cstate(drv, 3, "MPU OFF + CORE ON");
	cx = _fill_cstate_usage(dev, 3);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	_fill_cstate(drv, 4, "MPU RET + CORE RET");
	cx = _fill_cstate_usage(dev, 4);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	_fill_cstate(drv, 5, "MPU OFF + CORE RET");
	cx = _fill_cstate_usage(dev, 5);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
	cx = _fill_cstate_usage(dev, 6);
	/*
	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	 * enable OFF mode in a stable form for previous revisions.
	 * We disable C7 state as a result.
	 */
	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
		cx->valid = 0;
		pr_warn("%s: core off state C7 disabled due to i583\n",
			__func__);
	}
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	drv->state_count = OMAP3_NUM_STATES;
	cpuidle_register_driver(&omap3_idle_driver);

	dev->state_count = OMAP3_NUM_STATES;
	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2 RN	26	#include <linux/cpuidle.h>
	27
	28	#include <plat/prcm.h>
20b01669	29	#include <plat/irqs.h>
72e06d08	30	#include "powerdomain.h"
1540f214	31	#include "clockdomain.h"
0f724ed9	32	#include <plat/serial.h>
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
c98e2230	36
99e6a4d2 RN	37	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	38
bb4de3df KH	39	/*
	40	* The latencies/thresholds for various C states have
	41	* to be configured from the respective board files.
	42	* These are some default values (which might not provide
	43	* the best power savings) used on boards which do not
	44	* pass these details from the board file.
	45	*/
	46	static struct cpuidle_params cpuidle_params_table[] = {
	47	/* C1 */
866ba0ef	48	{2 + 2, 5, 1},
bb4de3df	49	/* C2 */
866ba0ef	50	{10 + 10, 30, 1},
bb4de3df	51	/* C3 */
866ba0ef	52	{50 + 50, 300, 1},
bb4de3df	53	/* C4 */
866ba0ef	54	{1500 + 1800, 4000, 1},
bb4de3df	55	/* C5 */
866ba0ef	56	{2500 + 7500, 12000, 1},
bb4de3df	57	/* C6 */
866ba0ef	58	{3000 + 8500, 15000, 1},
bb4de3df	59	/* C7 */
866ba0ef	60	{10000 + 30000, 300000, 1},
bb4de3df	61	};
badc303a JP	62	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	63
	64	/* Mach specific information to be recorded in the C-state driver_data */
	65	struct omap3_idle_statedata {
	66	u32 mpu_state;
	67	u32 core_state;
	68	u8 valid;
	69	};
	70	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	71
	72	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	73
06d8f065 PDS	74	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	75	struct clockdomain *clkdm)
	76	{
5cd1937b	77	clkdm_allow_idle(clkdm);
06d8f065 PDS	78	return 0;
	79	}
	80
	81	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	82	struct clockdomain *clkdm)
	83	{
5cd1937b	84	clkdm_deny_idle(clkdm);
06d8f065 PDS	85	return 0;
	86	}
	87
99e6a4d2 RN	88	/**
	89	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	90	* @dev: cpuidle device
46bcfad7	91	* @drv: cpuidle driver
e978aa7d	92	* @index: the index of state to be entered
99e6a4d2 RN	93	*
	94	* Called from the CPUidle framework to program the device to the
	95	* specified target state selected by the governor.
	96	*/
	97	static int omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	98	struct cpuidle_driver *drv,
e978aa7d	99	int index)
99e6a4d2	100	{
e978aa7d	101	struct omap3_idle_statedata *cx =
4202735e	102	cpuidle_get_statedata(&dev->states_usage[index]);
99e6a4d2	103	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	104	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
e978aa7d	105	int idle_time;
99e6a4d2	106
99e6a4d2 RN	107	/* Used to keep track of the total time in idle */
	108	getnstimeofday(&ts_preidle);
	109
	110	local_irq_disable();
	111	local_fiq_disable();
	112
7139178e JH	113	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	114	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	115
cf22854c	116	if (omap_irq_pending() \|\| need_resched())
20b01669	117	goto return_sleep_time;
99e6a4d2	118
badc303a	119	/* Deny idle for C1 */
e978aa7d	120	if (index == 0) {
06d8f065 PDS	121	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	122	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	123	}
	124
99e6a4d2 RN	125	/* Execute ARM wfi */
	126	omap_sram_idle();
	127
badc303a	128	/* Re-allow idle for C1 */
e978aa7d	129	if (index == 0) {
06d8f065 PDS	130	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	131	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	132	}
	133
20b01669	134	return_sleep_time:
99e6a4d2 RN	135	getnstimeofday(&ts_postidle);
	136	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	137
	138	local_irq_enable();
	139	local_fiq_enable();
	140
e978aa7d DD	141	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
	142	USEC_PER_SEC;
	143
	144	/* Update cpuidle counters */
	145	dev->last_residency = idle_time;
	146
	147	return index;
99e6a4d2 RN	148	}
99e6a4d2 RN	149
6af83b38	150	/**
04908918	151	* next_valid_state - Find next valid C-state
6af83b38	152	* @dev: cpuidle device
46bcfad7	153	* @drv: cpuidle driver
e978aa7d	154	* @index: Index of currently selected c-state
6af83b38	155	*
e978aa7d DD	156	* If the state corresponding to index is valid, index is returned back
	157	* to the caller. Else, this function searches for a lower c-state which is
	158	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	159	*
	160	* A state is valid if the 'valid' field is enabled and
	161	* if it satisfies the enable_off_mode condition.
6af83b38	162	*/
e978aa7d	163	static int next_valid_state(struct cpuidle_device *dev,
46bcfad7	164	struct cpuidle_driver *drv,
e978aa7d	165	int index)
6af83b38	166	{
4202735e	167	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
46bcfad7	168	struct cpuidle_state *curr = &drv->states[index];
4202735e	169	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	170	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	171	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	172	int next_index = -1;
04908918 JP	173
	174	if (enable_off_mode) {
	175	mpu_deepest_state = PWRDM_POWER_OFF;
	176	/*
	177	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	178	* CORE OFF mode is not supported in a stable form, restrict
	179	* instead the CORE state to RET.
	180	*/
	181	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	182	core_deepest_state = PWRDM_POWER_OFF;
	183	}
6af83b38 SP	184
6af83b38 SP	185	/* Check if current state is valid */
04908918 JP	186	if ((cx->valid) &&
	187	(cx->mpu_state >= mpu_deepest_state) &&
	188	(cx->core_state >= core_deepest_state)) {
e978aa7d	189	return index;
6af83b38	190	} else {
badc303a	191	int idx = OMAP3_NUM_STATES - 1;
6af83b38	192
c6cd91de	193	/* Reach the current state starting at highest C-state */
badc303a	194	for (; idx >= 0; idx--) {
46bcfad7	195	if (&drv->states[idx] == curr) {
e978aa7d	196	next_index = idx;
6af83b38 SP	197	break;
	198	}
	199	}
	200
c6cd91de	201	/* Should never hit this condition */
e978aa7d	202	WARN_ON(next_index == -1);
6af83b38 SP	203
	204	/*
	205	* Drop to next valid state.
	206	* Start search from the next (lower) state.
	207	*/
	208	idx--;
badc303a	209	for (; idx >= 0; idx--) {
4202735e	210	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
04908918 JP	211	if ((cx->valid) &&
	212	(cx->mpu_state >= mpu_deepest_state) &&
	213	(cx->core_state >= core_deepest_state)) {
e978aa7d	214	next_index = idx;
6af83b38 SP	215	break;
	216	}
	217	}
	218	/*
badc303a	219	* C1 is always valid.
e978aa7d DD	220	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	221	* this loop.
6af83b38 SP	222	*/
	223	}
	224
e978aa7d	225	return next_index;
6af83b38 SP	226	}
6af83b38 SP	227
99e6a4d2 RN	228	/**
	229	* omap3_enter_idle_bm - Checks for any bus activity
	230	* @dev: cpuidle device
46bcfad7	231	* @drv: cpuidle driver
e978aa7d	232	* @index: array index of target state to be programmed
99e6a4d2	233	*
badc303a JP	234	* This function checks for any pending activity and then programs
badc303a JP	235	* the device to the specified or a safer state.
99e6a4d2 RN	236	*/
99e6a4d2 RN	237	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	238	struct cpuidle_driver *drv,
e978aa7d	239	int index)
99e6a4d2	240	{
e978aa7d	241	int new_state_idx;
c6cd91de	242	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	243	struct omap3_idle_statedata *cx;
e7410cf7	244	int ret;
0f724ed9	245
c6cd91de	246	if (!omap3_can_sleep()) {
46bcfad7	247	new_state_idx = drv->safe_state_index;
e7410cf7 KH	248	goto select_state;
	249	}
	250
e7410cf7 KH	251	/*
	252	* Prevent idle completely if CAM is active.
	253	* CAM does not have wakeup capability in OMAP3.
	254	*/
	255	cam_state = pwrdm_read_pwrst(cam_pd);
	256	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	257	new_state_idx = drv->safe_state_index;
e7410cf7 KH	258	goto select_state;
	259	}
	260
c6cd91de JP	261	/*
	262	* FIXME: we currently manage device-specific idle states
	263	* for PER and CORE in combination with CPU-specific
	264	* idle states. This is wrong, and device-specific
	265	* idle management needs to be separated out into
	266	* its own code.
	267	*/
	268
e7410cf7 KH	269	/*
	270	* Prevent PER off if CORE is not in retention or off as this
	271	* would disable PER wakeups completely.
	272	*/
4202735e	273	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	274	core_next_state = cx->core_state;
e7410cf7 KH	275	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	276	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	277	(core_next_state > PWRDM_POWER_RET))
e7410cf7	278	per_next_state = PWRDM_POWER_RET;
0f724ed9	279
e7410cf7 KH	280	/* Are we changing PER target state? */
	281	if (per_next_state != per_saved_state)
	282	pwrdm_set_next_pwrst(per_pd, per_next_state);
	283
46bcfad7	284	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	285
e7410cf7	286	select_state:
46bcfad7	287	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	288
	289	/* Restore original PER state if it was modified */
	290	if (per_next_state != per_saved_state)
	291	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	292
	293	return ret;
99e6a4d2 RN	294	}
	295
	296	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	297
bb4de3df KH	298	void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
	299	{
	300	int i;
	301
	302	if (!cpuidle_board_params)
	303	return;
	304
badc303a JP	305	for (i = 0; i < OMAP3_NUM_STATES; i++) {
badc303a JP	306	cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
866ba0ef JP	307	cpuidle_params_table[i].exit_latency =
	308	cpuidle_board_params[i].exit_latency;
	309	cpuidle_params_table[i].target_residency =
	310	cpuidle_board_params[i].target_residency;
bb4de3df KH	311	}
	312	return;
	313	}
	314
99e6a4d2 RN	315	struct cpuidle_driver omap3_idle_driver = {
	316	.name = "omap3_idle",
	317	.owner = THIS_MODULE,
	318	};
	319
46bcfad7 DD	320	/* Helper to fill the C-state common data*/
46bcfad7 DD	321	static inline void _fill_cstate(struct cpuidle_driver *drv,
badc303a JP	322	int idx, const char *descr)
badc303a JP	323	{
46bcfad7	324	struct cpuidle_state *state = &drv->states[idx];
badc303a JP	325
	326	state->exit_latency = cpuidle_params_table[idx].exit_latency;
	327	state->target_residency = cpuidle_params_table[idx].target_residency;
	328	state->flags = CPUIDLE_FLAG_TIME_VALID;
	329	state->enter = omap3_enter_idle_bm;
badc303a JP	330	sprintf(state->name, "C%d", idx + 1);
badc303a JP	331	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
46bcfad7 DD	332
	333	}
	334
	335	/* Helper to register the driver_data */
	336	static inline struct omap3_idle_statedata *_fill_cstate_usage(
	337	struct cpuidle_device *dev,
	338	int idx)
	339	{
	340	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	341	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	342
	343	cx->valid = cpuidle_params_table[idx].valid;
4202735e	344	cpuidle_set_statedata(state_usage, cx);
badc303a JP	345
	346	return cx;
	347	}
	348
99e6a4d2 RN	349	/**
	350	* omap3_idle_init - Init routine for OMAP3 idle
	351	*
badc303a	352	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	353	* framework with the valid set of states.
99e6a4d2 RN	354	*/
0343371e	355	int __init omap3_idle_init(void)
99e6a4d2	356	{
99e6a4d2	357	struct cpuidle_device *dev;
46bcfad7	358	struct cpuidle_driver *drv = &omap3_idle_driver;
badc303a	359	struct omap3_idle_statedata *cx;
99e6a4d2 RN	360
99e6a4d2 RN	361	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	362	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	363	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	364	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	365
46bcfad7 DD	366
46bcfad7 DD	367	drv->safe_state_index = -1;
99e6a4d2 RN	368	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	369
badc303a	370	/* C1 . MPU WFI + Core active */
46bcfad7 DD	371	_fill_cstate(drv, 0, "MPU ON + CORE ON");
	372	(&drv->states[0])->enter = omap3_enter_idle;
	373	drv->safe_state_index = 0;
	374	cx = _fill_cstate_usage(dev, 0);
badc303a JP	375	cx->valid = 1; /* C1 is always valid */
	376	cx->mpu_state = PWRDM_POWER_ON;
	377	cx->core_state = PWRDM_POWER_ON;
	378
	379	/* C2 . MPU WFI + Core inactive */
46bcfad7 DD	380	_fill_cstate(drv, 1, "MPU ON + CORE ON");
46bcfad7 DD	381	cx = _fill_cstate_usage(dev, 1);
badc303a JP	382	cx->mpu_state = PWRDM_POWER_ON;
	383	cx->core_state = PWRDM_POWER_ON;
	384
	385	/* C3 . MPU CSWR + Core inactive */
46bcfad7 DD	386	_fill_cstate(drv, 2, "MPU RET + CORE ON");
46bcfad7 DD	387	cx = _fill_cstate_usage(dev, 2);
badc303a JP	388	cx->mpu_state = PWRDM_POWER_RET;
	389	cx->core_state = PWRDM_POWER_ON;
	390
	391	/* C4 . MPU OFF + Core inactive */
46bcfad7 DD	392	_fill_cstate(drv, 3, "MPU OFF + CORE ON");
46bcfad7 DD	393	cx = _fill_cstate_usage(dev, 3);
badc303a JP	394	cx->mpu_state = PWRDM_POWER_OFF;
	395	cx->core_state = PWRDM_POWER_ON;
	396
	397	/* C5 . MPU RET + Core RET */
46bcfad7 DD	398	_fill_cstate(drv, 4, "MPU RET + CORE RET");
46bcfad7 DD	399	cx = _fill_cstate_usage(dev, 4);
badc303a JP	400	cx->mpu_state = PWRDM_POWER_RET;
badc303a JP	401	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	402
badc303a	403	/* C6 . MPU OFF + Core RET */
46bcfad7 DD	404	_fill_cstate(drv, 5, "MPU OFF + CORE RET");
46bcfad7 DD	405	cx = _fill_cstate_usage(dev, 5);
badc303a JP	406	cx->mpu_state = PWRDM_POWER_OFF;
	407	cx->core_state = PWRDM_POWER_RET;
	408
	409	/* C7 . MPU OFF + Core OFF */
46bcfad7 DD	410	_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
46bcfad7 DD	411	cx = _fill_cstate_usage(dev, 6);
badc303a JP	412	/*
	413	* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	414	* enable OFF mode in a stable form for previous revisions.
	415	* We disable C7 state as a result.
	416	*/
	417	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
	418	cx->valid = 0;
	419	pr_warn("%s: core off state C7 disabled due to i583\n",
	420	__func__);
	421	}
	422	cx->mpu_state = PWRDM_POWER_OFF;
	423	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	424
46bcfad7 DD	425	drv->state_count = OMAP3_NUM_STATES;
	426	cpuidle_register_driver(&omap3_idle_driver);
	427
badc303a	428	dev->state_count = OMAP3_NUM_STATES;
99e6a4d2 RN	429	if (cpuidle_register_device(dev)) {
	430	printk(KERN_ERR "%s: CPUidle register device failed\n",
	431	__func__);
	432	return -EIO;
	433	}
	434
	435	return 0;
	436	}
0343371e KJ	437	#else
	438	int __init omap3_idle_init(void)
	439	{
	440	return 0;
	441	}
99e6a4d2	442	#endif /* CONFIG_CPU_IDLE */