[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include "common.h"

#include "iomap.h"
#include "mux.h"
#include "control.h"
#include "display.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
{
	u32 reg;
	u16 control_i2c_1;

	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);

	/*
	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	 * internal pull up resistor.
	 */
	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
		reg = omap4_ctrl_pad_readl(control_i2c_1);
		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
			omap4_ctrl_pad_writel(reg, control_i2c_1);
	}
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads(flags);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (IS_ERR(od)) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;

	/* create omapdss device */

	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

#define MAX_MODULE_SOFTRESET_WAIT	10000
int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
b7ee79ab	26
a0b38cc4	27	#include <video/omapdss.h>
cf07f531 SG	28	#include <plat/omap_hwmod.h>
cf07f531 SG	29	#include <plat/omap_device.h>
700dee78	30	#include <plat/omap-pm.h>
deee6d53	31	#include "common.h"
b7ee79ab	32
ee0839c2	33	#include "iomap.h"
ee9dfd82	34	#include "mux.h"
dc35835c	35	#include "control.h"
b923d40d AT	36	#include "display.h"
	37
	38	#define DISPC_CONTROL 0x0040
	39	#define DISPC_CONTROL2 0x0238
465698ee	40	#define DISPC_CONTROL3 0x0848
b923d40d AT	41	#define DISPC_IRQSTATUS 0x0018
	42
	43	#define DSS_SYSCONFIG 0x10
	44	#define DSS_SYSSTATUS 0x14
	45	#define DSS_CONTROL 0x40
	46	#define DSS_SDI_CONTROL 0x44
	47	#define DSS_PLL_CONTROL 0x48
	48
	49	#define LCD_EN_MASK (0x1 << 0)
	50	#define DIGIT_EN_MASK (0x1 << 1)
	51
	52	#define FRAMEDONE_IRQ_SHIFT 0
	53	#define EVSYNC_EVEN_IRQ_SHIFT 2
	54	#define EVSYNC_ODD_IRQ_SHIFT 3
	55	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	56	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	57	#define FRAMEDONETV_IRQ_SHIFT 24
	58
	59	/*
	60	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	61	* reset before deciding that something has gone wrong
	62	*/
	63	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	64
b7ee79ab SS	65	static struct platform_device omap_display_device = {
	66	.name = "omapdss",
	67	.id = -1,
	68	.dev = {
	69	.platform_data = NULL,
	70	},
	71	};
	72
179e0453 AT	73	struct omap_dss_hwmod_data {
	74	const char *oh_name;
	75	const char *dev_name;
	76	const int id;
	77	};
	78
bcad6dc3	79	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
179e0453 AT	80	{ "dss_core", "omapdss_dss", -1 },
	81	{ "dss_dispc", "omapdss_dispc", -1 },
	82	{ "dss_rfbi", "omapdss_rfbi", -1 },
	83	{ "dss_venc", "omapdss_venc", -1 },
	84	};
	85
bcad6dc3	86	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
179e0453 AT	87	{ "dss_core", "omapdss_dss", -1 },
	88	{ "dss_dispc", "omapdss_dispc", -1 },
	89	{ "dss_rfbi", "omapdss_rfbi", -1 },
	90	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	91	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	92	};
179e0453 AT	93
bcad6dc3	94	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
179e0453 AT	95	{ "dss_core", "omapdss_dss", -1 },
	96	{ "dss_dispc", "omapdss_dispc", -1 },
	97	{ "dss_rfbi", "omapdss_rfbi", -1 },
7c68dd96 TV	98	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	99	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	100	{ "dss_hdmi", "omapdss_hdmi", -1 },
	101	};
	102
e8a30b25	103	static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
ee9dfd82	104	{
9a901683 M	105	u32 reg;
	106	u16 control_i2c_1;
	107
ee9dfd82 M	108	omap_mux_init_signal("hdmi_cec",
ee9dfd82 M	109	OMAP_PIN_INPUT_PULLUP);
ee9dfd82 M	110	omap_mux_init_signal("hdmi_ddc_scl",
	111	OMAP_PIN_INPUT_PULLUP);
	112	omap_mux_init_signal("hdmi_ddc_sda",
	113	OMAP_PIN_INPUT_PULLUP);
9a901683 M	114
	115	/*
	116	* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	117	* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	118	* internal pull up resistor.
	119	*/
	120	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
	121	control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
	122	reg = omap4_ctrl_pad_readl(control_i2c_1);
	123	reg \|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK \|
	124	OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
	125	omap4_ctrl_pad_writel(reg, control_i2c_1);
	126	}
ee9dfd82 M	127	}
ee9dfd82 M	128
e8a30b25	129	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
dc35835c TV	130	{
	131	u32 enable_mask, enable_shift;
	132	u32 pipd_mask, pipd_shift;
	133	u32 reg;
	134
	135	if (dsi_id == 0) {
	136	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	137	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	138	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	139	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	140	} else if (dsi_id == 1) {
	141	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	142	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	143	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	144	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	145	} else {
	146	return -ENODEV;
	147	}
	148
	149	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	150
	151	reg &= ~enable_mask;
	152	reg &= ~pipd_mask;
	153
	154	reg \|= (lanes << enable_shift) & enable_mask;
	155	reg \|= (lanes << pipd_shift) & pipd_mask;
	156
	157	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	158
	159	return 0;
	160	}
	161
d1589f09	162	int __init omap_hdmi_init(enum omap_hdmi_flags flags)
ee9dfd82 M	163	{
ee9dfd82 M	164	if (cpu_is_omap44xx())
9a901683	165	omap4_hdmi_mux_pads(flags);
ee9dfd82 M	166
	167	return 0;
	168	}
	169
e8a30b25	170	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	171	{
dc35835c TV	172	if (cpu_is_omap44xx())
	173	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	174
5bc416cb TV	175	return 0;
	176	}
	177
e8a30b25	178	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	179	{
dc35835c TV	180	if (cpu_is_omap44xx())
dc35835c TV	181	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	182	}
5bc416cb TV	183
62c1dcfc TV	184	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	185	{
	186	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	187	}
	188
966eaed0 TV	189	static struct platform_device create_dss_pdev(const char pdev_name,
	190	int pdev_id, const char oh_name, void pdata, int pdata_len,
	191	struct platform_device *parent)
	192	{
	193	struct platform_device *pdev;
	194	struct omap_device *od;
	195	struct omap_hwmod *ohs[1];
	196	struct omap_hwmod *oh;
	197	int r;
	198
	199	oh = omap_hwmod_lookup(oh_name);
	200	if (!oh) {
	201	pr_err("Could not look up %s\n", oh_name);
	202	r = -ENODEV;
	203	goto err;
	204	}
	205
	206	pdev = platform_device_alloc(pdev_name, pdev_id);
	207	if (!pdev) {
	208	pr_err("Could not create pdev for %s\n", pdev_name);
	209	r = -ENOMEM;
	210	goto err;
	211	}
	212
	213	if (parent != NULL)
	214	pdev->dev.parent = &parent->dev;
	215
	216	if (pdev->id != -1)
	217	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	218	else
	219	dev_set_name(&pdev->dev, "%s", pdev->name);
	220
	221	ohs[0] = oh;
	222	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
9ee67723	223	if (IS_ERR(od)) {
966eaed0 TV	224	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	225	r = -ENOMEM;
	226	goto err;
	227	}
	228
	229	r = platform_device_add_data(pdev, pdata, pdata_len);
	230	if (r) {
	231	pr_err("Could not set pdata for %s\n", pdev_name);
	232	goto err;
	233	}
	234
	235	r = omap_device_register(pdev);
	236	if (r) {
	237	pr_err("Could not register omap_device for %s\n", pdev_name);
	238	goto err;
	239	}
	240
	241	return pdev;
	242
	243	err:
	244	return ERR_PTR(r);
	245	}
	246
53f576a8 TV	247	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	248	int pdev_id, void *pdata, int pdata_len,
	249	struct platform_device *parent)
	250	{
	251	struct platform_device *pdev;
	252	int r;
	253
	254	pdev = platform_device_alloc(pdev_name, pdev_id);
	255	if (!pdev) {
	256	pr_err("Could not create pdev for %s\n", pdev_name);
	257	r = -ENOMEM;
	258	goto err;
	259	}
	260
	261	if (parent != NULL)
	262	pdev->dev.parent = &parent->dev;
	263
	264	if (pdev->id != -1)
	265	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	266	else
	267	dev_set_name(&pdev->dev, "%s", pdev->name);
	268
	269	r = platform_device_add_data(pdev, pdata, pdata_len);
	270	if (r) {
	271	pr_err("Could not set pdata for %s\n", pdev_name);
	272	goto err;
	273	}
	274
c3a21fc7	275	r = platform_device_add(pdev);
53f576a8	276	if (r) {
c3a21fc7	277	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	278	goto err;
	279	}
	280
	281	return pdev;
	282
	283	err:
	284	return ERR_PTR(r);
	285	}
	286
b7ee79ab SS	287	int __init omap_display_init(struct omap_dss_board_info *board_data)
	288	{
	289	int r = 0;
3528c58e	290	struct platform_device *pdev;
179e0453	291	int i, oh_count;
179e0453	292	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	293	struct platform_device *dss_pdev;
cf07f531	294
00928eaf TV	295	/* create omapdss device */
	296
	297	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	298	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	299	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	300	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	301
	302	omap_display_device.dev.platform_data = board_data;
	303
	304	r = platform_device_register(&omap_display_device);
	305	if (r < 0) {
	306	pr_err("Unable to register omapdss device\n");
	307	return r;
	308	}
	309
	310	/* create devices for dss hwmods */
cf07f531	311
179e0453 AT	312	if (cpu_is_omap24xx()) {
	313	curr_dss_hwmod = omap2_dss_hwmod_data;
	314	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	315	} else if (cpu_is_omap34xx()) {
	316	curr_dss_hwmod = omap3_dss_hwmod_data;
	317	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	318	} else {
	319	curr_dss_hwmod = omap4_dss_hwmod_data;
	320	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	321	}
545376e7	322
966eaed0 TV	323	/*
	324	* First create the pdev for dss_core, which is used as a parent device
	325	* by the other dss pdevs. Note: dss_core has to be the first item in
	326	* the hwmod list.
	327	*/
	328	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	329	curr_dss_hwmod[0].id,
	330	curr_dss_hwmod[0].oh_name,
35deca3d	331	board_data, sizeof(*board_data),
966eaed0	332	NULL);
fd4b34f6	333
966eaed0 TV	334	if (IS_ERR(dss_pdev)) {
	335	pr_err("Could not build omap_device for %s\n",
	336	curr_dss_hwmod[0].oh_name);
	337
	338	return PTR_ERR(dss_pdev);
	339	}
	340
	341	for (i = 1; i < oh_count; i++) {
	342	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	343	curr_dss_hwmod[i].id,
	344	curr_dss_hwmod[i].oh_name,
35deca3d	345	board_data, sizeof(*board_data),
966eaed0 TV	346	dss_pdev);
	347
	348	if (IS_ERR(pdev)) {
	349	pr_err("Could not build omap_device for %s\n",
	350	curr_dss_hwmod[i].oh_name);
cf07f531	351
966eaed0 TV	352	return PTR_ERR(pdev);
966eaed0 TV	353	}
cf07f531	354	}
b7ee79ab	355
53f576a8 TV	356	/* Create devices for DPI and SDI */
53f576a8 TV	357
35deca3d TV	358	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
35deca3d TV	359	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	360	if (IS_ERR(pdev)) {
	361	pr_err("Could not build platform_device for omapdss_dpi\n");
	362	return PTR_ERR(pdev);
	363	}
	364
	365	if (cpu_is_omap34xx()) {
35deca3d TV	366	pdev = create_simple_dss_pdev("omapdss_sdi", -1,
35deca3d TV	367	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	368	if (IS_ERR(pdev)) {
	369	pr_err("Could not build platform_device for omapdss_sdi\n");
	370	return PTR_ERR(pdev);
	371	}
	372	}
	373
00928eaf	374	return 0;
b7ee79ab	375	}
13662dc5	376
b923d40d AT	377	static void dispc_disable_outputs(void)
	378	{
	379	u32 v, irq_mask = 0;
465698ee	380	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	381	int i;
	382	struct omap_dss_dispc_dev_attr *da;
	383	struct omap_hwmod *oh;
	384
	385	oh = omap_hwmod_lookup("dss_dispc");
	386	if (!oh) {
	387	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	388	return;
	389	}
	390
	391	if (!oh->dev_attr) {
	392	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	393	return;
	394	}
	395
	396	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	397
	398	/* store value of LCDENABLE and DIGITENABLE bits */
	399	v = omap_hwmod_read(oh, DISPC_CONTROL);
	400	lcd_en = v & LCD_EN_MASK;
	401	digit_en = v & DIGIT_EN_MASK;
	402
	403	/* store value of LCDENABLE for LCD2 */
	404	if (da->manager_count > 2) {
	405	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	406	lcd2_en = v & LCD_EN_MASK;
	407	}
	408
465698ee CM	409	/* store value of LCDENABLE for LCD3 */
	410	if (da->manager_count > 3) {
	411	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	412	lcd3_en = v & LCD_EN_MASK;
	413	}
	414
	415	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	416	return; /* no managers currently enabled */
	417
	418	/*
	419	* If any manager was enabled, we need to disable it before
	420	* DSS clocks are disabled or DISPC module is reset
	421	*/
	422	if (lcd_en)
	423	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	424
	425	if (digit_en) {
	426	if (da->has_framedonetv_irq) {
	427	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	428	} else {
	429	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	430	1 << EVSYNC_ODD_IRQ_SHIFT;
	431	}
	432	}
	433
	434	if (lcd2_en)
	435	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	436	if (lcd3_en)
465698ee CM	437	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	438
	439	/*
	440	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	441	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	442	*/
	443	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	444
	445	/* disable LCD and TV managers */
	446	v = omap_hwmod_read(oh, DISPC_CONTROL);
	447	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	448	omap_hwmod_write(v, oh, DISPC_CONTROL);
	449
	450	/* disable LCD2 manager */
	451	if (da->manager_count > 2) {
	452	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	453	v &= ~LCD_EN_MASK;
	454	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	455	}
	456
465698ee CM	457	/* disable LCD3 manager */
	458	if (da->manager_count > 3) {
	459	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	460	v &= ~LCD_EN_MASK;
	461	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	462	}
	463
b923d40d AT	464	i = 0;
	465	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	466	irq_mask) {
	467	i++;
	468	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	469	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	470	break;
	471	}
	472	mdelay(1);
	473	}
	474	}
	475
13662dc5 TV	476	#define MAX_MODULE_SOFTRESET_WAIT 10000
	477	int omap_dss_reset(struct omap_hwmod *oh)
	478	{
	479	struct omap_hwmod_opt_clk *oc;
	480	int c = 0;
	481	int i, r;
	482
	483	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	484	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	485	return -EINVAL;
	486	}
	487
	488	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	489	if (oc->_clk)
4d7cb45e	490	clk_prepare_enable(oc->_clk);
13662dc5	491
b923d40d AT	492	dispc_disable_outputs();
	493
	494	/* clear SDI registers */
	495	if (cpu_is_omap3430()) {
	496	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	497	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	498	}
	499
	500	/*
	501	* clear DSS_CONTROL register to switch DSS clock sources to
	502	* PRCM clock, if any
	503	*/
	504	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	505
13662dc5 TV	506	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	507	& SYSS_RESETDONE_MASK),
	508	MAX_MODULE_SOFTRESET_WAIT, c);
	509
	510	if (c == MAX_MODULE_SOFTRESET_WAIT)
	511	pr_warning("dss_core: waiting for reset to finish failed\n");
	512	else
	513	pr_debug("dss_core: softreset done\n");
	514
	515	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	516	if (oc->_clk)
4d7cb45e	517	clk_disable_unprepare(oc->_clk);
13662dc5 TV	518
	519	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	520
	521	return r;
	522	}