[deliverable/linux.git] / arch / arm / mach-omap2 / dma.c

/*
 * OMAP2+ DMA driver
 *
 * Copyright (C) 2003 - 2008 Nokia Corporation
 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
 * Graphics DMA and LCD DMA graphics tranformations
 * by Imre Deak <imre.deak@nokia.com>
 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 * Converted DMA library into platform driver
 *	- G, Manjunath Kondaiah <manjugk@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/omap-dma.h>

#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"

static u32 errata;

static struct omap_dma_dev_attr *d;

static enum omap_reg_offsets dma_common_ch_end;

static const struct omap_dma_reg reg_map[] = {
	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },

	/* Common register offsets */
	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },

	/* Channel specific register offsets */
	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },

	/* OMAP4 specific registers */
	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
};

static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
	void __iomem *addr = dma_base;

	addr += reg_map[reg].offset;
	addr += reg_map[reg].stride * lch;

	__raw_writel(val, addr);
}

static inline u32 dma_read(int reg, int lch)
{
	void __iomem *addr = dma_base;

	addr += reg_map[reg].offset;
	addr += reg_map[reg].stride * lch;

	return __raw_readl(addr);
}

static void omap2_clear_dma(int lch)
{
	int i;

	for (i = CSDP; i <= dma_common_ch_end; i += 1)
		dma_write(0, i, lch);
}

static void omap2_show_dma_caps(void)
{
	u8 revision = dma_read(REVISION, 0) & 0xff;
	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
				revision >> 4, revision & 0xf);
	return;
}

static u32 configure_dma_errata(void)
{

	/*
	 * Errata applicable for OMAP2430ES1.0 and all omap2420
	 *
	 * I.
	 * Erratum ID: Not Available
	 * Inter Frame DMA buffering issue DMA will wrongly
	 * buffer elements if packing and bursting is enabled. This might
	 * result in data gets stalled in FIFO at the end of the block.
	 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
	 * guarantee no data will stay in the DMA FIFO in case inter frame
	 * buffering occurs
	 *
	 * II.
	 * Erratum ID: Not Available
	 * DMA may hang when several channels are used in parallel
	 * In the following configuration, DMA channel hanging can occur:
	 * a. Channel i, hardware synchronized, is enabled
	 * b. Another channel (Channel x), software synchronized, is enabled.
	 * c. Channel i is disabled before end of transfer
	 * d. Channel i is reenabled.
	 * e. Steps 1 to 4 are repeated a certain number of times.
	 * f. A third channel (Channel y), software synchronized, is enabled.
	 * Channel x and Channel y may hang immediately after step 'f'.
	 * Workaround:
	 * For any channel used - make sure NextLCH_ID is set to the value j.
	 */
	if (cpu_is_omap2420() || (cpu_is_omap2430() &&
				(omap_type() == OMAP2430_REV_ES1_0))) {

		SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
		SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
	}

	/*
	 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
	 * after a transaction error.
	 * Workaround: SW should explicitely disable the channel.
	 */
	if (cpu_class_is_omap2())
		SET_DMA_ERRATA(DMA_ERRATA_i378);

	/*
	 * Erratum ID: i541: sDMA FIFO draining does not finish
	 * If sDMA channel is disabled on the fly, sDMA enters standby even
	 * through FIFO Drain is still in progress
	 * Workaround: Put sDMA in NoStandby more before a logical channel is
	 * disabled, then put it back to SmartStandby right after the channel
	 * finishes FIFO draining.
	 */
	if (cpu_is_omap34xx())
		SET_DMA_ERRATA(DMA_ERRATA_i541);

	/*
	 * Erratum ID: i88 : Special programming model needed to disable DMA
	 * before end of block.
	 * Workaround: software must ensure that the DMA is configured in No
	 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
	 */
	if (omap_type() == OMAP3430_REV_ES1_0)
		SET_DMA_ERRATA(DMA_ERRATA_i88);

	/*
	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
	 * read before the DMA controller finished disabling the channel.
	 */
	SET_DMA_ERRATA(DMA_ERRATA_3_3);

	/*
	 * Erratum ID: Not Available
	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
	 * after secure sram context save and restore.
	 * Work around: Hence we need to manually clear those IRQs to avoid
	 * spurious interrupts. This affects only secure devices.
	 */
	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		SET_DMA_ERRATA(DMA_ROMCODE_BUG);

	return errata;
}

/* One time initializations */
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
{
	struct platform_device			*pdev;
	struct omap_system_dma_plat_info	*p;
	struct resource				*mem;
	char					*name = "omap_dma_system";

	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
	if (!p) {
		pr_err("%s: Unable to allocate pdata for %s:%s\n",
			__func__, name, oh->name);
		return -ENOMEM;
	}

	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
	p->show_dma_caps	= omap2_show_dma_caps;
	p->clear_dma		= omap2_clear_dma;
	p->dma_write		= dma_write;
	p->dma_read		= dma_read;

	p->clear_lch_regs	= NULL;

	p->errata		= configure_dma_errata();

	pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
	kfree(p);
	if (IS_ERR(pdev)) {
		pr_err("%s: Can't build omap_device for %s:%s.\n",
			__func__, name, oh->name);
		return PTR_ERR(pdev);
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
		return -EINVAL;
	}
	dma_base = ioremap(mem->start, resource_size(mem));
	if (!dma_base) {
		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
		return -ENOMEM;
	}

	d = oh->dev_attr;
	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
					(d->lch_count), GFP_KERNEL);

	if (!d->chan) {
		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
		return -ENOMEM;
	}

	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		d->dev_caps |= HS_CHANNELS_RESERVED;

	/* Check the capabilities register for descriptor loading feature */
	if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
		dma_common_ch_end = CCDN;
	else
		dma_common_ch_end = CCFN;

	return 0;
}

static const struct platform_device_info omap_dma_dev_info = {
	.name = "omap-dma-engine",
	.id = -1,
	.dma_mask = DMA_BIT_MASK(32),
};

static int __init omap2_system_dma_init(void)
{
	struct platform_device *pdev;
	int res;

	res = omap_hwmod_for_each_by_class("dma",
			omap2_system_dma_init_dev, NULL);
	if (res)
		return res;

	if (of_have_populated_dt())
		return res;

	pdev = platform_device_register_full(&omap_dma_dev_info);
	if (IS_ERR(pdev))
		return PTR_ERR(pdev);

	return res;
}
omap_arch_initcall(omap2_system_dma_init);
Commit	Line	Data
59de3cf1 MK	1	/*
	2	* OMAP2+ DMA driver
	3	*
	4	* Copyright (C) 2003 - 2008 Nokia Corporation
	5	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
	6	* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
	7	* Graphics DMA and LCD DMA graphics tranformations
	8	* by Imre Deak <imre.deak@nokia.com>
	9	* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
	10	* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
	11	*
	12	* Copyright (C) 2009 Texas Instruments
	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	14	*
	15	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	16	* Converted DMA library into platform driver
	17	* - G, Manjunath Kondaiah <manjugk@ti.com>
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License version 2 as
	21	* published by the Free Software Foundation.
	22	*/
	23
	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/slab.h>
	27	#include <linux/module.h>
	28	#include <linux/init.h>
	29	#include <linux/device.h>
be1f9481	30	#include <linux/dma-mapping.h>
8d30662a	31	#include <linux/of.h>
45c3eb7d	32	#include <linux/omap-dma.h>
59de3cf1	33
e4c060db	34	#include "soc.h"
2a296c8f	35	#include "omap_hwmod.h"
25c7d49e TL	36	#include "omap_device.h"
25c7d49e TL	37
f31cc962	38	static u32 errata;
f31cc962 MK	39
	40	static struct omap_dma_dev_attr *d;
	41
ad0c381a	42	static enum omap_reg_offsets dma_common_ch_end;
f31cc962	43
64a2dc3d RK	44	static const struct omap_dma_reg reg_map[] = {
	45	[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
	46	[GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
	47	[IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
	48	[IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
	49	[IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
	50	[IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
	51	[IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
	52	[IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
	53	[IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
	54	[IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
	55	[SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
	56	[OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
	57	[CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
	58	[CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
	59	[CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
	60	[CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
f31cc962 MK	61
f31cc962 MK	62	/* Common register offsets */
64a2dc3d RK	63	[CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
	64	[CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
	65	[CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
	66	[CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
	67	[CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
	68	[CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
	69	[CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
	70	[CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
	71	[CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
	72	[CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
	73	[CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
	74	[CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
	75	[CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	76
f31cc962 MK	77	/* Channel specific register offsets */
64a2dc3d RK	78	[CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
	79	[CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
	80	[CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
	81	[CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
	82	[COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	83
f31cc962 MK	84	/* OMAP4 specific registers */
64a2dc3d RK	85	[CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
	86	[CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
	87	[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	88	};
f31cc962 MK	89
f31cc962 MK	90	static void __iomem *dma_base;
	91	static inline void dma_write(u32 val, int reg, int lch)
	92	{
64a2dc3d RK	93	void __iomem *addr = dma_base;
	94
	95	addr += reg_map[reg].offset;
	96	addr += reg_map[reg].stride * lch;
f31cc962	97
64a2dc3d	98	__raw_writel(val, addr);
f31cc962 MK	99	}
	100
	101	static inline u32 dma_read(int reg, int lch)
	102	{
64a2dc3d RK	103	void __iomem *addr = dma_base;
	104
	105	addr += reg_map[reg].offset;
	106	addr += reg_map[reg].stride * lch;
f31cc962	107
64a2dc3d	108	return __raw_readl(addr);
f31cc962 MK	109	}
f31cc962 MK	110
f31cc962 MK	111	static void omap2_clear_dma(int lch)
f31cc962 MK	112	{
ad0c381a	113	int i;
f31cc962	114
ad0c381a	115	for (i = CSDP; i <= dma_common_ch_end; i += 1)
f31cc962 MK	116	dma_write(0, i, lch);
	117	}
	118
	119	static void omap2_show_dma_caps(void)
	120	{
	121	u8 revision = dma_read(REVISION, 0) & 0xff;
	122	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
	123	revision >> 4, revision & 0xf);
	124	return;
	125	}
	126
	127	static u32 configure_dma_errata(void)
	128	{
	129
	130	/*
	131	* Errata applicable for OMAP2430ES1.0 and all omap2420
	132	*
	133	* I.
	134	* Erratum ID: Not Available
	135	* Inter Frame DMA buffering issue DMA will wrongly
	136	* buffer elements if packing and bursting is enabled. This might
	137	* result in data gets stalled in FIFO at the end of the block.
	138	* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
	139	* guarantee no data will stay in the DMA FIFO in case inter frame
	140	* buffering occurs
	141	*
	142	* II.
	143	* Erratum ID: Not Available
	144	* DMA may hang when several channels are used in parallel
	145	* In the following configuration, DMA channel hanging can occur:
	146	* a. Channel i, hardware synchronized, is enabled
	147	* b. Another channel (Channel x), software synchronized, is enabled.
	148	* c. Channel i is disabled before end of transfer
	149	* d. Channel i is reenabled.
	150	* e. Steps 1 to 4 are repeated a certain number of times.
	151	* f. A third channel (Channel y), software synchronized, is enabled.
	152	* Channel x and Channel y may hang immediately after step 'f'.
	153	* Workaround:
	154	* For any channel used - make sure NextLCH_ID is set to the value j.
	155	*/
	156	if (cpu_is_omap2420() \|\| (cpu_is_omap2430() &&
	157	(omap_type() == OMAP2430_REV_ES1_0))) {
	158
	159	SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
	160	SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
	161	}
	162
	163	/*
	164	* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
	165	* after a transaction error.
	166	* Workaround: SW should explicitely disable the channel.
	167	*/
	168	if (cpu_class_is_omap2())
	169	SET_DMA_ERRATA(DMA_ERRATA_i378);
	170
	171	/*
	172	* Erratum ID: i541: sDMA FIFO draining does not finish
	173	* If sDMA channel is disabled on the fly, sDMA enters standby even
	174	* through FIFO Drain is still in progress
	175	* Workaround: Put sDMA in NoStandby more before a logical channel is
	176	* disabled, then put it back to SmartStandby right after the channel
	177	* finishes FIFO draining.
	178	*/
	179	if (cpu_is_omap34xx())
180	SET_DMA_ERRATA(DMA_ERRATA_i541);
181
182	/*
183	* Erratum ID: i88 : Special programming model needed to disable DMA
184	* before end of block.
185	* Workaround: software must ensure that the DMA is configured in No
186	* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
187	*/
188	if (omap_type() == OMAP3430_REV_ES1_0)
189	SET_DMA_ERRATA(DMA_ERRATA_i88);
190
191	/*
192	* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
193	* read before the DMA controller finished disabling the channel.
194	*/
195	SET_DMA_ERRATA(DMA_ERRATA_3_3);
196
197	/*
198	* Erratum ID: Not Available
199	* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
200	* after secure sram context save and restore.
201	* Work around: Hence we need to manually clear those IRQs to avoid
202	* spurious interrupts. This affects only secure devices.
203	*/
204	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
205	SET_DMA_ERRATA(DMA_ROMCODE_BUG);
206
207	return errata;
208	}
209
59de3cf1 MK	210	/* One time initializations */
	211	static int __init omap2_system_dma_init_dev(struct omap_hwmod oh, void unused)
	212	{
3528c58e	213	struct platform_device *pdev;
59de3cf1	214	struct omap_system_dma_plat_info *p;
f31cc962	215	struct resource *mem;
59de3cf1 MK	216	char *name = "omap_dma_system";
	217
	218	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
	219	if (!p) {
	220	pr_err("%s: Unable to allocate pdata for %s:%s\n",
	221	__func__, name, oh->name);
	222	return -ENOMEM;
	223	}
	224
f31cc962	225	p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
f31cc962 MK	226	p->show_dma_caps = omap2_show_dma_caps;
	227	p->clear_dma = omap2_clear_dma;
	228	p->dma_write = dma_write;
	229	p->dma_read = dma_read;
	230
	231	p->clear_lch_regs = NULL;
	232
	233	p->errata = configure_dma_errata();
	234
c1d1cd59	235	pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
59de3cf1	236	kfree(p);
3528c58e	237	if (IS_ERR(pdev)) {
25985edc	238	pr_err("%s: Can't build omap_device for %s:%s.\n",
59de3cf1	239	__func__, name, oh->name);
3528c58e	240	return PTR_ERR(pdev);
59de3cf1 MK	241	}
59de3cf1 MK	242
3528c58e	243	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f31cc962	244	if (!mem) {
3528c58e	245	dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
f31cc962 MK	246	return -EINVAL;
	247	}
	248	dma_base = ioremap(mem->start, resource_size(mem));
	249	if (!dma_base) {
3528c58e	250	dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
f31cc962 MK	251	return -ENOMEM;
	252	}
	253
	254	d = oh->dev_attr;
	255	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
	256	(d->lch_count), GFP_KERNEL);
	257
	258	if (!d->chan) {
3528c58e	259	dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
f31cc962 MK	260	return -ENOMEM;
f31cc962 MK	261	}
f6d5e079	262
82809601 TL	263	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
	264	d->dev_caps \|= HS_CHANNELS_RESERVED;
	265
f6d5e079 S	266	/* Check the capabilities register for descriptor loading feature */
	267	if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
	268	dma_common_ch_end = CCDN;
	269	else
	270	dma_common_ch_end = CCFN;
	271
59de3cf1 MK	272	return 0;
	273	}
	274
be1f9481 TL	275	static const struct platform_device_info omap_dma_dev_info = {
	276	.name = "omap-dma-engine",
	277	.id = -1,
	278	.dma_mask = DMA_BIT_MASK(32),
	279	};
	280
59de3cf1 MK	281	static int __init omap2_system_dma_init(void)
59de3cf1 MK	282	{
be1f9481 TL	283	struct platform_device *pdev;
	284	int res;
	285
	286	res = omap_hwmod_for_each_by_class("dma",
59de3cf1	287	omap2_system_dma_init_dev, NULL);
be1f9481 TL	288	if (res)
	289	return res;
	290
8d30662a JH	291	if (of_have_populated_dt())
	292	return res;
	293
be1f9481 TL	294	pdev = platform_device_register_full(&omap_dma_dev_info);
	295	if (IS_ERR(pdev))
	296	return PTR_ERR(pdev);
	297
	298	return res;
59de3cf1	299	}
b76c8b19	300	omap_arch_initcall(omap2_system_dma_init);