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a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
358965d7 RW |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
a1391d27 RN |
6 | * |
7 | * Written by Paul Walmsley | |
358965d7 RW |
8 | * Testing and integration fixes by Jouni Högander |
9 | * | |
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | |
11 | * Menon | |
a1391d27 RN |
12 | * |
13 | * Parts of this code are based on code written by | |
14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
a1391d27 RN |
21 | #include <linux/kernel.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/io.h> | |
a1391d27 RN |
28 | #include <linux/bitops.h> |
29 | ||
16975a79 RN |
30 | #include <plat/cpu.h> |
31 | #include <plat/clock.h> | |
a1391d27 RN |
32 | #include <asm/clkdev.h> |
33 | ||
34 | #include "clock.h" | |
35 | #include "prm.h" | |
36 | #include "prm-regbits-34xx.h" | |
37 | #include "cm.h" | |
38 | #include "cm-regbits-34xx.h" | |
39 | ||
40 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
41 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
42 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
43 | ||
44 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
45 | ||
60c3f651 | 46 | /* Private functions */ |
a1391d27 RN |
47 | |
48 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
49 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | |
50 | { | |
51 | const struct dpll_data *dd; | |
52 | u32 v; | |
53 | ||
54 | dd = clk->dpll_data; | |
55 | ||
56 | v = __raw_readl(dd->control_reg); | |
57 | v &= ~dd->enable_mask; | |
58 | v |= clken_bits << __ffs(dd->enable_mask); | |
59 | __raw_writel(v, dd->control_reg); | |
60 | } | |
61 | ||
62 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
63 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |
64 | { | |
65 | const struct dpll_data *dd; | |
66 | int i = 0; | |
67 | int ret = -EINVAL; | |
68 | ||
69 | dd = clk->dpll_data; | |
70 | ||
71 | state <<= __ffs(dd->idlest_mask); | |
72 | ||
73 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | |
74 | i < MAX_DPLL_WAIT_TRIES) { | |
75 | i++; | |
76 | udelay(1); | |
77 | } | |
78 | ||
79 | if (i == MAX_DPLL_WAIT_TRIES) { | |
80 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
81 | clk->name, (state) ? "locked" : "bypassed"); | |
82 | } else { | |
83 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
84 | clk->name, (state) ? "locked" : "bypassed", i); | |
85 | ||
86 | ret = 0; | |
87 | } | |
88 | ||
89 | return ret; | |
90 | } | |
91 | ||
92 | /* From 3430 TRM ES2 4.7.6.2 */ | |
93 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |
94 | { | |
95 | unsigned long fint; | |
96 | u16 f = 0; | |
97 | ||
98 | fint = clk->dpll_data->clk_ref->rate / n; | |
99 | ||
100 | pr_debug("clock: fint is %lu\n", fint); | |
101 | ||
102 | if (fint >= 750000 && fint <= 1000000) | |
103 | f = 0x3; | |
104 | else if (fint > 1000000 && fint <= 1250000) | |
105 | f = 0x4; | |
106 | else if (fint > 1250000 && fint <= 1500000) | |
107 | f = 0x5; | |
108 | else if (fint > 1500000 && fint <= 1750000) | |
109 | f = 0x6; | |
110 | else if (fint > 1750000 && fint <= 2100000) | |
111 | f = 0x7; | |
112 | else if (fint > 7500000 && fint <= 10000000) | |
113 | f = 0xB; | |
114 | else if (fint > 10000000 && fint <= 12500000) | |
115 | f = 0xC; | |
116 | else if (fint > 12500000 && fint <= 15000000) | |
117 | f = 0xD; | |
118 | else if (fint > 15000000 && fint <= 17500000) | |
119 | f = 0xE; | |
120 | else if (fint > 17500000 && fint <= 21000000) | |
121 | f = 0xF; | |
122 | else | |
123 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
124 | ||
125 | return f; | |
126 | } | |
127 | ||
a1391d27 RN |
128 | /* |
129 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
130 | * @clk: pointer to a DPLL struct clk | |
131 | * | |
132 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
133 | * readiness before returning. Will save and restore the DPLL's | |
134 | * autoidle state across the enable, per the CDP code. If the DPLL | |
135 | * locked successfully, return 0; if the DPLL did not lock in the time | |
136 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
137 | */ | |
138 | static int _omap3_noncore_dpll_lock(struct clk *clk) | |
139 | { | |
140 | u8 ai; | |
141 | int r; | |
142 | ||
143 | pr_debug("clock: locking DPLL %s\n", clk->name); | |
144 | ||
145 | ai = omap3_dpll_autoidle_read(clk); | |
146 | ||
147 | omap3_dpll_deny_idle(clk); | |
148 | ||
149 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
150 | ||
151 | r = _omap3_wait_dpll_status(clk, 1); | |
152 | ||
153 | if (ai) | |
154 | omap3_dpll_allow_idle(clk); | |
155 | ||
156 | return r; | |
157 | } | |
158 | ||
159 | /* | |
160 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
161 | * @clk: pointer to a DPLL struct clk | |
162 | * | |
163 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
164 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
165 | * rate. Waits for the DPLL to report readiness before returning. | |
166 | * Will save and restore the DPLL's autoidle state across the enable, | |
167 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
168 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
169 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
170 | * return -EINVAL. | |
171 | */ | |
172 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | |
173 | { | |
174 | int r; | |
175 | u8 ai; | |
176 | ||
177 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
178 | return -EINVAL; | |
179 | ||
180 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
181 | clk->name); | |
182 | ||
183 | ai = omap3_dpll_autoidle_read(clk); | |
184 | ||
185 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
186 | ||
187 | r = _omap3_wait_dpll_status(clk, 0); | |
188 | ||
189 | if (ai) | |
190 | omap3_dpll_allow_idle(clk); | |
191 | else | |
192 | omap3_dpll_deny_idle(clk); | |
193 | ||
194 | return r; | |
195 | } | |
196 | ||
197 | /* | |
198 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
199 | * @clk: pointer to a DPLL struct clk | |
200 | * | |
201 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
202 | * restore the DPLL's autoidle state across the stop, per the CDP | |
203 | * code. If DPLL3 was passed in, or the DPLL does not support | |
204 | * low-power stop, return -EINVAL; otherwise, return 0. | |
205 | */ | |
206 | static int _omap3_noncore_dpll_stop(struct clk *clk) | |
207 | { | |
208 | u8 ai; | |
209 | ||
210 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
211 | return -EINVAL; | |
212 | ||
213 | pr_debug("clock: stopping DPLL %s\n", clk->name); | |
214 | ||
215 | ai = omap3_dpll_autoidle_read(clk); | |
216 | ||
217 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
218 | ||
219 | if (ai) | |
220 | omap3_dpll_allow_idle(clk); | |
221 | else | |
222 | omap3_dpll_deny_idle(clk); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
358965d7 RW |
227 | /** |
228 | * lookup_dco_sddiv - Set j-type DPLL4 compensation variables | |
229 | * @clk: pointer to a DPLL struct clk | |
230 | * @dco: digital control oscillator selector | |
231 | * @sd_div: target sigma-delta divider | |
232 | * @m: DPLL multiplier to set | |
233 | * @n: DPLL divider to set | |
234 | * | |
235 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
236 | * | |
237 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
238 | * out in non-multi-OMAP builds for those chips? | |
239 | */ | |
240 | static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | |
241 | u8 n) | |
242 | { | |
243 | unsigned long fint, clkinp, sd; /* watch out for overflow */ | |
244 | int mod1, mod2; | |
245 | ||
246 | clkinp = clk->parent->rate; | |
247 | fint = (clkinp / n) * m; | |
248 | ||
249 | if (fint < 1000000000) | |
250 | *dco = 2; | |
251 | else | |
252 | *dco = 4; | |
253 | /* | |
254 | * target sigma-delta to near 250MHz | |
255 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | |
256 | */ | |
257 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | |
258 | mod1 = (clkinp * m) % (250 * n); | |
259 | sd = (clkinp * m) / (250 * n); | |
260 | mod2 = sd % 10; | |
261 | sd /= 10; | |
262 | ||
263 | if (mod1 || mod2) | |
264 | sd++; | |
265 | *sd_div = sd; | |
266 | } | |
267 | ||
60c3f651 PW |
268 | /* |
269 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
270 | * @clk: struct clk * of DPLL to set | |
271 | * @m: DPLL multiplier to set | |
272 | * @n: DPLL divider to set | |
273 | * @freqsel: FREQSEL value to set | |
274 | * | |
275 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | |
276 | * lock.. Returns -EINVAL upon error, or 0 upon success. | |
277 | */ | |
278 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |
279 | { | |
280 | struct dpll_data *dd = clk->dpll_data; | |
281 | u32 v; | |
282 | ||
283 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
284 | _omap3_noncore_dpll_bypass(clk); | |
285 | ||
5eb75f55 VB |
286 | /* |
287 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | |
288 | * since freqsel field is no longer present | |
289 | */ | |
290 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
60c3f651 PW |
291 | v = __raw_readl(dd->control_reg); |
292 | v &= ~dd->freqsel_mask; | |
293 | v |= freqsel << __ffs(dd->freqsel_mask); | |
294 | __raw_writel(v, dd->control_reg); | |
295 | } | |
296 | ||
297 | /* Set DPLL multiplier, divider */ | |
298 | v = __raw_readl(dd->mult_div1_reg); | |
299 | v &= ~(dd->mult_mask | dd->div1_mask); | |
300 | v |= m << __ffs(dd->mult_mask); | |
301 | v |= (n - 1) << __ffs(dd->div1_mask); | |
358965d7 RW |
302 | |
303 | /* | |
304 | * XXX This code is not needed for 3430/AM35XX; can it be optimized | |
305 | * out in non-multi-OMAP builds for those chips? | |
306 | */ | |
307 | if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { | |
308 | u8 dco, sd_div; | |
309 | lookup_dco_sddiv(clk, &dco, &sd_div, m, n); | |
310 | /* XXX This probably will need revision for OMAP4 */ | |
311 | v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK | |
312 | | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | |
313 | v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); | |
314 | v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | |
315 | } | |
316 | ||
60c3f651 PW |
317 | __raw_writel(v, dd->mult_div1_reg); |
318 | ||
319 | /* We let the clock framework set the other output dividers later */ | |
320 | ||
321 | /* REVISIT: Set ramp-up delay? */ | |
322 | ||
323 | _omap3_noncore_dpll_lock(clk); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | /* Public functions */ | |
329 | ||
330 | /** | |
331 | * omap3_dpll_recalc - recalculate DPLL rate | |
332 | * @clk: DPLL struct clk | |
333 | * | |
334 | * Recalculate and propagate the DPLL rate. | |
335 | */ | |
336 | unsigned long omap3_dpll_recalc(struct clk *clk) | |
337 | { | |
338 | return omap2_get_dpll_rate(clk); | |
339 | } | |
340 | ||
341 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
342 | ||
a1391d27 RN |
343 | /** |
344 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
345 | * @clk: pointer to a DPLL struct clk | |
346 | * | |
347 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
348 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
349 | * the same as the DPLL's parent clock, it will enter bypass; | |
350 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
351 | * indicate readiness before returning, unless the DPLL takes too long | |
352 | * to enter the target state. Intended to be used as the struct clk's | |
353 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
354 | * support low-power stop, or if the DPLL took too long to enter | |
355 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
356 | */ | |
357 | int omap3_noncore_dpll_enable(struct clk *clk) | |
358 | { | |
359 | int r; | |
360 | struct dpll_data *dd; | |
361 | ||
362 | dd = clk->dpll_data; | |
363 | if (!dd) | |
364 | return -EINVAL; | |
365 | ||
366 | if (clk->rate == dd->clk_bypass->rate) { | |
367 | WARN_ON(clk->parent != dd->clk_bypass); | |
368 | r = _omap3_noncore_dpll_bypass(clk); | |
369 | } else { | |
370 | WARN_ON(clk->parent != dd->clk_ref); | |
371 | r = _omap3_noncore_dpll_lock(clk); | |
372 | } | |
373 | /* | |
374 | *FIXME: this is dubious - if clk->rate has changed, what about | |
375 | * propagating? | |
376 | */ | |
377 | if (!r) | |
378 | clk->rate = omap2_get_dpll_rate(clk); | |
379 | ||
380 | return r; | |
381 | } | |
382 | ||
383 | /** | |
384 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
385 | * @clk: pointer to a DPLL struct clk | |
386 | * | |
387 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
388 | * intended for use in struct clkops. No return value. | |
389 | */ | |
390 | void omap3_noncore_dpll_disable(struct clk *clk) | |
391 | { | |
392 | _omap3_noncore_dpll_stop(clk); | |
393 | } | |
394 | ||
395 | ||
396 | /* Non-CORE DPLL rate set code */ | |
397 | ||
a1391d27 RN |
398 | /** |
399 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
400 | * @clk: struct clk * of DPLL to set | |
401 | * @rate: rounded target rate | |
402 | * | |
403 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | |
404 | * low-power bypass, and the target rate is the bypass source clock | |
405 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
406 | * target rate if it hasn't been done already, then program and lock | |
407 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
408 | */ | |
409 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |
410 | { | |
411 | struct clk *new_parent = NULL; | |
16975a79 | 412 | u16 freqsel = 0; |
a1391d27 RN |
413 | struct dpll_data *dd; |
414 | int ret; | |
415 | ||
416 | if (!clk || !rate) | |
417 | return -EINVAL; | |
418 | ||
419 | dd = clk->dpll_data; | |
420 | if (!dd) | |
421 | return -EINVAL; | |
422 | ||
423 | if (rate == omap2_get_dpll_rate(clk)) | |
424 | return 0; | |
425 | ||
426 | /* | |
427 | * Ensure both the bypass and ref clocks are enabled prior to | |
428 | * doing anything; we need the bypass clock running to reprogram | |
429 | * the DPLL. | |
430 | */ | |
431 | omap2_clk_enable(dd->clk_bypass); | |
432 | omap2_clk_enable(dd->clk_ref); | |
433 | ||
434 | if (dd->clk_bypass->rate == rate && | |
435 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | |
436 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | |
437 | ||
438 | ret = _omap3_noncore_dpll_bypass(clk); | |
439 | if (!ret) | |
440 | new_parent = dd->clk_bypass; | |
441 | } else { | |
442 | if (dd->last_rounded_rate != rate) | |
443 | omap2_dpll_round_rate(clk, rate); | |
444 | ||
445 | if (dd->last_rounded_rate == 0) | |
446 | return -EINVAL; | |
447 | ||
5eb75f55 VB |
448 | /* No freqsel on OMAP4 and OMAP3630 */ |
449 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
16975a79 RN |
450 | freqsel = _omap3_dpll_compute_freqsel(clk, |
451 | dd->last_rounded_n); | |
452 | if (!freqsel) | |
453 | WARN_ON(1); | |
454 | } | |
a1391d27 RN |
455 | |
456 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | |
457 | clk->name, rate); | |
458 | ||
459 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | |
460 | dd->last_rounded_n, freqsel); | |
461 | if (!ret) | |
462 | new_parent = dd->clk_ref; | |
463 | } | |
464 | if (!ret) { | |
465 | /* | |
466 | * Switch the parent clock in the heirarchy, and make sure | |
467 | * that the new parent's usecount is correct. Note: we | |
468 | * enable the new parent before disabling the old to avoid | |
469 | * any unnecessary hardware disable->enable transitions. | |
470 | */ | |
471 | if (clk->usecount) { | |
472 | omap2_clk_enable(new_parent); | |
473 | omap2_clk_disable(clk->parent); | |
474 | } | |
475 | clk_reparent(clk, new_parent); | |
476 | clk->rate = rate; | |
477 | } | |
478 | omap2_clk_disable(dd->clk_ref); | |
479 | omap2_clk_disable(dd->clk_bypass); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | /* DPLL autoidle read/set code */ | |
485 | ||
486 | /** | |
487 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
488 | * @clk: struct clk * of the DPLL to read | |
489 | * | |
490 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
491 | * -EINVAL if passed a null pointer or if the struct clk does not | |
492 | * appear to refer to a DPLL. | |
493 | */ | |
494 | u32 omap3_dpll_autoidle_read(struct clk *clk) | |
495 | { | |
496 | const struct dpll_data *dd; | |
497 | u32 v; | |
498 | ||
499 | if (!clk || !clk->dpll_data) | |
500 | return -EINVAL; | |
501 | ||
502 | dd = clk->dpll_data; | |
503 | ||
504 | v = __raw_readl(dd->autoidle_reg); | |
505 | v &= dd->autoidle_mask; | |
506 | v >>= __ffs(dd->autoidle_mask); | |
507 | ||
508 | return v; | |
509 | } | |
510 | ||
511 | /** | |
512 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
513 | * @clk: struct clk * of the DPLL to operate on | |
514 | * | |
515 | * Enable DPLL automatic idle control. This automatic idle mode | |
516 | * switching takes effect only when the DPLL is locked, at least on | |
517 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
518 | * clocks are gated. No return value. | |
519 | */ | |
520 | void omap3_dpll_allow_idle(struct clk *clk) | |
521 | { | |
522 | const struct dpll_data *dd; | |
523 | u32 v; | |
524 | ||
525 | if (!clk || !clk->dpll_data) | |
526 | return; | |
527 | ||
528 | dd = clk->dpll_data; | |
529 | ||
530 | /* | |
531 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
532 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
533 | * optionally enter this mode. | |
534 | */ | |
535 | v = __raw_readl(dd->autoidle_reg); | |
536 | v &= ~dd->autoidle_mask; | |
537 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
538 | __raw_writel(v, dd->autoidle_reg); | |
539 | } | |
540 | ||
541 | /** | |
542 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
543 | * @clk: struct clk * of the DPLL to operate on | |
544 | * | |
545 | * Disable DPLL automatic idle control. No return value. | |
546 | */ | |
547 | void omap3_dpll_deny_idle(struct clk *clk) | |
548 | { | |
549 | const struct dpll_data *dd; | |
550 | u32 v; | |
551 | ||
552 | if (!clk || !clk->dpll_data) | |
553 | return; | |
554 | ||
555 | dd = clk->dpll_data; | |
556 | ||
557 | v = __raw_readl(dd->autoidle_reg); | |
558 | v &= ~dd->autoidle_mask; | |
559 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
560 | __raw_writel(v, dd->autoidle_reg); | |
561 | ||
562 | } | |
563 | ||
564 | /* Clock control for DPLL outputs */ | |
565 | ||
566 | /** | |
567 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
568 | * @clk: DPLL output struct clk | |
569 | * | |
570 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
571 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
572 | */ | |
573 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |
574 | { | |
575 | const struct dpll_data *dd; | |
576 | unsigned long rate; | |
577 | u32 v; | |
578 | struct clk *pclk; | |
579 | ||
580 | /* Walk up the parents of clk, looking for a DPLL */ | |
581 | pclk = clk->parent; | |
582 | while (pclk && !pclk->dpll_data) | |
583 | pclk = pclk->parent; | |
584 | ||
585 | /* clk does not have a DPLL as a parent? */ | |
586 | WARN_ON(!pclk); | |
587 | ||
588 | dd = pclk->dpll_data; | |
589 | ||
590 | WARN_ON(!dd->enable_mask); | |
591 | ||
592 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | |
593 | v >>= __ffs(dd->enable_mask); | |
358965d7 | 594 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
a1391d27 RN |
595 | rate = clk->parent->rate; |
596 | else | |
597 | rate = clk->parent->rate * 2; | |
598 | return rate; | |
599 | } |