Commit | Line | Data |
---|---|---|
97f67898 RN |
1 | /* |
2 | * OMAP4-specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Rajendra Nayak | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/bitops.h> | |
17 | ||
dbc04161 | 18 | #include "soc.h" |
97f67898 | 19 | #include "clock.h" |
a1900f2e | 20 | #include "clock44xx.h" |
97f67898 RN |
21 | #include "cm-regbits-44xx.h" |
22 | ||
3ff51ed8 JH |
23 | /* |
24 | * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that | |
25 | * can supported when using the DPLL low-power mode. Frequencies are | |
26 | * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, | |
27 | * Status, and Low-Power Operation Mode". | |
28 | */ | |
29 | #define OMAP4_DPLL_LP_FINT_MAX 1000000 | |
30 | #define OMAP4_DPLL_LP_FOUT_MAX 100000000 | |
31 | ||
97f67898 | 32 | /* Supported only on OMAP4 */ |
32cc0021 | 33 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) |
97f67898 RN |
34 | { |
35 | u32 v; | |
36 | u32 mask; | |
37 | ||
38 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
39 | return -EINVAL; | |
40 | ||
41 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
42 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
43 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
44 | ||
45 | v = __raw_readl(clk->clksel_reg); | |
46 | v &= mask; | |
47 | v >>= __ffs(mask); | |
48 | ||
49 | return v; | |
50 | } | |
51 | ||
32cc0021 | 52 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
53 | { |
54 | u32 v; | |
55 | u32 mask; | |
56 | ||
57 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
58 | return; | |
59 | ||
60 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
61 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
62 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
63 | ||
64 | v = __raw_readl(clk->clksel_reg); | |
65 | /* Clear the bit to allow gatectrl */ | |
66 | v &= ~mask; | |
67 | __raw_writel(v, clk->clksel_reg); | |
68 | } | |
69 | ||
32cc0021 | 70 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
71 | { |
72 | u32 v; | |
73 | u32 mask; | |
74 | ||
75 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
76 | return; | |
77 | ||
78 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
79 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
80 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
81 | ||
82 | v = __raw_readl(clk->clksel_reg); | |
83 | /* Set the bit to deny gatectrl */ | |
84 | v |= mask; | |
85 | __raw_writel(v, clk->clksel_reg); | |
86 | } | |
70db8a62 | 87 | |
32cc0021 MT |
88 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { |
89 | .allow_idle = omap4_dpllmx_allow_gatectrl, | |
90 | .deny_idle = omap4_dpllmx_deny_gatectrl, | |
91 | }; | |
70db8a62 | 92 | |
3ff51ed8 JH |
93 | /** |
94 | * omap4_dpll_lpmode_recalc - compute DPLL low-power setting | |
95 | * @dd: pointer to the dpll data structure | |
96 | * | |
97 | * Calculates if low-power mode can be enabled based upon the last | |
98 | * multiplier and divider values calculated. If low-power mode can be | |
99 | * enabled, then the bit to enable low-power mode is stored in the | |
100 | * last_rounded_lpmode variable. This implementation is based upon the | |
101 | * criteria for enabling low-power mode as described in the OMAP4430/60 | |
102 | * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power | |
103 | * Operation Mode". | |
104 | */ | |
105 | static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) | |
106 | { | |
107 | long fint, fout; | |
108 | ||
109 | fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); | |
110 | fout = fint * dd->last_rounded_m; | |
111 | ||
112 | if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) | |
113 | dd->last_rounded_lpmode = 1; | |
114 | else | |
115 | dd->last_rounded_lpmode = 0; | |
116 | } | |
117 | ||
a1900f2e MT |
118 | /** |
119 | * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit | |
120 | * @clk: struct clk * of the DPLL to compute the rate for | |
121 | * | |
122 | * Compute the output rate for the OMAP4 DPLL represented by @clk. | |
123 | * Takes the REGM4XEN bit into consideration, which is needed for the | |
124 | * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) | |
125 | * upon success, or 0 upon error. | |
126 | */ | |
32cc0021 MT |
127 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
128 | unsigned long parent_rate) | |
129 | { | |
130 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
131 | u32 v; |
132 | unsigned long rate; | |
133 | struct dpll_data *dd; | |
134 | ||
135 | if (!clk || !clk->dpll_data) | |
136 | return 0; | |
137 | ||
138 | dd = clk->dpll_data; | |
139 | ||
140 | rate = omap2_get_dpll_rate(clk); | |
141 | ||
142 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | |
143 | v = __raw_readl(dd->control_reg); | |
144 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) | |
145 | rate *= OMAP4430_REGM4XEN_MULT; | |
146 | ||
147 | return rate; | |
148 | } | |
149 | ||
150 | /** | |
151 | * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit | |
152 | * @clk: struct clk * of the DPLL to round a rate for | |
153 | * @target_rate: the desired rate of the DPLL | |
154 | * | |
155 | * Compute the rate that would be programmed into the DPLL hardware | |
156 | * for @clk if set_rate() were to be provided with the rate | |
157 | * @target_rate. Takes the REGM4XEN bit into consideration, which is | |
158 | * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before | |
159 | * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or | |
160 | * ~0 if an error occurred in omap2_dpll_round_rate(). | |
161 | */ | |
32cc0021 MT |
162 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
163 | unsigned long target_rate, | |
164 | unsigned long *parent_rate) | |
165 | { | |
166 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
167 | struct dpll_data *dd; |
168 | long r; | |
169 | ||
170 | if (!clk || !clk->dpll_data) | |
171 | return -EINVAL; | |
172 | ||
173 | dd = clk->dpll_data; | |
174 | ||
3ff51ed8 | 175 | dd->last_rounded_m4xen = 0; |
a1900f2e | 176 | |
3ff51ed8 JH |
177 | /* |
178 | * First try to compute the DPLL configuration for | |
179 | * target rate without using the 4X multiplier. | |
180 | */ | |
32cc0021 | 181 | r = omap2_dpll_round_rate(hw, target_rate, NULL); |
3ff51ed8 JH |
182 | if (r != ~0) |
183 | goto out; | |
184 | ||
185 | /* | |
186 | * If we did not find a valid DPLL configuration, try again, but | |
187 | * this time see if using the 4X multiplier can help. Enabling the | |
188 | * 4X multiplier is equivalent to dividing the target rate by 4. | |
189 | */ | |
190 | r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, | |
191 | NULL); | |
a1900f2e MT |
192 | if (r == ~0) |
193 | return r; | |
194 | ||
3ff51ed8 JH |
195 | dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; |
196 | dd->last_rounded_m4xen = 1; | |
197 | ||
198 | out: | |
199 | omap4_dpll_lpmode_recalc(dd); | |
a1900f2e | 200 | |
3ff51ed8 | 201 | return dd->last_rounded_rate; |
a1900f2e | 202 | } |