[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc-onenand.c

/*
 * linux/arch/arm/mach-omap2/gpmc-onenand.c
 *
 * Copyright (C) 2006 - 2009 Nokia Corporation
 * Contacts:	Juha Yrjola
 *		Tony Lindgren
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/onenand_regs.h>
#include <linux/io.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <linux/err.h>

#include <asm/mach/flash.h>

#include "soc.h"

#define	ONENAND_IO_SIZE	SZ_128K

#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
#define	ONENAND_FLAG_HF		(1 << 2)
#define	ONENAND_FLAG_VHF	(1 << 3)

static unsigned onenand_flags;
static unsigned latency;

static struct omap_onenand_platform_data *gpmc_onenand_data;

static struct resource gpmc_onenand_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device gpmc_onenand_device = {
	.name		= "omap2-onenand",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &gpmc_onenand_resource,
};

static struct gpmc_settings onenand_async = {
	.device_width	= GPMC_DEVWIDTH_16BIT,
	.mux_add_data	= GPMC_MUX_AD,
};

static struct gpmc_settings onenand_sync = {
	.burst_read	= true,
	.burst_wrap	= true,
	.burst_len	= GPMC_BURST_16,
	.device_width	= GPMC_DEVWIDTH_16BIT,
	.mux_add_data	= GPMC_MUX_AD,
	.wait_pin	= 0,
};

static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
{
	struct gpmc_device_timings dev_t;
	const int t_cer = 15;
	const int t_avdp = 12;
	const int t_aavdh = 7;
	const int t_ce = 76;
	const int t_aa = 76;
	const int t_oe = 20;
	const int t_cez = 20; /* max of t_cez, t_oez */
	const int t_wpl = 40;
	const int t_wph = 30;

	memset(&dev_t, 0, sizeof(dev_t));

	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
	dev_t.t_avdp_w = dev_t.t_avdp_r;
	dev_t.t_aavdh = t_aavdh * 1000;
	dev_t.t_aa = t_aa * 1000;
	dev_t.t_ce = t_ce * 1000;
	dev_t.t_oe = t_oe * 1000;
	dev_t.t_cez_r = t_cez * 1000;
	dev_t.t_cez_w = dev_t.t_cez_r;
	dev_t.t_wpl = t_wpl * 1000;
	dev_t.t_wph = t_wph * 1000;

	gpmc_calc_timings(t, &onenand_async, &dev_t);
}

static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
{
	u32 reg;

	/* Ensure sync read and sync write are disabled */
	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}

static void set_onenand_cfg(void __iomem *onenand_base)
{
	u32 reg;

	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
		ONENAND_SYS_CFG1_BL_16;
	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
		reg |= ONENAND_SYS_CFG1_SYNC_READ;
	else
		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
	else
		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
	if (onenand_flags & ONENAND_FLAG_HF)
		reg |= ONENAND_SYS_CFG1_HF;
	else
		reg &= ~ONENAND_SYS_CFG1_HF;
	if (onenand_flags & ONENAND_FLAG_VHF)
		reg |= ONENAND_SYS_CFG1_VHF;
	else
		reg &= ~ONENAND_SYS_CFG1_VHF;
	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}

static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
				  void __iomem *onenand_base)
{
	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
	int freq;

	switch ((ver >> 4) & 0xf) {
	case 0:
		freq = 40;
		break;
	case 1:
		freq = 54;
		break;
	case 2:
		freq = 66;
		break;
	case 3:
		freq = 83;
		break;
	case 4:
		freq = 104;
		break;
	default:
		freq = 54;
		break;
	}

	return freq;
}

static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
					    unsigned int flags,
					    int freq)
{
	struct gpmc_device_timings dev_t;
	const int t_cer  = 15;
	const int t_avdp = 12;
	const int t_cez  = 20; /* max of t_cez, t_oez */
	const int t_wpl  = 40;
	const int t_wph  = 30;
	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
	int div, gpmc_clk_ns;

	if (flags & ONENAND_SYNC_READ)
		onenand_flags = ONENAND_FLAG_SYNCREAD;
	else if (flags & ONENAND_SYNC_READWRITE)
		onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;

	switch (freq) {
	case 104:
		min_gpmc_clk_period = 9600; /* 104 MHz */
		t_ces   = 3;
		t_avds  = 4;
		t_avdh  = 2;
		t_ach   = 3;
		t_aavdh = 6;
		t_rdyo  = 6;
		break;
	case 83:
		min_gpmc_clk_period = 12000; /* 83 MHz */
		t_ces   = 5;
		t_avds  = 4;
		t_avdh  = 2;
		t_ach   = 6;
		t_aavdh = 6;
		t_rdyo  = 9;
		break;
	case 66:
		min_gpmc_clk_period = 15000; /* 66 MHz */
		t_ces   = 6;
		t_avds  = 5;
		t_avdh  = 2;
		t_ach   = 6;
		t_aavdh = 6;
		t_rdyo  = 11;
		break;
	default:
		min_gpmc_clk_period = 18500; /* 54 MHz */
		t_ces   = 7;
		t_avds  = 7;
		t_avdh  = 7;
		t_ach   = 9;
		t_aavdh = 7;
		t_rdyo  = 15;
		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
		break;
	}

	div = gpmc_calc_divider(min_gpmc_clk_period);
	gpmc_clk_ns = gpmc_ticks_to_ns(div);
	if (gpmc_clk_ns < 15) /* >66MHz */
		onenand_flags |= ONENAND_FLAG_HF;
	else
		onenand_flags &= ~ONENAND_FLAG_HF;
	if (gpmc_clk_ns < 12) /* >83MHz */
		onenand_flags |= ONENAND_FLAG_VHF;
	else
		onenand_flags &= ~ONENAND_FLAG_VHF;
	if (onenand_flags & ONENAND_FLAG_VHF)
		latency = 8;
	else if (onenand_flags & ONENAND_FLAG_HF)
		latency = 6;
	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
		latency = 3;
	else
		latency = 4;

	/* Set synchronous read timings */
	memset(&dev_t, 0, sizeof(dev_t));

	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
		onenand_sync.sync_read = true;
	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
		onenand_sync.sync_write = true;
		onenand_sync.burst_write = true;
	} else {
		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
		dev_t.t_wpl = t_wpl * 1000;
		dev_t.t_wph = t_wph * 1000;
		dev_t.t_aavdh = t_aavdh * 1000;
	}
	dev_t.ce_xdelay = true;
	dev_t.avd_xdelay = true;
	dev_t.oe_xdelay = true;
	dev_t.we_xdelay = true;
	dev_t.clk = min_gpmc_clk_period;
	dev_t.t_bacc = dev_t.clk;
	dev_t.t_ces = t_ces * 1000;
	dev_t.t_avds = t_avds * 1000;
	dev_t.t_avdh = t_avdh * 1000;
	dev_t.t_ach = t_ach * 1000;
	dev_t.cyc_iaa = (latency + 1);
	dev_t.t_cez_r = t_cez * 1000;
	dev_t.t_cez_w = dev_t.t_cez_r;
	dev_t.cyc_aavdh_oe = 1;
	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;

	gpmc_calc_timings(t, &onenand_sync, &dev_t);
}

static int omap2_onenand_setup_async(void __iomem *onenand_base)
{
	struct gpmc_timings t;
	int ret;

	if (gpmc_onenand_data->of_node) {
		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
				      &onenand_async);
		if (onenand_async.sync_read || onenand_async.sync_write) {
			if (onenand_async.sync_write)
				gpmc_onenand_data->flags |=
					ONENAND_SYNC_READWRITE;
			else
				gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
			onenand_async.sync_read = false;
			onenand_async.sync_write = false;
		}
	}

	omap2_onenand_set_async_mode(onenand_base);

	omap2_onenand_calc_async_timings(&t);

	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
	if (ret < 0)
		return ret;

	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
	if (ret < 0)
		return ret;

	omap2_onenand_set_async_mode(onenand_base);

	return 0;
}

static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
{
	int ret, freq = *freq_ptr;
	struct gpmc_timings t;

	if (!freq) {
		/* Very first call freq is not known */
		freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
		set_onenand_cfg(onenand_base);
	}

	if (gpmc_onenand_data->of_node) {
		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
				      &onenand_sync);
	} else {
		/*
		 * FIXME: Appears to be legacy code from initial ONENAND commit.
		 * Unclear what boards this is for and if this can be removed.
		 */
		if (!cpu_is_omap34xx())
			onenand_sync.wait_on_read = true;
	}

	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);

	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
	if (ret < 0)
		return ret;

	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
	if (ret < 0)
		return ret;

	set_onenand_cfg(onenand_base);

	*freq_ptr = freq;

	return 0;
}

static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
{
	struct device *dev = &gpmc_onenand_device.dev;
	unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
	int ret;

	ret = omap2_onenand_setup_async(onenand_base);
	if (ret) {
		dev_err(dev, "unable to set to async mode\n");
		return ret;
	}

	if (!(gpmc_onenand_data->flags & l))
		return 0;

	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
	if (ret)
		dev_err(dev, "unable to set to sync mode\n");
	return ret;
}

void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
{
	int err;
	struct device *dev = &gpmc_onenand_device.dev;

	gpmc_onenand_data = _onenand_data;
	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;

	if (cpu_is_omap24xx() &&
			(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
		dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
		gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
		gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
	}

	if (cpu_is_omap34xx())
		gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
	else
		gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;

	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
				(unsigned long *)&gpmc_onenand_resource.start);
	if (err < 0) {
		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
			gpmc_onenand_data->cs, err);
		return;
	}

	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
							ONENAND_IO_SIZE - 1;

	if (platform_device_register(&gpmc_onenand_device) < 0) {
		dev_err(dev, "Unable to register OneNAND device\n");
		gpmc_cs_free(gpmc_onenand_data->cs);
		return;
	}
}
Commit	Line	Data
aa62e90f JY	1	/*
	2	* linux/arch/arm/mach-omap2/gpmc-onenand.c
	3	*
	4	* Copyright (C) 2006 - 2009 Nokia Corporation
	5	* Contacts: Juha Yrjola
	6	* Tony Lindgren
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
d44b28c4	13	#include <linux/string.h>
aa62e90f JY	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/mtd/onenand_regs.h>
	17	#include <linux/io.h>
e639cd5b	18	#include <linux/omap-gpmc.h>
2203747c	19	#include <linux/platform_data/mtd-onenand-omap2.h>
46376884	20	#include <linux/err.h>
aa62e90f JY	21
	22	#include <asm/mach/flash.h>
	23
dbc04161 TL	24	#include "soc.h"
dbc04161 TL	25
681988ba AM	26	#define ONENAND_IO_SIZE SZ_128K
681988ba AM	27
46376884 AM	28	#define ONENAND_FLAG_SYNCREAD (1 << 0)
	29	#define ONENAND_FLAG_SYNCWRITE (1 << 1)
	30	#define ONENAND_FLAG_HF (1 << 2)
	31	#define ONENAND_FLAG_VHF (1 << 3)
	32
	33	static unsigned onenand_flags;
	34	static unsigned latency;
46376884	35
aa62e90f JY	36	static struct omap_onenand_platform_data *gpmc_onenand_data;
aa62e90f JY	37
681988ba AM	38	static struct resource gpmc_onenand_resource = {
	39	.flags = IORESOURCE_MEM,
	40	};
	41
aa62e90f JY	42	static struct platform_device gpmc_onenand_device = {
	43	.name = "omap2-onenand",
	44	.id = -1,
681988ba AM	45	.num_resources = 1,
681988ba AM	46	.resource = &gpmc_onenand_resource,
aa62e90f JY	47	};
aa62e90f JY	48
c3be5b45	49	static struct gpmc_settings onenand_async = {
3aef65ee	50	.device_width = GPMC_DEVWIDTH_16BIT,
c3be5b45 JH	51	.mux_add_data = GPMC_MUX_AD,
	52	};
	53
	54	static struct gpmc_settings onenand_sync = {
	55	.burst_read = true,
3aef65ee JH	56	.burst_wrap = true,
	57	.burst_len = GPMC_BURST_16,
	58	.device_width = GPMC_DEVWIDTH_16BIT,
c3be5b45	59	.mux_add_data = GPMC_MUX_AD,
3aef65ee	60	.wait_pin = 0,
c3be5b45 JH	61	};
c3be5b45 JH	62
be9f10c0	63	static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
aa62e90f	64	{
4f4426f9	65	struct gpmc_device_timings dev_t;
aa62e90f JY	66	const int t_cer = 15;
	67	const int t_avdp = 12;
	68	const int t_aavdh = 7;
	69	const int t_ce = 76;
	70	const int t_aa = 76;
	71	const int t_oe = 20;
	72	const int t_cez = 20; /* max of t_cez, t_oez */
aa62e90f JY	73	const int t_wpl = 40;
	74	const int t_wph = 30;
	75
4f4426f9 AM	76	memset(&dev_t, 0, sizeof(dev_t));
4f4426f9 AM	77
4f4426f9 AM	78	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
	79	dev_t.t_avdp_w = dev_t.t_avdp_r;
	80	dev_t.t_aavdh = t_aavdh * 1000;
	81	dev_t.t_aa = t_aa * 1000;
	82	dev_t.t_ce = t_ce * 1000;
	83	dev_t.t_oe = t_oe * 1000;
	84	dev_t.t_cez_r = t_cez * 1000;
	85	dev_t.t_cez_w = dev_t.t_cez_r;
	86	dev_t.t_wpl = t_wpl * 1000;
	87	dev_t.t_wph = t_wph * 1000;
	88
c3be5b45	89	gpmc_calc_timings(t, &onenand_async, &dev_t);
46376884 AM	90	}
46376884 AM	91
46376884 AM	92	static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
	93	{
	94	u32 reg;
6d453e84 AH	95
	96	/* Ensure sync read and sync write are disabled */
	97	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	98	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
	99	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
aa62e90f JY	100	}
aa62e90f JY	101
46376884	102	static void set_onenand_cfg(void __iomem *onenand_base)
aa62e90f JY	103	{
	104	u32 reg;
	105
	106	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	107	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) \| (0x7 << 9));
	108	reg \|= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) \|
	109	ONENAND_SYS_CFG1_BL_16;
46376884	110	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
aa62e90f JY	111	reg \|= ONENAND_SYS_CFG1_SYNC_READ;
	112	else
	113	reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
46376884	114	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
aa62e90f JY	115	reg \|= ONENAND_SYS_CFG1_SYNC_WRITE;
	116	else
	117	reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
46376884	118	if (onenand_flags & ONENAND_FLAG_HF)
aa62e90f JY	119	reg \|= ONENAND_SYS_CFG1_HF;
	120	else
	121	reg &= ~ONENAND_SYS_CFG1_HF;
46376884	122	if (onenand_flags & ONENAND_FLAG_VHF)
1435ca0f AH	123	reg \|= ONENAND_SYS_CFG1_VHF;
	124	else
	125	reg &= ~ONENAND_SYS_CFG1_VHF;
aa62e90f JY	126	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
	127	}
	128
5714b7ed	129	static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
757ef791	130	void __iomem *onenand_base)
5714b7ed AH	131	{
5714b7ed AH	132	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
757ef791	133	int freq;
5714b7ed AH	134
	135	switch ((ver >> 4) & 0xf) {
	136	case 0:
	137	freq = 40;
	138	break;
	139	case 1:
	140	freq = 54;
	141	break;
	142	case 2:
	143	freq = 66;
	144	break;
	145	case 3:
	146	freq = 83;
	147	break;
	148	case 4:
	149	freq = 104;
	150	break;
	151	default:
	152	freq = 54;
	153	break;
	154	}
	155
	156	return freq;
	157	}
	158
be9f10c0 JH	159	static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
	160	unsigned int flags,
	161	int freq)
aa62e90f	162	{
4f4426f9	163	struct gpmc_device_timings dev_t;
aa62e90f JY	164	const int t_cer = 15;
	165	const int t_avdp = 12;
	166	const int t_cez = 20; /* max of t_cez, t_oez */
aa62e90f JY	167	const int t_wpl = 40;
	168	const int t_wph = 30;
	169	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
4f4426f9	170	int div, gpmc_clk_ns;
aa62e90f	171
be9f10c0	172	if (flags & ONENAND_SYNC_READ)
46376884	173	onenand_flags = ONENAND_FLAG_SYNCREAD;
be9f10c0	174	else if (flags & ONENAND_SYNC_READWRITE)
46376884	175	onenand_flags = ONENAND_FLAG_SYNCREAD \| ONENAND_FLAG_SYNCWRITE;
aa62e90f JY	176
aa62e90f JY	177	switch (freq) {
4931445b AH	178	case 104:
	179	min_gpmc_clk_period = 9600; /* 104 MHz */
	180	t_ces = 3;
	181	t_avds = 4;
	182	t_avdh = 2;
	183	t_ach = 3;
	184	t_aavdh = 6;
1435ca0f	185	t_rdyo = 6;
4931445b	186	break;
aa62e90f	187	case 83:
a3551f5b	188	min_gpmc_clk_period = 12000; /* 83 MHz */
aa62e90f JY	189	t_ces = 5;
	190	t_avds = 4;
	191	t_avdh = 2;
	192	t_ach = 6;
	193	t_aavdh = 6;
	194	t_rdyo = 9;
	195	break;
	196	case 66:
a3551f5b	197	min_gpmc_clk_period = 15000; /* 66 MHz */
aa62e90f JY	198	t_ces = 6;
	199	t_avds = 5;
	200	t_avdh = 2;
	201	t_ach = 6;
	202	t_aavdh = 6;
	203	t_rdyo = 11;
	204	break;
	205	default:
a3551f5b	206	min_gpmc_clk_period = 18500; /* 54 MHz */
aa62e90f JY	207	t_ces = 7;
	208	t_avds = 7;
	209	t_avdh = 7;
	210	t_ach = 9;
	211	t_aavdh = 7;
	212	t_rdyo = 15;
46376884	213	onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
aa62e90f JY	214	break;
	215	}
	216
1b47ca1a	217	div = gpmc_calc_divider(min_gpmc_clk_period);
aa62e90f	218	gpmc_clk_ns = gpmc_ticks_to_ns(div);
6a53bc75	219	if (gpmc_clk_ns < 15) /* >66MHz */
46376884 AM	220	onenand_flags \|= ONENAND_FLAG_HF;
	221	else
	222	onenand_flags &= ~ONENAND_FLAG_HF;
6a53bc75	223	if (gpmc_clk_ns < 12) /* >83MHz */
46376884 AM	224	onenand_flags \|= ONENAND_FLAG_VHF;
	225	else
	226	onenand_flags &= ~ONENAND_FLAG_VHF;
	227	if (onenand_flags & ONENAND_FLAG_VHF)
1435ca0f	228	latency = 8;
46376884	229	else if (onenand_flags & ONENAND_FLAG_HF)
aa62e90f JY	230	latency = 6;
	231	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
	232	latency = 3;
	233	else
	234	latency = 4;
	235
46376884	236	/* Set synchronous read timings */
4f4426f9	237	memset(&dev_t, 0, sizeof(dev_t));
aa62e90f	238
3aef65ee JH	239	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
3aef65ee JH	240	onenand_sync.sync_read = true;
46376884	241	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
c3be5b45	242	onenand_sync.sync_write = true;
3aef65ee	243	onenand_sync.burst_write = true;
aa62e90f	244	} else {
4f4426f9 AM	245	dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
	246	dev_t.t_wpl = t_wpl * 1000;
	247	dev_t.t_wph = t_wph * 1000;
	248	dev_t.t_aavdh = t_aavdh * 1000;
aa62e90f	249	}
4f4426f9 AM	250	dev_t.ce_xdelay = true;
	251	dev_t.avd_xdelay = true;
	252	dev_t.oe_xdelay = true;
	253	dev_t.we_xdelay = true;
	254	dev_t.clk = min_gpmc_clk_period;
	255	dev_t.t_bacc = dev_t.clk;
	256	dev_t.t_ces = t_ces * 1000;
	257	dev_t.t_avds = t_avds * 1000;
	258	dev_t.t_avdh = t_avdh * 1000;
	259	dev_t.t_ach = t_ach * 1000;
	260	dev_t.cyc_iaa = (latency + 1);
	261	dev_t.t_cez_r = t_cez * 1000;
	262	dev_t.t_cez_w = dev_t.t_cez_r;
	263	dev_t.cyc_aavdh_oe = 1;
	264	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
	265
c3be5b45	266	gpmc_calc_timings(t, &onenand_sync, &dev_t);
46376884 AM	267	}
46376884 AM	268
46376884 AM	269	static int omap2_onenand_setup_async(void __iomem *onenand_base)
	270	{
	271	struct gpmc_timings t;
	272	int ret;
	273
1dc1c338	274	if (gpmc_onenand_data->of_node) {
32cde0b5 JH	275	gpmc_read_settings_dt(gpmc_onenand_data->of_node,
32cde0b5 JH	276	&onenand_async);
1dc1c338 AK	277	if (onenand_async.sync_read \|\| onenand_async.sync_write) {
	278	if (onenand_async.sync_write)
	279	gpmc_onenand_data->flags \|=
	280	ONENAND_SYNC_READWRITE;
	281	else
	282	gpmc_onenand_data->flags \|= ONENAND_SYNC_READ;
	283	onenand_async.sync_read = false;
	284	onenand_async.sync_write = false;
	285	}
	286	}
32cde0b5	287
46376884 AM	288	omap2_onenand_set_async_mode(onenand_base);
46376884 AM	289
be9f10c0	290	omap2_onenand_calc_async_timings(&t);
46376884	291
3aef65ee JH	292	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
	293	if (ret < 0)
	294	return ret;
	295
2e676901	296	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
71856843	297	if (ret < 0)
46376884 AM	298	return ret;
	299
	300	omap2_onenand_set_async_mode(onenand_base);
	301
	302	return 0;
	303	}
	304
	305	static int omap2_onenand_setup_sync(void __iomem onenand_base, int freq_ptr)
	306	{
	307	int ret, freq = *freq_ptr;
	308	struct gpmc_timings t;
46376884 AM	309
	310	if (!freq) {
	311	/* Very first call freq is not known */
757ef791	312	freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
46376884 AM	313	set_onenand_cfg(onenand_base);
	314	}
	315
32cde0b5 JH	316	if (gpmc_onenand_data->of_node) {
	317	gpmc_read_settings_dt(gpmc_onenand_data->of_node,
	318	&onenand_sync);
	319	} else {
	320	/*
	321	* FIXME: Appears to be legacy code from initial ONENAND commit.
	322	* Unclear what boards this is for and if this can be removed.
	323	*/
	324	if (!cpu_is_omap34xx())
	325	onenand_sync.wait_on_read = true;
	326	}
3aef65ee	327
be9f10c0	328	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
aa62e90f	329
3aef65ee JH	330	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
	331	if (ret < 0)
	332	return ret;
	333
2e676901	334	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
71856843	335	if (ret < 0)
46376884 AM	336	return ret;
	337
	338	set_onenand_cfg(onenand_base);
aa62e90f	339
3ad2d861 AH	340	*freq_ptr = freq;
3ad2d861 AH	341
aa62e90f JY	342	return 0;
	343	}
	344
3ad2d861	345	static int gpmc_onenand_setup(void __iomem onenand_base, int freq_ptr)
aa62e90f JY	346	{
aa62e90f JY	347	struct device *dev = &gpmc_onenand_device.dev;
46376884 AM	348	unsigned l = ONENAND_SYNC_READ \| ONENAND_SYNC_READWRITE;
46376884 AM	349	int ret;
aa62e90f	350
46376884 AM	351	ret = omap2_onenand_setup_async(onenand_base);
	352	if (ret) {
	353	dev_err(dev, "unable to set to async mode\n");
	354	return ret;
aa62e90f JY	355	}
aa62e90f JY	356
46376884 AM	357	if (!(gpmc_onenand_data->flags & l))
	358	return 0;
	359
	360	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
	361	if (ret)
	362	dev_err(dev, "unable to set to sync mode\n");
	363	return ret;
aa62e90f JY	364	}
aa62e90f JY	365
faf5d2ff	366	void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
aa62e90f	367	{
681988ba	368	int err;
df25cb46	369	struct device *dev = &gpmc_onenand_device.dev;
681988ba	370
aa62e90f JY	371	gpmc_onenand_data = _onenand_data;
	372	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
	373	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
	374
	375	if (cpu_is_omap24xx() &&
	376	(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
7ab91596	377	dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
aa62e90f JY	378	gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
	379	gpmc_onenand_data->flags \|= ONENAND_SYNC_READ;
	380	}
	381
eb77b6a7 AM	382	if (cpu_is_omap34xx())
	383	gpmc_onenand_data->flags \|= ONENAND_IN_OMAP34XX;
	384	else
	385	gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
	386
681988ba AM	387	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
	388	(unsigned long *)&gpmc_onenand_resource.start);
	389	if (err < 0) {
df25cb46 EG	390	dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
df25cb46 EG	391	gpmc_onenand_data->cs, err);
681988ba AM	392	return;
	393	}
	394
	395	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
	396	ONENAND_IO_SIZE - 1;
	397
aa62e90f	398	if (platform_device_register(&gpmc_onenand_device) < 0) {
df25cb46	399	dev_err(dev, "Unable to register OneNAND device\n");
681988ba	400	gpmc_cs_free(gpmc_onenand_data->cs);
aa62e90f JY	401	return;
	402	}
	403	}