projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: OMAP2+: Remove unnecesary include in GPMC driver
[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c
CommitLineData
4bbbc1ad
JY		 1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
44169075
SS		 8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
4bbbc1ad
JY		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
fd1dc87d
PW		 15#undef DEBUG
16
db97eb7d 17#include <linux/irq.h>
4bbbc1ad
JY		 18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/err.h>
21#include <linux/clk.h>
f37e4580
ID		 22#include <linux/ioport.h>
23#include <linux/spinlock.h>
fced80c7 24#include <linux/io.h>
fd1dc87d 25#include <linux/module.h>
db97eb7d 26#include <linux/interrupt.h>
da496873 27#include <linux/platform_device.h>
bc6b1e7b 28#include <linux/of.h>
cdd6928c 29#include <linux/of_address.h>
bc6b1e7b
DM		 30#include <linux/of_mtd.h>
31#include <linux/of_device.h>
32#include <linux/mtd/nand.h>
b3f5525c 33#include <linux/pm_runtime.h>
4bbbc1ad 34
bc3668ea 35#include <linux/platform_data/mtd-nand-omap2.h>
4bbbc1ad 36
7f245162 37#include <asm/mach-types.h>
72d0f1c3 38
dbc04161 39#include "soc.h"
25c7d49e 40#include "omap_device.h"
3ef5d007 41#include "gpmc.h"
bc6b1e7b 42#include "gpmc-nand.h"
75d3625e 43#include "gpmc-onenand.h"
7d7e1eba 44
4be48fd5
AM		 45#define DEVICE_NAME "omap-gpmc"
46
fd1dc87d 47/* GPMC register offsets */
4bbbc1ad
JY		 48#define GPMC_REVISION 0x00
49#define GPMC_SYSCONFIG 0x10
50#define GPMC_SYSSTATUS 0x14
51#define GPMC_IRQSTATUS 0x18
52#define GPMC_IRQENABLE 0x1c
53#define GPMC_TIMEOUT_CONTROL 0x40
54#define GPMC_ERR_ADDRESS 0x44
55#define GPMC_ERR_TYPE 0x48
56#define GPMC_CONFIG 0x50
57#define GPMC_STATUS 0x54
58#define GPMC_PREFETCH_CONFIG1 0x1e0
59#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 60#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 61#define GPMC_PREFETCH_STATUS 0x1f0
62#define GPMC_ECC_CONFIG 0x1f4
63#define GPMC_ECC_CONTROL 0x1f8
64#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 65#define GPMC_ECC1_RESULT 0x200
8d602cf5 66#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 67#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
68#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
69#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
27c9fd60 70#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
71#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
72#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
4bbbc1ad 73
2c65e744
YY		 74/* GPMC ECC control settings */
75#define GPMC_ECC_CTRL_ECCCLEAR 0x100
76#define GPMC_ECC_CTRL_ECCDISABLE 0x000
77#define GPMC_ECC_CTRL_ECCREG1 0x001
78#define GPMC_ECC_CTRL_ECCREG2 0x002
79#define GPMC_ECC_CTRL_ECCREG3 0x003
80#define GPMC_ECC_CTRL_ECCREG4 0x004
81#define GPMC_ECC_CTRL_ECCREG5 0x005
82#define GPMC_ECC_CTRL_ECCREG6 0x006
83#define GPMC_ECC_CTRL_ECCREG7 0x007
84#define GPMC_ECC_CTRL_ECCREG8 0x008
85#define GPMC_ECC_CTRL_ECCREG9 0x009
86
e378d22b
RQ		 87#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
88
559d94b0
AM		 89#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
90#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
91#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
92#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
93#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
94#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
95
948d38e7 96#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 97#define GPMC_CS_SIZE 0x30
2fdf0c98 98#define GPMC_BCH_SIZE 0x10
4bbbc1ad 99
f37e4580 100#define GPMC_MEM_END 0x3FFFFFFF
f37e4580
ID		 101
102#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
103#define GPMC_SECTION_SHIFT 28 /* 128 MB */
104
59e9c5ae 105#define CS_NUM_SHIFT 24
106#define ENABLE_PREFETCH (0x1 << 7)
107#define DMA_MPU_MODE 2
108
da496873
AM		 109#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
110#define GPMC_REVISION_MINOR(l) (l & 0xf)
111
112#define GPMC_HAS_WR_ACCESS 0x1
113#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
aa8d4767 114#define GPMC_HAS_MUX_AAD 0x4
da496873 115
9f833156
JH		 116#define GPMC_NR_WAITPINS 4
117
6b6c32fc
AM		 118/* XXX: Only NAND irq has been considered,currently these are the only ones used
119 */
120#define GPMC_NR_IRQ 2
121
9ed7a776
TL		 122struct gpmc_cs_data {
123 const char *name;
124
125#define GPMC_CS_RESERVED (1 << 0)
126 u32 flags;
127
128 struct resource mem;
129};
130
6b6c32fc
AM		 131struct gpmc_client_irq {
132 unsigned irq;
133 u32 bitmask;
134};
135
a2d3e7ba
RN		 136/* Structure to save gpmc cs context */
137struct gpmc_cs_config {
138 u32 config1;
139 u32 config2;
140 u32 config3;
141 u32 config4;
142 u32 config5;
143 u32 config6;
144 u32 config7;
145 int is_valid;
146};
147
148/*
149 * Structure to save/restore gpmc context
150 * to support core off on OMAP3
151 */
152struct omap3_gpmc_regs {
153 u32 sysconfig;
154 u32 irqenable;
155 u32 timeout_ctrl;
156 u32 config;
157 u32 prefetch_config1;
158 u32 prefetch_config2;
159 u32 prefetch_control;
160 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
161};
162
6b6c32fc
AM		 163static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
164static struct irq_chip gpmc_irq_chip;
af072196 165static int gpmc_irq_start;
6b6c32fc 166
f37e4580 167static struct resource gpmc_mem_root;
9ed7a776 168static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
87b247c4 169static DEFINE_SPINLOCK(gpmc_mem_lock);
6797b4fe 170/* Define chip-selects as reserved by default until probe completes */
f34f3716 171static unsigned int gpmc_cs_num = GPMC_CS_NUM;
9f833156 172static unsigned int gpmc_nr_waitpins;
da496873
AM		 173static struct device *gpmc_dev;
174static int gpmc_irq;
175static resource_size_t phys_base, mem_size;
176static unsigned gpmc_capability;
fd1dc87d 177static void __iomem *gpmc_base;
4bbbc1ad 178
fd1dc87d 179static struct clk *gpmc_l3_clk;
4bbbc1ad 180
db97eb7d
SG		 181static irqreturn_t gpmc_handle_irq(int irq, void *dev);
182
4bbbc1ad
JY		 183static void gpmc_write_reg(int idx, u32 val)
184{
edfaf05c 185 writel_relaxed(val, gpmc_base + idx);
4bbbc1ad
JY		 186}
187
188static u32 gpmc_read_reg(int idx)
189{
edfaf05c 190 return readl_relaxed(gpmc_base + idx);
4bbbc1ad
JY		 191}
192
193void gpmc_cs_write_reg(int cs, int idx, u32 val)
194{
195 void __iomem *reg_addr;
196
948d38e7 197 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 198 writel_relaxed(val, reg_addr);
4bbbc1ad
JY		 199}
200
3fc089e7 201static u32 gpmc_cs_read_reg(int cs, int idx)
4bbbc1ad 202{
fd1dc87d
PW		 203 void __iomem *reg_addr;
204
948d38e7 205 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 206 return readl_relaxed(reg_addr);
4bbbc1ad
JY		 207}
208
fd1dc87d 209/* TODO: Add support for gpmc_fck to clock framework and use it */
3fc089e7 210static unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 211{
fd1dc87d
PW		 212 unsigned long rate = clk_get_rate(gpmc_l3_clk);
213
fd1dc87d
PW		 214 rate /= 1000;
215 rate = 1000000000 / rate; /* In picoseconds */
216
217 return rate;
4bbbc1ad
JY		 218}
219
3fc089e7 220static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
4bbbc1ad
JY		 221{
222 unsigned long tick_ps;
223
224 /* Calculate in picosecs to yield more exact results */
225 tick_ps = gpmc_get_fclk_period();
226
227 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
228}
229
3fc089e7 230static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
a3551f5b
AH		 231{
232 unsigned long tick_ps;
233
234 /* Calculate in picosecs to yield more exact results */
235 tick_ps = gpmc_get_fclk_period();
236
237 return (time_ps + tick_ps - 1) / tick_ps;
238}
239
fd1dc87d
PW		 240unsigned int gpmc_ticks_to_ns(unsigned int ticks)
241{
242 return ticks * gpmc_get_fclk_period() / 1000;
243}
244
246da26d
AM		 245static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
246{
247 return ticks * gpmc_get_fclk_period();
248}
249
250static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
251{
252 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
253
254 return ticks * gpmc_get_fclk_period();
255}
256
559d94b0
AM		 257static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
258{
259 u32 l;
260
261 l = gpmc_cs_read_reg(cs, reg);
262 if (value)
263 l |= mask;
264 else
265 l &= ~mask;
266 gpmc_cs_write_reg(cs, reg, l);
267}
268
269static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
270{
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
272 GPMC_CONFIG1_TIME_PARA_GRAN,
273 p->time_para_granularity);
274 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
275 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
276 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
277 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
278 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
279 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
280 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
281 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
282 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
283 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
284 p->cycle2cyclesamecsen);
285 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
286 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
287 p->cycle2cyclediffcsen);
288}
289
35ac051e
TL		 290#ifdef DEBUG
291static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
292 bool raw, bool noval, int shift,
293 const char *name)
294{
295 u32 l;
296 int nr_bits, max_value, mask;
297
298 l = gpmc_cs_read_reg(cs, reg);
299 nr_bits = end_bit - st_bit + 1;
300 max_value = (1 << nr_bits) - 1;
301 mask = max_value << st_bit;
302 l = (l & mask) >> st_bit;
303 if (shift)
304 l = (shift << l);
305 if (noval && (l == 0))
306 return 0;
307 if (!raw) {
308 unsigned int time_ns_min, time_ns, time_ns_max;
309
310 time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
311 time_ns = gpmc_ticks_to_ns(l);
312 time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
313 max_value : l + 1);
314 pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
315 name, time_ns, time_ns_min, time_ns_max, l);
316 } else {
317 pr_info("gpmc,%s = <%u>\n", name, l);
318 }
319
320 return l;
321}
322
323#define GPMC_PRINT_CONFIG(cs, config) \
324 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
325 gpmc_cs_read_reg(cs, config))
326#define GPMC_GET_RAW(reg, st, end, field) \
327 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
328#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
329 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
330#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
331 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
332#define GPMC_GET_TICKS(reg, st, end, field) \
333 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
334
335static void gpmc_show_regs(int cs, const char *desc)
336{
337 pr_info("gpmc cs%i %s:\n", cs, desc);
338 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
339 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
340 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
341 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
342 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
343 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
344}
345
346/*
347 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
348 * see commit c9fb809.
349 */
350static void gpmc_cs_show_timings(int cs, const char *desc)
351{
352 gpmc_show_regs(cs, desc);
353
354 pr_info("gpmc cs%i access configuration:\n", cs);
355 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
356 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
357 GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
358 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
359 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
360 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
361 GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
362 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
363 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
364 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
365 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
366 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
367
368 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
369
370 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
371
372 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
373 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
374
375 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
376 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
377
378 pr_info("gpmc cs%i timings configuration:\n", cs);
379 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
380 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
381 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
382
383 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
384 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
385 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
386
387 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
388 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
389 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
390 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
391
392 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
393 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
394 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
395
396 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
397
398 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
399 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
400
401 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
402 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
403
404 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
405 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
406}
407#else
408static inline void gpmc_cs_show_timings(int cs, const char *desc)
409{
410}
411#endif
412
4bbbc1ad 413static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468 414 int time, const char *name)
4bbbc1ad
JY		 415{
416 u32 l;
417 int ticks, mask, nr_bits;
418
419 if (time == 0)
420 ticks = 0;
421 else
422 ticks = gpmc_ns_to_ticks(time);
423 nr_bits = end_bit - st_bit + 1;
80323742
RQ		 424 mask = (1 << nr_bits) - 1;
425
426 if (ticks > mask) {
427 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
428 __func__, cs, name, time, ticks, mask);
429
4bbbc1ad 430 return -1;
1c22cc13 431 }
4bbbc1ad 432
4bbbc1ad
JY		 433 l = gpmc_cs_read_reg(cs, reg);
434#ifdef DEBUG
1c22cc13
DB		 435 printk(KERN_INFO
436 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468 437 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13 438 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 439#endif
440 l &= ~(mask << st_bit);
441 l |= ticks << st_bit;
442 gpmc_cs_write_reg(cs, reg, l);
443
444 return 0;
445}
446
4bbbc1ad
JY		 447#define GPMC_SET_ONE(reg, st, end, field) \
448 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
449 t->field, #field) < 0) \
450 return -1
4bbbc1ad 451
1b47ca1a 452int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad
JY		 453{
454 int div;
455 u32 l;
456
a3551f5b 457 l = sync_clk + (gpmc_get_fclk_period() - 1);
4bbbc1ad
JY		 458 div = l / gpmc_get_fclk_period();
459 if (div > 4)
460 return -1;
1c22cc13 461 if (div <= 0)
4bbbc1ad
JY		 462 div = 1;
463
464 return div;
465}
466
467int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
468{
469 int div;
470 u32 l;
471
35ac051e 472 gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
1b47ca1a 473 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 474 if (div < 0)
a032d33b 475 return div;
4bbbc1ad
JY		 476
477 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
478 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
479 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
480
481 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
482 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
483 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
484
485 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
486 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
487 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
488 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
489
490 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
491 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
492 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
493
494 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
495
559d94b0
AM		 496 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
497 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
498
499 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
500 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
501
da496873 502 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
cc26b3b0 503 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
da496873 504 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
cc26b3b0 505 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
cc26b3b0 506
1c22cc13
DB		 507 /* caller is expected to have initialized CONFIG1 to cover
508 * at least sync vs async
509 */
510 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
511 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad 512#ifdef DEBUG
1c22cc13
DB		 513 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
514 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 515#endif
1c22cc13
DB		 516 l &= ~0x03;
517 l |= (div - 1);
518 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
519 }
4bbbc1ad 520
559d94b0 521 gpmc_cs_bool_timings(cs, &t->bool_timings);
35ac051e 522 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
559d94b0 523
4bbbc1ad
JY		 524 return 0;
525}
526
4cf27d2e 527static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
f37e4580
ID		 528{
529 u32 l;
530 u32 mask;
531
c71f8e9b
JH		 532 /*
533 * Ensure that base address is aligned on a
534 * boundary equal to or greater than size.
535 */
536 if (base & (size - 1))
537 return -EINVAL;
538
f37e4580
ID		 539 mask = (1 << GPMC_SECTION_SHIFT) - size;
540 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
541 l &= ~0x3f;
542 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
543 l &= ~(0x0f << 8);
544 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
a2d3e7ba 545 l |= GPMC_CONFIG7_CSVALID;
f37e4580 546 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
c71f8e9b
JH		 547
548 return 0;
f37e4580
ID		 549}
550
4cf27d2e
RQ		 551static void gpmc_cs_enable_mem(int cs)
552{
553 u32 l;
554
555 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
556 l |= GPMC_CONFIG7_CSVALID;
557 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
558}
559
f37e4580
ID		 560static void gpmc_cs_disable_mem(int cs)
561{
562 u32 l;
563
564 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 565 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 566 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
567}
568
569static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
570{
571 u32 l;
572 u32 mask;
573
574 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
575 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
576 mask = (l >> 8) & 0x0f;
577 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
578}
579
580static int gpmc_cs_mem_enabled(int cs)
581{
582 u32 l;
583
584 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 585 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 586}
587
f5d8edaf 588static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 589{
9ed7a776
TL		 590 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
591
592 gpmc->flags |= GPMC_CS_RESERVED;
f37e4580
ID		 593}
594
ae9d908a 595static bool gpmc_cs_reserved(int cs)
f37e4580 596{
9ed7a776
TL		 597 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
598
599 return gpmc->flags & GPMC_CS_RESERVED;
600}
601
602static void gpmc_cs_set_name(int cs, const char *name)
603{
604 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
605
606 gpmc->name = name;
607}
608
609const char *gpmc_cs_get_name(int cs)
610{
611 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
612
613 return gpmc->name;
f37e4580
ID		 614}
615
616static unsigned long gpmc_mem_align(unsigned long size)
617{
618 int order;
619
620 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
621 order = GPMC_CHUNK_SHIFT - 1;
622 do {
623 size >>= 1;
624 order++;
625 } while (size);
626 size = 1 << order;
627 return size;
628}
629
630static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
631{
9ed7a776
TL		 632 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
633 struct resource *res = &gpmc->mem;
f37e4580
ID		 634 int r;
635
636 size = gpmc_mem_align(size);
637 spin_lock(&gpmc_mem_lock);
638 res->start = base;
639 res->end = base + size - 1;
640 r = request_resource(&gpmc_mem_root, res);
641 spin_unlock(&gpmc_mem_lock);
642
643 return r;
644}
645
da496873
AM		 646static int gpmc_cs_delete_mem(int cs)
647{
9ed7a776
TL		 648 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
649 struct resource *res = &gpmc->mem;
da496873
AM		 650 int r;
651
652 spin_lock(&gpmc_mem_lock);
efe80723 653 r = release_resource(res);
da496873
AM		 654 res->start = 0;
655 res->end = 0;
656 spin_unlock(&gpmc_mem_lock);
657
658 return r;
659}
660
cdd6928c
JH		 661/**
662 * gpmc_cs_remap - remaps a chip-select physical base address
663 * @cs: chip-select to remap
664 * @base: physical base address to re-map chip-select to
665 *
666 * Re-maps a chip-select to a new physical base address specified by
667 * "base". Returns 0 on success and appropriate negative error code
668 * on failure.
669 */
670static int gpmc_cs_remap(int cs, u32 base)
671{
672 int ret;
673 u32 old_base, size;
674
f34f3716
GP		 675 if (cs > gpmc_cs_num) {
676 pr_err("%s: requested chip-select is disabled\n", __func__);
cdd6928c 677 return -ENODEV;
f34f3716 678 }
fb677ef7
TL		 679
680 /*
681 * Make sure we ignore any device offsets from the GPMC partition
682 * allocated for the chip select and that the new base confirms
683 * to the GPMC 16MB minimum granularity.
684 */
685 base &= ~(SZ_16M - 1);
686
cdd6928c
JH		 687 gpmc_cs_get_memconf(cs, &old_base, &size);
688 if (base == old_base)
689 return 0;
4cf27d2e 690
cdd6928c
JH		 691 ret = gpmc_cs_delete_mem(cs);
692 if (ret < 0)
693 return ret;
4cf27d2e 694
cdd6928c 695 ret = gpmc_cs_insert_mem(cs, base, size);
c71f8e9b
JH		 696 if (ret < 0)
697 return ret;
cdd6928c 698
4cf27d2e
RQ		 699 ret = gpmc_cs_set_memconf(cs, base, size);
700
701 return ret;
cdd6928c
JH		 702}
703
f37e4580
ID		 704int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
705{
9ed7a776
TL		 706 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
707 struct resource *res = &gpmc->mem;
f37e4580
ID		 708 int r = -1;
709
f34f3716
GP		 710 if (cs > gpmc_cs_num) {
711 pr_err("%s: requested chip-select is disabled\n", __func__);
f37e4580 712 return -ENODEV;
f34f3716 713 }
f37e4580
ID		 714 size = gpmc_mem_align(size);
715 if (size > (1 << GPMC_SECTION_SHIFT))
716 return -ENOMEM;
717
718 spin_lock(&gpmc_mem_lock);
719 if (gpmc_cs_reserved(cs)) {
720 r = -EBUSY;
721 goto out;
722 }
723 if (gpmc_cs_mem_enabled(cs))
724 r = adjust_resource(res, res->start & ~(size - 1), size);
725 if (r < 0)
726 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
727 size, NULL, NULL);
728 if (r < 0)
729 goto out;
730
4cf27d2e
RQ		 731 /* Disable CS while changing base address and size mask */
732 gpmc_cs_disable_mem(cs);
733
734 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
c71f8e9b
JH		 735 if (r < 0) {
736 release_resource(res);
737 goto out;
738 }
739
4cf27d2e
RQ		 740 /* Enable CS */
741 gpmc_cs_enable_mem(cs);
f37e4580
ID		 742 *base = res->start;
743 gpmc_cs_set_reserved(cs, 1);
744out:
745 spin_unlock(&gpmc_mem_lock);
746 return r;
747}
fd1dc87d 748EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 749
750void gpmc_cs_free(int cs)
751{
9ed7a776
TL		 752 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
753 struct resource *res = &gpmc->mem;
efe80723 754
f37e4580 755 spin_lock(&gpmc_mem_lock);
f34f3716 756 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
f37e4580
ID		 757 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
758 BUG();
759 spin_unlock(&gpmc_mem_lock);
760 return;
761 }
762 gpmc_cs_disable_mem(cs);
efe80723
TL		 763 if (res->flags)
764 release_resource(res);
f37e4580
ID		 765 gpmc_cs_set_reserved(cs, 0);
766 spin_unlock(&gpmc_mem_lock);
767}
fd1dc87d 768EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 769
948d38e7 770/**
3a544354 771 * gpmc_configure - write request to configure gpmc
948d38e7
SG		 772 * @cmd: command type
773 * @wval: value to write
774 * @return status of the operation
775 */
3a544354 776int gpmc_configure(int cmd, int wval)
948d38e7 777{
3a544354 778 u32 regval;
948d38e7
SG		 779
780 switch (cmd) {
db97eb7d
SG		 781 case GPMC_ENABLE_IRQ:
782 gpmc_write_reg(GPMC_IRQENABLE, wval);
783 break;
784
948d38e7
SG		 785 case GPMC_SET_IRQ_STATUS:
786 gpmc_write_reg(GPMC_IRQSTATUS, wval);
787 break;
788
789 case GPMC_CONFIG_WP:
790 regval = gpmc_read_reg(GPMC_CONFIG);
791 if (wval)
792 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
793 else
794 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
795 gpmc_write_reg(GPMC_CONFIG, regval);
796 break;
797
948d38e7 798 default:
3a544354
JH		 799 pr_err("%s: command not supported\n", __func__);
800 return -EINVAL;
948d38e7
SG		 801 }
802
3a544354 803 return 0;
948d38e7 804}
3a544354 805EXPORT_SYMBOL(gpmc_configure);
948d38e7 806
52bd138d
AM		 807void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
808{
2fdf0c98
AM		 809 int i;
810
52bd138d
AM		 811 reg->gpmc_status = gpmc_base + GPMC_STATUS;
812 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
813 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
814 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
815 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
816 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
817 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
818 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
819 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
820 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
821 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
822 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
823 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
824 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
825 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 826
827 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
828 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
829 GPMC_BCH_SIZE * i;
830 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
831 GPMC_BCH_SIZE * i;
832 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
833 GPMC_BCH_SIZE * i;
834 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
835 GPMC_BCH_SIZE * i;
27c9fd60 836 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
837 i * GPMC_BCH_SIZE;
838 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
839 i * GPMC_BCH_SIZE;
840 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
841 i * GPMC_BCH_SIZE;
2fdf0c98 842 }
52bd138d
AM		 843}
844
6b6c32fc
AM		 845int gpmc_get_client_irq(unsigned irq_config)
846{
847 int i;
848
849 if (hweight32(irq_config) > 1)
850 return 0;
851
852 for (i = 0; i < GPMC_NR_IRQ; i++)
853 if (gpmc_client_irq[i].bitmask & irq_config)
854 return gpmc_client_irq[i].irq;
855
856 return 0;
857}
858
859static int gpmc_irq_endis(unsigned irq, bool endis)
860{
861 int i;
862 u32 regval;
863
864 for (i = 0; i < GPMC_NR_IRQ; i++)
865 if (irq == gpmc_client_irq[i].irq) {
866 regval = gpmc_read_reg(GPMC_IRQENABLE);
867 if (endis)
868 regval |= gpmc_client_irq[i].bitmask;
869 else
870 regval &= ~gpmc_client_irq[i].bitmask;
871 gpmc_write_reg(GPMC_IRQENABLE, regval);
872 break;
873 }
874
875 return 0;
876}
877
878static void gpmc_irq_disable(struct irq_data *p)
879{
880 gpmc_irq_endis(p->irq, false);
881}
882
883static void gpmc_irq_enable(struct irq_data *p)
884{
885 gpmc_irq_endis(p->irq, true);
886}
887
888static void gpmc_irq_noop(struct irq_data *data) { }
889
890static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
891
da496873 892static int gpmc_setup_irq(void)
6b6c32fc
AM		 893{
894 int i;
895 u32 regval;
896
897 if (!gpmc_irq)
898 return -EINVAL;
899
900 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
71856843 901 if (gpmc_irq_start < 0) {
6b6c32fc
AM		 902 pr_err("irq_alloc_descs failed\n");
903 return gpmc_irq_start;
904 }
905
906 gpmc_irq_chip.name = "gpmc";
907 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
908 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
909 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
910 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
911 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
912 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
913 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
914
915 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
916 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
917
918 for (i = 0; i < GPMC_NR_IRQ; i++) {
919 gpmc_client_irq[i].irq = gpmc_irq_start + i;
920 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
921 &gpmc_irq_chip, handle_simple_irq);
922 set_irq_flags(gpmc_client_irq[i].irq,
923 IRQF_VALID | IRQF_NOAUTOEN);
924 }
925
926 /* Disable interrupts */
927 gpmc_write_reg(GPMC_IRQENABLE, 0);
928
929 /* clear interrupts */
930 regval = gpmc_read_reg(GPMC_IRQSTATUS);
931 gpmc_write_reg(GPMC_IRQSTATUS, regval);
932
933 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
934}
935
351a102d 936static int gpmc_free_irq(void)
da496873
AM		 937{
938 int i;
939
940 if (gpmc_irq)
941 free_irq(gpmc_irq, NULL);
942
943 for (i = 0; i < GPMC_NR_IRQ; i++) {
944 irq_set_handler(gpmc_client_irq[i].irq, NULL);
945 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
946 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
947 }
948
949 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
950
951 return 0;
952}
953
351a102d 954static void gpmc_mem_exit(void)
da496873
AM		 955{
956 int cs;
957
f34f3716 958 for (cs = 0; cs < gpmc_cs_num; cs++) {
da496873
AM		 959 if (!gpmc_cs_mem_enabled(cs))
960 continue;
961 gpmc_cs_delete_mem(cs);
962 }
963
964}
965
84b00f0e 966static void gpmc_mem_init(void)
f37e4580 967{
84b00f0e 968 int cs;
f37e4580 969
bf234397
JH		 970 /*
971 * The first 1MB of GPMC address space is typically mapped to
972 * the internal ROM. Never allocate the first page, to
973 * facilitate bug detection; even if we didn't boot from ROM.
7f245162 974 */
bf234397 975 gpmc_mem_root.start = SZ_1M;
f37e4580
ID		 976 gpmc_mem_root.end = GPMC_MEM_END;
977
978 /* Reserve all regions that has been set up by bootloader */
f34f3716 979 for (cs = 0; cs < gpmc_cs_num; cs++) {
f37e4580
ID		 980 u32 base, size;
981
982 if (!gpmc_cs_mem_enabled(cs))
983 continue;
984 gpmc_cs_get_memconf(cs, &base, &size);
84b00f0e
JH		 985 if (gpmc_cs_insert_mem(cs, base, size)) {
986 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
987 __func__, cs, base, base + size);
988 gpmc_cs_disable_mem(cs);
8119024e 989 }
f37e4580 990 }
4bbbc1ad
JY		 991}
992
246da26d
AM		 993static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
994{
995 u32 temp;
996 int div;
997
998 div = gpmc_calc_divider(sync_clk);
999 temp = gpmc_ps_to_ticks(time_ps);
1000 temp = (temp + div - 1) / div;
1001 return gpmc_ticks_to_ps(temp * div);
1002}
1003
1004/* XXX: can the cycles be avoided ? */
1005static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1006 struct gpmc_device_timings *dev_t,
1007 bool mux)
246da26d 1008{
246da26d
AM		 1009 u32 temp;
1010
1011 /* adv_rd_off */
1012 temp = dev_t->t_avdp_r;
1013 /* XXX: mux check required ? */
1014 if (mux) {
1015 /* XXX: t_avdp not to be required for sync, only added for tusb
1016 * this indirectly necessitates requirement of t_avdp_r and
1017 * t_avdp_w instead of having a single t_avdp
1018 */
1019 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1020 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1021 }
1022 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1023
1024 /* oe_on */
1025 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1026 if (mux) {
1027 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1028 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1029 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1030 }
1031 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1032
1033 /* access */
1034 /* XXX: any scope for improvement ?, by combining oe_on
1035 * and clk_activation, need to check whether
1036 * access = clk_activation + round to sync clk ?
1037 */
1038 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1039 temp += gpmc_t->clk_activation;
1040 if (dev_t->cyc_oe)
1041 temp = max_t(u32, temp, gpmc_t->oe_on +
1042 gpmc_ticks_to_ps(dev_t->cyc_oe));
1043 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1044
1045 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1046 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1047
1048 /* rd_cycle */
1049 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1050 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1051 gpmc_t->access;
1052 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1053 if (dev_t->t_ce_rdyz)
1054 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1055 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1056
1057 return 0;
1058}
1059
1060static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1061 struct gpmc_device_timings *dev_t,
1062 bool mux)
246da26d 1063{
246da26d
AM		 1064 u32 temp;
1065
1066 /* adv_wr_off */
1067 temp = dev_t->t_avdp_w;
1068 if (mux) {
1069 temp = max_t(u32, temp,
1070 gpmc_t->clk_activation + dev_t->t_avdh);
1071 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1072 }
1073 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1074
1075 /* wr_data_mux_bus */
1076 temp = max_t(u32, dev_t->t_weasu,
1077 gpmc_t->clk_activation + dev_t->t_rdyo);
1078 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1079 * and in that case remember to handle we_on properly
1080 */
1081 if (mux) {
1082 temp = max_t(u32, temp,
1083 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1084 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1085 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1086 }
1087 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1088
1089 /* we_on */
1090 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1091 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1092 else
1093 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1094
1095 /* wr_access */
1096 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1097 gpmc_t->wr_access = gpmc_t->access;
1098
1099 /* we_off */
1100 temp = gpmc_t->we_on + dev_t->t_wpl;
1101 temp = max_t(u32, temp,
1102 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1103 temp = max_t(u32, temp,
1104 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1105 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1106
1107 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1108 dev_t->t_wph);
1109
1110 /* wr_cycle */
1111 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1112 temp += gpmc_t->wr_access;
1113 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1114 if (dev_t->t_ce_rdyz)
1115 temp = max_t(u32, temp,
1116 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1117 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1118
1119 return 0;
1120}
1121
1122static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1123 struct gpmc_device_timings *dev_t,
1124 bool mux)
246da26d 1125{
246da26d
AM		 1126 u32 temp;
1127
1128 /* adv_rd_off */
1129 temp = dev_t->t_avdp_r;
1130 if (mux)
1131 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1132 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1133
1134 /* oe_on */
1135 temp = dev_t->t_oeasu;
1136 if (mux)
1137 temp = max_t(u32, temp,
1138 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1139 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1140
1141 /* access */
1142 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1143 gpmc_t->oe_on + dev_t->t_oe);
1144 temp = max_t(u32, temp,
1145 gpmc_t->cs_on + dev_t->t_ce);
1146 temp = max_t(u32, temp,
1147 gpmc_t->adv_on + dev_t->t_aa);
1148 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1149
1150 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1151 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1152
1153 /* rd_cycle */
1154 temp = max_t(u32, dev_t->t_rd_cycle,
1155 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1156 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1157 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1158
1159 return 0;
1160}
1161
1162static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1163 struct gpmc_device_timings *dev_t,
1164 bool mux)
246da26d 1165{
246da26d
AM		 1166 u32 temp;
1167
1168 /* adv_wr_off */
1169 temp = dev_t->t_avdp_w;
1170 if (mux)
1171 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1172 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1173
1174 /* wr_data_mux_bus */
1175 temp = dev_t->t_weasu;
1176 if (mux) {
1177 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1178 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1179 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1180 }
1181 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1182
1183 /* we_on */
1184 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1185 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1186 else
1187 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1188
1189 /* we_off */
1190 temp = gpmc_t->we_on + dev_t->t_wpl;
1191 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1192
1193 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1194 dev_t->t_wph);
1195
1196 /* wr_cycle */
1197 temp = max_t(u32, dev_t->t_wr_cycle,
1198 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1199 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1200
1201 return 0;
1202}
1203
1204static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1205 struct gpmc_device_timings *dev_t)
1206{
1207 u32 temp;
1208
1209 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1210 gpmc_get_fclk_period();
1211
1212 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1213 dev_t->t_bacc,
1214 gpmc_t->sync_clk);
1215
1216 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1217 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1218
1219 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1220 return 0;
1221
1222 if (dev_t->ce_xdelay)
1223 gpmc_t->bool_timings.cs_extra_delay = true;
1224 if (dev_t->avd_xdelay)
1225 gpmc_t->bool_timings.adv_extra_delay = true;
1226 if (dev_t->oe_xdelay)
1227 gpmc_t->bool_timings.oe_extra_delay = true;
1228 if (dev_t->we_xdelay)
1229 gpmc_t->bool_timings.we_extra_delay = true;
1230
1231 return 0;
1232}
1233
1234static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1235 struct gpmc_device_timings *dev_t,
1236 bool sync)
246da26d
AM		 1237{
1238 u32 temp;
1239
1240 /* cs_on */
1241 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1242
1243 /* adv_on */
1244 temp = dev_t->t_avdasu;
1245 if (dev_t->t_ce_avd)
1246 temp = max_t(u32, temp,
1247 gpmc_t->cs_on + dev_t->t_ce_avd);
1248 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1249
c3be5b45 1250 if (sync)
246da26d
AM		 1251 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1252
1253 return 0;
1254}
1255
1256/* TODO: remove this function once all peripherals are confirmed to
1257 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1258 * has to be modified to handle timings in ps instead of ns
1259*/
1260static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1261{
1262 t->cs_on /= 1000;
1263 t->cs_rd_off /= 1000;
1264 t->cs_wr_off /= 1000;
1265 t->adv_on /= 1000;
1266 t->adv_rd_off /= 1000;
1267 t->adv_wr_off /= 1000;
1268 t->we_on /= 1000;
1269 t->we_off /= 1000;
1270 t->oe_on /= 1000;
1271 t->oe_off /= 1000;
1272 t->page_burst_access /= 1000;
1273 t->access /= 1000;
1274 t->rd_cycle /= 1000;
1275 t->wr_cycle /= 1000;
1276 t->bus_turnaround /= 1000;
1277 t->cycle2cycle_delay /= 1000;
1278 t->wait_monitoring /= 1000;
1279 t->clk_activation /= 1000;
1280 t->wr_access /= 1000;
1281 t->wr_data_mux_bus /= 1000;
1282}
1283
1284int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1285 struct gpmc_settings *gpmc_s,
1286 struct gpmc_device_timings *dev_t)
246da26d 1287{
c3be5b45
JH		 1288 bool mux = false, sync = false;
1289
1290 if (gpmc_s) {
1291 mux = gpmc_s->mux_add_data ? true : false;
1292 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1293 }
1294
246da26d
AM		 1295 memset(gpmc_t, 0, sizeof(*gpmc_t));
1296
c3be5b45 1297 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
246da26d 1298
c3be5b45
JH		 1299 if (gpmc_s && gpmc_s->sync_read)
1300 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
246da26d 1301 else
c3be5b45 1302 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
246da26d 1303
c3be5b45
JH		 1304 if (gpmc_s && gpmc_s->sync_write)
1305 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
246da26d 1306 else
c3be5b45 1307 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
246da26d
AM		 1308
1309 /* TODO: remove, see function definition */
1310 gpmc_convert_ps_to_ns(gpmc_t);
1311
1312 return 0;
1313}
1314
aa8d4767
JH		 1315/**
1316 * gpmc_cs_program_settings - programs non-timing related settings
1317 * @cs: GPMC chip-select to program
1318 * @p: pointer to GPMC settings structure
1319 *
1320 * Programs non-timing related settings for a GPMC chip-select, such as
1321 * bus-width, burst configuration, etc. Function should be called once
1322 * for each chip-select that is being used and must be called before
1323 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1324 * register will be initialised to zero by this function. Returns 0 on
1325 * success and appropriate negative error code on failure.
1326 */
1327int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1328{
1329 u32 config1;
1330
1331 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1332 pr_err("%s: invalid width %d!", __func__, p->device_width);
1333 return -EINVAL;
1334 }
1335
1336 /* Address-data multiplexing not supported for NAND devices */
1337 if (p->device_nand && p->mux_add_data) {
1338 pr_err("%s: invalid configuration!\n", __func__);
1339 return -EINVAL;
1340 }
1341
1342 if ((p->mux_add_data > GPMC_MUX_AD) ||
1343 ((p->mux_add_data == GPMC_MUX_AAD) &&
1344 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1345 pr_err("%s: invalid multiplex configuration!\n", __func__);
1346 return -EINVAL;
1347 }
1348
1349 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1350 if (p->burst_read || p->burst_write) {
1351 switch (p->burst_len) {
1352 case GPMC_BURST_4:
1353 case GPMC_BURST_8:
1354 case GPMC_BURST_16:
1355 break;
1356 default:
1357 pr_err("%s: invalid page/burst-length (%d)\n",
1358 __func__, p->burst_len);
1359 return -EINVAL;
1360 }
1361 }
1362
2b54057c 1363 if (p->wait_pin > gpmc_nr_waitpins) {
aa8d4767
JH		 1364 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1365 return -EINVAL;
1366 }
1367
1368 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1369
1370 if (p->sync_read)
1371 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1372 if (p->sync_write)
1373 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1374 if (p->wait_on_read)
1375 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1376 if (p->wait_on_write)
1377 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1378 if (p->wait_on_read || p->wait_on_write)
1379 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1380 if (p->device_nand)
1381 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1382 if (p->mux_add_data)
1383 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1384 if (p->burst_read)
1385 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1386 if (p->burst_write)
1387 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1388 if (p->burst_read || p->burst_write) {
1389 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1390 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1391 }
1392
1393 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1394
1395 return 0;
1396}
1397
bc6b1e7b 1398#ifdef CONFIG_OF
31957609 1399static const struct of_device_id gpmc_dt_ids[] = {
bc6b1e7b
DM		 1400 { .compatible = "ti,omap2420-gpmc" },
1401 { .compatible = "ti,omap2430-gpmc" },
1402 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1403 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1404 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1405 { }
1406};
1407MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1408
8c8a7771
JH		 1409/**
1410 * gpmc_read_settings_dt - read gpmc settings from device-tree
1411 * @np: pointer to device-tree node for a gpmc child device
1412 * @p: pointer to gpmc settings structure
1413 *
1414 * Reads the GPMC settings for a GPMC child device from device-tree and
1415 * stores them in the GPMC settings structure passed. The GPMC settings
1416 * structure is initialised to zero by this function and so any
1417 * previously stored settings will be cleared.
1418 */
1419void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1420{
1421 memset(p, 0, sizeof(struct gpmc_settings));
1422
1423 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1424 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
8c8a7771
JH		 1425 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1426 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1427
1428 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1429 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1430 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1431 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1432 if (!p->burst_read && !p->burst_write)
1433 pr_warn("%s: page/burst-length set but not used!\n",
1434 __func__);
1435 }
1436
1437 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1438 p->wait_on_read = of_property_read_bool(np,
1439 "gpmc,wait-on-read");
1440 p->wait_on_write = of_property_read_bool(np,
1441 "gpmc,wait-on-write");
1442 if (!p->wait_on_read && !p->wait_on_write)
2b54057c
RQ		 1443 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1444 __func__);
8c8a7771
JH		 1445 }
1446}
1447
bc6b1e7b
DM		 1448static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1449 struct gpmc_timings *gpmc_t)
1450{
d36b4cd4
JH		 1451 struct gpmc_bool_timings *p;
1452
1453 if (!np || !gpmc_t)
1454 return;
bc6b1e7b
DM		 1455
1456 memset(gpmc_t, 0, sizeof(*gpmc_t));
1457
1458 /* minimum clock period for syncronous mode */
d36b4cd4 1459 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
bc6b1e7b
DM		 1460
1461 /* chip select timtings */
d36b4cd4
JH		 1462 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1463 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1464 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
bc6b1e7b
DM		 1465
1466 /* ADV signal timings */
d36b4cd4
JH		 1467 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1468 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1469 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
bc6b1e7b
DM		 1470
1471 /* WE signal timings */
d36b4cd4
JH		 1472 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1473 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
bc6b1e7b
DM		 1474
1475 /* OE signal timings */
d36b4cd4
JH		 1476 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1477 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
bc6b1e7b
DM		 1478
1479 /* access and cycle timings */
d36b4cd4
JH		 1480 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1481 &gpmc_t->page_burst_access);
1482 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1483 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1484 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1485 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1486 &gpmc_t->bus_turnaround);
1487 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1488 &gpmc_t->cycle2cycle_delay);
1489 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1490 &gpmc_t->wait_monitoring);
1491 of_property_read_u32(np, "gpmc,clk-activation-ns",
1492 &gpmc_t->clk_activation);
1493
1494 /* only applicable to OMAP3+ */
1495 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1496 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1497 &gpmc_t->wr_data_mux_bus);
1498
1499 /* bool timing parameters */
1500 p = &gpmc_t->bool_timings;
1501
1502 p->cycle2cyclediffcsen =
1503 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1504 p->cycle2cyclesamecsen =
1505 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1506 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1507 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1508 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1509 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1510 p->time_para_granularity =
1511 of_property_read_bool(np, "gpmc,time-para-granularity");
bc6b1e7b
DM		 1512}
1513
6b187b21 1514#if IS_ENABLED(CONFIG_MTD_NAND)
bc6b1e7b 1515
496c8a0b
MJ		 1516static const char * const nand_xfer_types[] = {
1517 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1518 [NAND_OMAP_POLLED] = "polled",
1519 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1520 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1521};
1522
bc6b1e7b
DM		 1523static int gpmc_probe_nand_child(struct platform_device *pdev,
1524 struct device_node *child)
1525{
1526 u32 val;
1527 const char *s;
1528 struct gpmc_timings gpmc_t;
1529 struct omap_nand_platform_data *gpmc_nand_data;
1530
1531 if (of_property_read_u32(child, "reg", &val) < 0) {
1532 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1533 child->full_name);
1534 return -ENODEV;
1535 }
1536
1537 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1538 GFP_KERNEL);
1539 if (!gpmc_nand_data)
1540 return -ENOMEM;
1541
1542 gpmc_nand_data->cs = val;
1543 gpmc_nand_data->of_node = child;
1544
ac65caf5
PG		 1545 /* Detect availability of ELM module */
1546 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1547 if (gpmc_nand_data->elm_of_node == NULL)
1548 gpmc_nand_data->elm_of_node =
1549 of_parse_phandle(child, "elm_id", 0);
1550 if (gpmc_nand_data->elm_of_node == NULL)
1551 pr_warn("%s: ti,elm-id property not found\n", __func__);
1552
1553 /* select ecc-scheme for NAND */
1554 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1555 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1556 return -ENODEV;
1557 }
a3e83f05
RQ		 1558
1559 if (!strcmp(s, "sw"))
1560 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1561 else if (!strcmp(s, "ham1") ||
1562 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
ac65caf5
PG		 1563 gpmc_nand_data->ecc_opt =
1564 OMAP_ECC_HAM1_CODE_HW;
1565 else if (!strcmp(s, "bch4"))
1566 if (gpmc_nand_data->elm_of_node)
1567 gpmc_nand_data->ecc_opt =
1568 OMAP_ECC_BCH4_CODE_HW;
1569 else
1570 gpmc_nand_data->ecc_opt =
1571 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1572 else if (!strcmp(s, "bch8"))
1573 if (gpmc_nand_data->elm_of_node)
1574 gpmc_nand_data->ecc_opt =
1575 OMAP_ECC_BCH8_CODE_HW;
1576 else
1577 gpmc_nand_data->ecc_opt =
1578 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
27c9fd60 1579 else if (!strcmp(s, "bch16"))
1580 if (gpmc_nand_data->elm_of_node)
1581 gpmc_nand_data->ecc_opt =
1582 OMAP_ECC_BCH16_CODE_HW;
1583 else
1584 pr_err("%s: BCH16 requires ELM support\n", __func__);
ac65caf5
PG		 1585 else
1586 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
bc6b1e7b 1587
ac65caf5 1588 /* select data transfer mode for NAND controller */
496c8a0b
MJ		 1589 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1590 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1591 if (!strcasecmp(s, nand_xfer_types[val])) {
1592 gpmc_nand_data->xfer_type = val;
1593 break;
1594 }
1595
fef775ca
EG		 1596 gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1597
bc6b1e7b
DM		 1598 val = of_get_nand_bus_width(child);
1599 if (val == 16)
1600 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1601
1602 gpmc_read_timings_dt(child, &gpmc_t);
1603 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1604
1605 return 0;
1606}
1607#else
1608static int gpmc_probe_nand_child(struct platform_device *pdev,
1609 struct device_node *child)
1610{
1611 return 0;
1612}
1613#endif
1614
980386d2 1615#if IS_ENABLED(CONFIG_MTD_ONENAND)
75d3625e
EG		 1616static int gpmc_probe_onenand_child(struct platform_device *pdev,
1617 struct device_node *child)
1618{
1619 u32 val;
1620 struct omap_onenand_platform_data *gpmc_onenand_data;
1621
1622 if (of_property_read_u32(child, "reg", &val) < 0) {
1623 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1624 child->full_name);
1625 return -ENODEV;
1626 }
1627
1628 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1629 GFP_KERNEL);
1630 if (!gpmc_onenand_data)
1631 return -ENOMEM;
1632
1633 gpmc_onenand_data->cs = val;
1634 gpmc_onenand_data->of_node = child;
1635 gpmc_onenand_data->dma_channel = -1;
1636
1637 if (!of_property_read_u32(child, "dma-channel", &val))
1638 gpmc_onenand_data->dma_channel = val;
1639
1640 gpmc_onenand_init(gpmc_onenand_data);
1641
1642 return 0;
1643}
1644#else
1645static int gpmc_probe_onenand_child(struct platform_device *pdev,
1646 struct device_node *child)
1647{
1648 return 0;
1649}
1650#endif
1651
cdd6928c 1652/**
3af91cf7 1653 * gpmc_probe_generic_child - configures the gpmc for a child device
cdd6928c 1654 * @pdev: pointer to gpmc platform device
3af91cf7 1655 * @child: pointer to device-tree node for child device
cdd6928c 1656 *
3af91cf7 1657 * Allocates and configures a GPMC chip-select for a child device.
cdd6928c
JH		 1658 * Returns 0 on success and appropriate negative error code on failure.
1659 */
3af91cf7 1660static int gpmc_probe_generic_child(struct platform_device *pdev,
cdd6928c
JH		 1661 struct device_node *child)
1662{
1663 struct gpmc_settings gpmc_s;
1664 struct gpmc_timings gpmc_t;
1665 struct resource res;
1666 unsigned long base;
9ed7a776 1667 const char *name;
cdd6928c 1668 int ret, cs;
e378d22b 1669 u32 val;
cdd6928c
JH		 1670
1671 if (of_property_read_u32(child, "reg", &cs) < 0) {
1672 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1673 child->full_name);
1674 return -ENODEV;
1675 }
1676
1677 if (of_address_to_resource(child, 0, &res) < 0) {
1678 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1679 child->full_name);
1680 return -ENODEV;
1681 }
1682
9ed7a776
TL		 1683 /*
1684 * Check if we have multiple instances of the same device
1685 * on a single chip select. If so, use the already initialized
1686 * timings.
1687 */
1688 name = gpmc_cs_get_name(cs);
1689 if (name && child->name && of_node_cmp(child->name, name) == 0)
1690 goto no_timings;
1691
cdd6928c
JH		 1692 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1693 if (ret < 0) {
1694 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1695 return ret;
1696 }
9ed7a776 1697 gpmc_cs_set_name(cs, child->name);
cdd6928c 1698
35ac051e
TL		 1699 gpmc_read_settings_dt(child, &gpmc_s);
1700 gpmc_read_timings_dt(child, &gpmc_t);
1701
1702 /*
1703 * For some GPMC devices we still need to rely on the bootloader
1704 * timings because the devices can be connected via FPGA.
1705 * REVISIT: Add timing support from slls644g.pdf.
1706 */
1707 if (!gpmc_t.cs_rd_off) {
1708 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1709 cs);
1710 gpmc_cs_show_timings(cs,
1711 "please add GPMC bootloader timings to .dts");
1712 goto no_timings;
1713 }
1714
4cf27d2e
RQ		 1715 /* CS must be disabled while making changes to gpmc configuration */
1716 gpmc_cs_disable_mem(cs);
1717
cdd6928c
JH		 1718 /*
1719 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1720 * location in the gpmc address space. When booting with
1721 * device-tree we want the NOR flash to be mapped to the
1722 * location specified in the device-tree blob. So remap the
1723 * CS to this location. Once DT migration is complete should
1724 * just make gpmc_cs_request() map a specific address.
1725 */
1726 ret = gpmc_cs_remap(cs, res.start);
1727 if (ret < 0) {
f70bf2a3
FE		 1728 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1729 cs, &res.start);
cdd6928c
JH		 1730 goto err;
1731 }
1732
cdd6928c
JH		 1733 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1734 if (ret < 0)
1735 goto err;
1736
1737 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1738 if (ret < 0)
1739 goto err;
1740
7604baf3
RQ		 1741 ret = gpmc_cs_set_timings(cs, &gpmc_t);
1742 if (ret) {
1743 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1744 child->name);
1745 goto err;
1746 }
cdd6928c 1747
e378d22b
RQ		 1748 /* Clear limited address i.e. enable A26-A11 */
1749 val = gpmc_read_reg(GPMC_CONFIG);
1750 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1751 gpmc_write_reg(GPMC_CONFIG, val);
1752
4cf27d2e
RQ		 1753 /* Enable CS region */
1754 gpmc_cs_enable_mem(cs);
cdd6928c 1755
fd4446f2 1756no_timings:
cdd6928c
JH		 1757 if (of_platform_device_create(child, NULL, &pdev->dev))
1758 return 0;
1759
1760 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
e8ffd6fd 1761 ret = -ENODEV;
cdd6928c
JH		 1762
1763err:
1764 gpmc_cs_free(cs);
1765
1766 return ret;
1767}
1768
bc6b1e7b
DM		 1769static int gpmc_probe_dt(struct platform_device *pdev)
1770{
1771 int ret;
1772 struct device_node *child;
1773 const struct of_device_id *of_id =
1774 of_match_device(gpmc_dt_ids, &pdev->dev);
1775
1776 if (!of_id)
1777 return 0;
1778
f34f3716
GP		 1779 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1780 &gpmc_cs_num);
1781 if (ret < 0) {
1782 pr_err("%s: number of chip-selects not defined\n", __func__);
1783 return ret;
1784 } else if (gpmc_cs_num < 1) {
1785 pr_err("%s: all chip-selects are disabled\n", __func__);
1786 return -EINVAL;
1787 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1788 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1789 __func__, GPMC_CS_NUM);
1790 return -EINVAL;
1791 }
1792
9f833156
JH		 1793 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1794 &gpmc_nr_waitpins);
1795 if (ret < 0) {
1796 pr_err("%s: number of wait pins not found!\n", __func__);
1797 return ret;
1798 }
1799
68e2eb53 1800 for_each_available_child_of_node(pdev->dev.of_node, child) {
bc6b1e7b 1801
f2b09f67
JMC		 1802 if (!child->name)
1803 continue;
cdd6928c 1804
f2b09f67
JMC		 1805 if (of_node_cmp(child->name, "nand") == 0)
1806 ret = gpmc_probe_nand_child(pdev, child);
1807 else if (of_node_cmp(child->name, "onenand") == 0)
1808 ret = gpmc_probe_onenand_child(pdev, child);
1809 else if (of_node_cmp(child->name, "ethernet") == 0 ||
fd4446f2
TL		 1810 of_node_cmp(child->name, "nor") == 0 ||
1811 of_node_cmp(child->name, "uart") == 0)
f2b09f67 1812 ret = gpmc_probe_generic_child(pdev, child);
cdd6928c 1813
b327b362
JMC		 1814 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1815 __func__, child->full_name))
5330dc16 1816 of_node_put(child);
5330dc16
JMC		 1817 }
1818
bc6b1e7b
DM		 1819 return 0;
1820}
1821#else
1822static int gpmc_probe_dt(struct platform_device *pdev)
1823{
1824 return 0;
1825}
1826#endif
1827
351a102d 1828static int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 1829{
8119024e 1830 int rc;
6b6c32fc 1831 u32 l;
da496873 1832 struct resource *res;
4bbbc1ad 1833
da496873
AM		 1834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1835 if (res == NULL)
1836 return -ENOENT;
8d08436d 1837
da496873
AM		 1838 phys_base = res->start;
1839 mem_size = resource_size(res);
fd1dc87d 1840
5857bd98
TR		 1841 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1842 if (IS_ERR(gpmc_base))
1843 return PTR_ERR(gpmc_base);
da496873
AM		 1844
1845 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1846 if (res == NULL)
1847 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1848 else
1849 gpmc_irq = res->start;
1850
8bf9be56 1851 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
da496873 1852 if (IS_ERR(gpmc_l3_clk)) {
8bf9be56 1853 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
da496873
AM		 1854 gpmc_irq = 0;
1855 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 1856 }
1857
8bf9be56
RQ		 1858 if (!clk_get_rate(gpmc_l3_clk)) {
1859 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
1860 return -EINVAL;
1861 }
1862
b3f5525c 1863 pm_runtime_enable(&pdev->dev);
1864 pm_runtime_get_sync(&pdev->dev);
1daa8c1d 1865
da496873
AM		 1866 gpmc_dev = &pdev->dev;
1867
4bbbc1ad 1868 l = gpmc_read_reg(GPMC_REVISION);
aa8d4767
JH		 1869
1870 /*
1871 * FIXME: Once device-tree migration is complete the below flags
1872 * should be populated based upon the device-tree compatible
1873 * string. For now just use the IP revision. OMAP3+ devices have
1874 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1875 * devices support the addr-addr-data multiplex protocol.
1876 *
1877 * GPMC IP revisions:
1878 * - OMAP24xx = 2.0
1879 * - OMAP3xxx = 5.0
1880 * - OMAP44xx/54xx/AM335x = 6.0
1881 */
da496873
AM		 1882 if (GPMC_REVISION_MAJOR(l) > 0x4)
1883 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
aa8d4767
JH		 1884 if (GPMC_REVISION_MAJOR(l) > 0x5)
1885 gpmc_capability |= GPMC_HAS_MUX_AAD;
da496873
AM		 1886 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1887 GPMC_REVISION_MINOR(l));
1888
84b00f0e 1889 gpmc_mem_init();
db97eb7d 1890
71856843 1891 if (gpmc_setup_irq() < 0)
da496873
AM		 1892 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1893
f34f3716
GP		 1894 if (!pdev->dev.of_node) {
1895 gpmc_cs_num = GPMC_CS_NUM;
9f833156 1896 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
f34f3716 1897 }
9f833156 1898
bc6b1e7b
DM		 1899 rc = gpmc_probe_dt(pdev);
1900 if (rc < 0) {
b3f5525c 1901 pm_runtime_put_sync(&pdev->dev);
bc6b1e7b
DM		 1902 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1903 return rc;
1904 }
1905
da496873
AM		 1906 return 0;
1907}
1908
351a102d 1909static int gpmc_remove(struct platform_device *pdev)
da496873
AM		 1910{
1911 gpmc_free_irq();
1912 gpmc_mem_exit();
b3f5525c 1913 pm_runtime_put_sync(&pdev->dev);
1914 pm_runtime_disable(&pdev->dev);
da496873
AM		 1915 gpmc_dev = NULL;
1916 return 0;
1917}
1918
b536dd41 1919#ifdef CONFIG_PM_SLEEP
1920static int gpmc_suspend(struct device *dev)
1921{
1922 omap3_gpmc_save_context();
1923 pm_runtime_put_sync(dev);
1924 return 0;
1925}
1926
1927static int gpmc_resume(struct device *dev)
1928{
1929 pm_runtime_get_sync(dev);
1930 omap3_gpmc_restore_context();
1931 return 0;
1932}
1933#endif
1934
1935static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1936
da496873
AM		 1937static struct platform_driver gpmc_driver = {
1938 .probe = gpmc_probe,
351a102d 1939 .remove = gpmc_remove,
da496873
AM		 1940 .driver = {
1941 .name = DEVICE_NAME,
1942 .owner = THIS_MODULE,
bc6b1e7b 1943 .of_match_table = of_match_ptr(gpmc_dt_ids),
b536dd41 1944 .pm = &gpmc_pm_ops,
da496873
AM		 1945 },
1946};
1947
1948static __init int gpmc_init(void)
1949{
1950 return platform_driver_register(&gpmc_driver);
1951}
1952
1953static __exit void gpmc_exit(void)
1954{
1955 platform_driver_unregister(&gpmc_driver);
1956
db97eb7d 1957}
da496873 1958
b76c8b19 1959omap_postcore_initcall(gpmc_init);
da496873 1960module_exit(gpmc_exit);
db97eb7d 1961
4be48fd5
AM		 1962static int __init omap_gpmc_init(void)
1963{
1964 struct omap_hwmod *oh;
1965 struct platform_device *pdev;
1966 char *oh_name = "gpmc";
1967
2f98ca89
DM		 1968 /*
1969 * if the board boots up with a populated DT, do not
1970 * manually add the device from this initcall
1971 */
1972 if (of_have_populated_dt())
1973 return -ENODEV;
1974
4be48fd5
AM		 1975 oh = omap_hwmod_lookup(oh_name);
1976 if (!oh) {
1977 pr_err("Could not look up %s\n", oh_name);
1978 return -ENODEV;
1979 }
1980
c1d1cd59 1981 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
4be48fd5
AM		 1982 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1983
1261674a 1984 return PTR_RET(pdev);
4be48fd5 1985}
b76c8b19 1986omap_postcore_initcall(omap_gpmc_init);
4be48fd5 1987
db97eb7d
SG		 1988static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1989{
6b6c32fc
AM		 1990 int i;
1991 u32 regval;
1992
1993 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1994
1995 if (!regval)
1996 return IRQ_NONE;
1997
1998 for (i = 0; i < GPMC_NR_IRQ; i++)
1999 if (regval & gpmc_client_irq[i].bitmask)
2000 generic_handle_irq(gpmc_client_irq[i].irq);
db97eb7d 2001
6b6c32fc 2002 gpmc_write_reg(GPMC_IRQSTATUS, regval);
db97eb7d
SG		 2003
2004 return IRQ_HANDLED;
4bbbc1ad 2005}
a2d3e7ba 2006
a2d3e7ba
RN		 2007static struct omap3_gpmc_regs gpmc_context;
2008
b2fa3b7c 2009void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 2010{
2011 int i;
b2fa3b7c 2012
a2d3e7ba
RN		 2013 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2014 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2015 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2016 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2017 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2018 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2019 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
f34f3716 2020 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2021 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2022 if (gpmc_context.cs_context[i].is_valid) {
2023 gpmc_context.cs_context[i].config1 =
2024 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2025 gpmc_context.cs_context[i].config2 =
2026 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2027 gpmc_context.cs_context[i].config3 =
2028 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2029 gpmc_context.cs_context[i].config4 =
2030 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2031 gpmc_context.cs_context[i].config5 =
2032 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2033 gpmc_context.cs_context[i].config6 =
2034 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2035 gpmc_context.cs_context[i].config7 =
2036 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2037 }
2038 }
2039}
2040
b2fa3b7c 2041void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 2042{
2043 int i;
b2fa3b7c 2044
a2d3e7ba
RN		 2045 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2046 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2047 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2048 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2049 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2050 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2051 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
f34f3716 2052 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2053 if (gpmc_context.cs_context[i].is_valid) {
2054 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2055 gpmc_context.cs_context[i].config1);
2056 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2057 gpmc_context.cs_context[i].config2);
2058 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2059 gpmc_context.cs_context[i].config3);
2060 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2061 gpmc_context.cs_context[i].config4);
2062 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2063 gpmc_context.cs_context[i].config5);
2064 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2065 gpmc_context.cs_context[i].config6);
2066 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2067 gpmc_context.cs_context[i].config7);
2068 }
2069 }
2070}
Linux kernel - Deliverables
This page took 0.723656 seconds and 5 git commands to generate.